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engicam: Set fdt_file env during run-time
[people/ms/u-boot.git] / board / sunxi / board.c
CommitLineData
cba69eee
IC		 1/*
2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some board init for the Allwinner A10-evb board.
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
e79c7c88 15#include <mmc.h>
6944aff1 16#include <axp_pmic.h>
cba69eee 17#include <asm/arch/clock.h>
b41d7d05 18#include <asm/arch/cpu.h>
2d7a084b 19#include <asm/arch/display.h>
cba69eee 20#include <asm/arch/dram.h>
e24ea55c
IC		 21#include <asm/arch/gpio.h>
22#include <asm/arch/mmc.h>
4a8c7c1f 23#include <asm/arch/spl.h>
2aacc423 24#include <asm/arch/usb_phy.h>
d96ebc46
SS		 25#ifndef CONFIG_ARM64
26#include <asm/armv7.h>
27#endif
4f7e01c9 28#include <asm/gpio.h>
b41d7d05 29#include <asm/io.h>
3f8ea3b0 30#include <crc.h>
4a8c7c1f 31#include <environment.h>
f221961e 32#include <libfdt.h>
f62bfa56 33#include <nand.h>
b41d7d05 34#include <net.h>
0d8382ae 35#include <sy8106a.h>
cba69eee 36
55410089
HG		 37#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39int soft_i2c_gpio_sda;
40int soft_i2c_gpio_scl;
4f7e01c9
HG		 41
42static int soft_i2c_board_init(void)
43{
44 int ret;
45
46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
47 if (soft_i2c_gpio_sda < 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
50 return soft_i2c_gpio_sda;
51 }
52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
53 if (ret) {
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
56 return ret;
57 }
58
59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
60 if (soft_i2c_gpio_scl < 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
63 return soft_i2c_gpio_scl;
64 }
65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
66 if (ret) {
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
69 return ret;
70 }
71
72 return 0;
73}
74#else
75static int soft_i2c_board_init(void) { return 0; }
55410089
HG		 76#endif
77
cba69eee
IC		 78DECLARE_GLOBAL_DATA_PTR;
79
acbc7e0a
JS		 80void i2c_init_board(void)
81{
82#ifdef CONFIG_I2C0_ENABLE
83#if defined(CONFIG_MACH_SUN4I) || \
84 defined(CONFIG_MACH_SUN5I) || \
85 defined(CONFIG_MACH_SUN7I) || \
86 defined(CONFIG_MACH_SUN8I_R40)
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
89 clock_twi_onoff(0, 1);
90#elif defined(CONFIG_MACH_SUN6I)
91 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
92 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
93 clock_twi_onoff(0, 1);
94#elif defined(CONFIG_MACH_SUN8I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
97 clock_twi_onoff(0, 1);
98#endif
99#endif
100
101#ifdef CONFIG_I2C1_ENABLE
102#if defined(CONFIG_MACH_SUN4I) || \
103 defined(CONFIG_MACH_SUN7I) || \
104 defined(CONFIG_MACH_SUN8I_R40)
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
107 clock_twi_onoff(1, 1);
108#elif defined(CONFIG_MACH_SUN5I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
111 clock_twi_onoff(1, 1);
112#elif defined(CONFIG_MACH_SUN6I)
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
115 clock_twi_onoff(1, 1);
116#elif defined(CONFIG_MACH_SUN8I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
119 clock_twi_onoff(1, 1);
120#endif
121#endif
122
123#ifdef CONFIG_I2C2_ENABLE
124#if defined(CONFIG_MACH_SUN4I) || \
125 defined(CONFIG_MACH_SUN7I) || \
126 defined(CONFIG_MACH_SUN8I_R40)
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
129 clock_twi_onoff(2, 1);
130#elif defined(CONFIG_MACH_SUN5I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
133 clock_twi_onoff(2, 1);
134#elif defined(CONFIG_MACH_SUN6I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
137 clock_twi_onoff(2, 1);
138#elif defined(CONFIG_MACH_SUN8I)
139 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
140 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
141 clock_twi_onoff(2, 1);
142#endif
143#endif
144
145#ifdef CONFIG_I2C3_ENABLE
146#if defined(CONFIG_MACH_SUN6I)
147 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
148 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
149 clock_twi_onoff(3, 1);
150#elif defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
153 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
154 clock_twi_onoff(3, 1);
155#endif
156#endif
157
158#ifdef CONFIG_I2C4_ENABLE
159#if defined(CONFIG_MACH_SUN7I) || \
160 defined(CONFIG_MACH_SUN8I_R40)
161 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
162 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
163 clock_twi_onoff(4, 1);
164#endif
165#endif
166
167#ifdef CONFIG_R_I2C_ENABLE
168 clock_twi_onoff(5, 1);
169 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
170 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
171#endif
172}
173
cba69eee
IC		 174/* add board specific code here */
175int board_init(void)
176{
f5fd7886 177 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
cba69eee
IC		 178
179 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
180
d96ebc46 181#ifndef CONFIG_ARM64
cba69eee
IC		 182 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
183 debug("id_pfr1: 0x%08x\n", id_pfr1);
184 /* Generic Timer Extension available? */
d96ebc46
SS		 185 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
186 uint32_t freq;
187
cba69eee 188 debug("Setting CNTFRQ\n");
d96ebc46
SS		 189
190 /*
191 * CNTFRQ is a secure register, so we will crash if we try to
192 * write this from the non-secure world (read is OK, though).
193 * In case some bootcode has already set the correct value,
194 * we avoid the risk of writing to it.
195 */
196 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
e4916e85 197 if (freq != COUNTER_FREQUENCY) {
d96ebc46 198 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
e4916e85 199 freq, COUNTER_FREQUENCY);
d96ebc46
SS		 200#ifdef CONFIG_NON_SECURE
201 printf("arch timer frequency is wrong, but cannot adjust it\n");
202#else
203 asm volatile("mcr p15, 0, %0, c14, c0, 0"
e4916e85 204 : : "r"(COUNTER_FREQUENCY));
d96ebc46
SS		 205#endif
206 }
cba69eee 207 }
d96ebc46 208#endif /* !CONFIG_ARM64 */
cba69eee 209
2fcf033d
HG		 210 ret = axp_gpio_init();
211 if (ret)
212 return ret;
213
9fbb0c3a 214#ifdef CONFIG_SATAPWR
d7b560e6
MJ		 215 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
216 gpio_request(satapwr_pin, "satapwr");
217 gpio_direction_output(satapwr_pin, 1);
9fbb0c3a 218#endif
fc8991c6 219#ifdef CONFIG_MACPWR
f5fd7886
MJ		 220 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
221 gpio_request(macpwr_pin, "macpwr");
222 gpio_direction_output(macpwr_pin, 1);
fc8991c6
HG		 223#endif
224
a8f01ccf
JS		 225#ifdef CONFIG_DM_I2C
226 /*
227 * Temporary workaround for enabling I2C clocks until proper sunxi DM
228 * clk, reset and pinctrl drivers land.
229 */
230 i2c_init_board();
231#endif
232
4f7e01c9
HG		 233 /* Uses dm gpio code so do this here and not in i2c_init_board() */
234 return soft_i2c_board_init();
cba69eee
IC		 235}
236
237int dram_init(void)
238{
239 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
240
241 return 0;
242}
243
4ccae81c 244#if defined(CONFIG_NAND_SUNXI)
ad008299
KG		 245static void nand_pinmux_setup(void)
246{
247 unsigned int pin;
ad008299 248
022a99d8 249 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
ad008299
KG		 250 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
251
022a99d8
HG		 252#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
253 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
254 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
255#endif
256 /* sun4i / sun7i do have a PC23, but it is not used for nand,
257 * only sun7i has a PC24 */
258#ifdef CONFIG_MACH_SUN7I
ad008299 259 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
022a99d8 260#endif
ad008299
KG		 261}
262
263static void nand_clock_setup(void)
264{
265 struct sunxi_ccm_reg *const ccm =
266 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
31c21471 267
ad008299 268 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
31c21471
HG		 269#ifdef CONFIG_MACH_SUN9I
270 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
271#else
272 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
273#endif
ad008299
KG		 274 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
275}
f62bfa56
HG		 276
277void board_nand_init(void)
278{
279 nand_pinmux_setup();
280 nand_clock_setup();
4ccae81c
BB		 281#ifndef CONFIG_SPL_BUILD
282 sunxi_nand_init();
283#endif
f62bfa56 284}
ad008299
KG		 285#endif
286
4aa2ba3a 287#ifdef CONFIG_MMC
e24ea55c
IC		 288static void mmc_pinmux_setup(int sdc)
289{
290 unsigned int pin;
8deacca9 291 __maybe_unused int pins;
e24ea55c
IC		 292
293 switch (sdc) {
294 case 0:
8deacca9 295 /* SDC0: PF0-PF5 */
e24ea55c 296 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
487b3277 297 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
e24ea55c
IC		 298 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
299 sunxi_gpio_set_drv(pin, 2);
300 }
301 break;
302
303 case 1:
8deacca9
PK		 304 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
305
8094a4a2
CYT		 306#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
307 defined(CONFIG_MACH_SUN8I_R40)
8deacca9
PK		 308 if (pins == SUNXI_GPIO_H) {
309 /* SDC1: PH22-PH-27 */
310 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
311 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
312 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
313 sunxi_gpio_set_drv(pin, 2);
314 }
315 } else {
316 /* SDC1: PG0-PG5 */
317 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
318 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
319 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
320 sunxi_gpio_set_drv(pin, 2);
321 }
322 }
323#elif defined(CONFIG_MACH_SUN5I)
324 /* SDC1: PG3-PG8 */
bbff84b3 325 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
487b3277 326 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
e24ea55c
IC		 327 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
328 sunxi_gpio_set_drv(pin, 2);
329 }
8deacca9
PK		 330#elif defined(CONFIG_MACH_SUN6I)
331 /* SDC1: PG0-PG5 */
332 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
333 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
334 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
335 sunxi_gpio_set_drv(pin, 2);
336 }
337#elif defined(CONFIG_MACH_SUN8I)
338 if (pins == SUNXI_GPIO_D) {
339 /* SDC1: PD2-PD7 */
340 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
341 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
342 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
343 sunxi_gpio_set_drv(pin, 2);
344 }
345 } else {
346 /* SDC1: PG0-PG5 */
347 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
348 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
349 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
350 sunxi_gpio_set_drv(pin, 2);
351 }
352 }
353#endif
e24ea55c
IC		 354 break;
355
356 case 2:
8deacca9
PK		 357 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
358
359#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
360 /* SDC2: PC6-PC11 */
e24ea55c 361 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487b3277 362 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
e24ea55c
IC		 363 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
364 sunxi_gpio_set_drv(pin, 2);
365 }
8deacca9
PK		 366#elif defined(CONFIG_MACH_SUN5I)
367 if (pins == SUNXI_GPIO_E) {
368 /* SDC2: PE4-PE9 */
369 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
370 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
371 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
372 sunxi_gpio_set_drv(pin, 2);
373 }
374 } else {
375 /* SDC2: PC6-PC15 */
376 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
377 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
378 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
379 sunxi_gpio_set_drv(pin, 2);
380 }
381 }
382#elif defined(CONFIG_MACH_SUN6I)
383 if (pins == SUNXI_GPIO_A) {
384 /* SDC2: PA9-PA14 */
385 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
386 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
387 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
388 sunxi_gpio_set_drv(pin, 2);
389 }
390 } else {
391 /* SDC2: PC6-PC15, PC24 */
392 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
393 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
394 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
395 sunxi_gpio_set_drv(pin, 2);
396 }
397
398 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
399 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
400 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
401 }
8094a4a2
CYT		 402#elif defined(CONFIG_MACH_SUN8I_R40)
403 /* SDC2: PC6-PC15, PC24 */
404 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
405 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
406 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
407 sunxi_gpio_set_drv(pin, 2);
408 }
409
410 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
411 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
412 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
d96ebc46 413#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
8deacca9
PK		 414 /* SDC2: PC5-PC6, PC8-PC16 */
415 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
416 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
417 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
418 sunxi_gpio_set_drv(pin, 2);
419 }
420
421 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
425 }
3ebb4567
PT		 426#elif defined(CONFIG_MACH_SUN9I)
427 /* SDC2: PC6-PC16 */
428 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
429 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
430 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
431 sunxi_gpio_set_drv(pin, 2);
432 }
8deacca9 433#endif
e24ea55c
IC		 434 break;
435
436 case 3:
8deacca9
PK		 437 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
438
8094a4a2
CYT		 439#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
440 defined(CONFIG_MACH_SUN8I_R40)
8deacca9 441 /* SDC3: PI4-PI9 */
e24ea55c 442 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
8deacca9 443 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
e24ea55c
IC		 444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
446 }
8deacca9
PK		 447#elif defined(CONFIG_MACH_SUN6I)
448 if (pins == SUNXI_GPIO_A) {
449 /* SDC3: PA9-PA14 */
450 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
451 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
454 }
455 } else {
456 /* SDC3: PC6-PC15, PC24 */
457 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
461 }
462
463 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
464 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
466 }
467#endif
e24ea55c
IC		 468 break;
469
470 default:
471 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
472 break;
473 }
474}
475
476int board_mmc_init(bd_t *bis)
477{
e79c7c88
HG		 478 __maybe_unused struct mmc *mmc0, *mmc1;
479 __maybe_unused char buf[512];
480
e24ea55c 481 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
e79c7c88
HG		 482 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
483 if (!mmc0)
484 return -1;
485
2ccfac01 486#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
e24ea55c 487 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
e79c7c88
HG		 488 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
489 if (!mmc1)
490 return -1;
491#endif
492
bf5b9b10 493#if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
e79c7c88 494 /*
bf5b9b10
DK		 495 * On systems with an emmc (mmc2), figure out if we are booting from
496 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
497 * are searched there first. Note we only do this for u-boot proper,
498 * not for the SPL, see spl_boot_device().
e79c7c88 499 */
ef36d9ae 500 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
bf5b9b10 501 /* Booting from emmc / mmc2, swap */
bcce53d0
SG		 502 mmc0->block_dev.devnum = 1;
503 mmc1->block_dev.devnum = 0;
bf5b9b10 504 }
e24ea55c
IC		 505#endif
506
507 return 0;
508}
509#endif
510
cba69eee
IC		 511#ifdef CONFIG_SPL_BUILD
512void sunxi_board_init(void)
513{
14bc66bd 514 int power_failed = 0;
cba69eee
IC		 515 unsigned long ramsize;
516
0d8382ae
JW		 517#ifdef CONFIG_SY8106A_POWER
518 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
519#endif
520
95ab8fee 521#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
795857df
CYT		 522 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
523 defined CONFIG_AXP818_POWER
6944aff1
HG		 524 power_failed = axp_init();
525
795857df
CYT		 526#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
527 defined CONFIG_AXP818_POWER
6944aff1 528 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
24289208 529#endif
6944aff1
HG		 530 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
531 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
95ab8fee 532#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
6944aff1 533 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
5c7f10fd 534#endif
795857df
CYT		 535#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
536 defined CONFIG_AXP818_POWER
6944aff1 537 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
14bc66bd
HN		 538#endif
539
795857df
CYT		 540#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
541 defined CONFIG_AXP818_POWER
6944aff1
HG		 542 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
543#endif
544 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
f3c5045a 545#if !defined(CONFIG_AXP152_POWER)
6944aff1
HG		 546 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
547#endif
548#ifdef CONFIG_AXP209_POWER
549 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
550#endif
551
795857df
CYT		 552#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
553 defined(CONFIG_AXP818_POWER)
3517a27d
CYT		 554 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
555 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
795857df 556#if !defined CONFIG_AXP809_POWER
3517a27d
CYT		 557 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
558 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
795857df 559#endif
6944aff1
HG		 560 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
561 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
562 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
563#endif
38491d9c
CYT		 564
565#ifdef CONFIG_AXP818_POWER
566 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
567 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
568 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
795857df
CYT		 569#endif
570
571#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
15278ccb 572 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
38491d9c 573#endif
6944aff1 574#endif
cba69eee
IC		 575 printf("DRAM:");
576 ramsize = sunxi_dram_init();
cd8b35d2 577 printf(" %d MiB\n", (int)(ramsize >> 20));
cba69eee
IC		 578 if (!ramsize)
579 hang();
14bc66bd
HN		 580
581 /*
582 * Only clock up the CPU to full speed if we are reasonably
583 * assured it's being powered with suitable core voltage
584 */
585 if (!power_failed)
e71b422b 586 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
14bc66bd
HN		 587 else
588 printf("Failed to set core voltage! Can't set CPU frequency\n");
cba69eee
IC		 589}
590#endif
b41d7d05 591
f1df758d
PK		 592#ifdef CONFIG_USB_GADGET
593int g_dnl_board_usb_cable_connected(void)
594{
5bfdca0d 595 return sunxi_usb_phy_vbus_detect(0);
f1df758d
PK		 596}
597#endif
598
9f852211
PK		 599#ifdef CONFIG_SERIAL_TAG
600void get_board_serial(struct tag_serialnr *serialnr)
601{
602 char *serial_string;
603 unsigned long long serial;
604
605 serial_string = getenv("serial#");
606
607 if (serial_string) {
608 serial = simple_strtoull(serial_string, NULL, 16);
609
610 serialnr->high = (unsigned int) (serial >> 32);
611 serialnr->low = (unsigned int) (serial & 0xffffffff);
612 } else {
613 serialnr->high = 0;
614 serialnr->low = 0;
615 }
616}
617#endif
618
af654d14
BN		 619/*
620 * Check the SPL header for the "sunxi" variant. If found: parse values
621 * that might have been passed by the loader ("fel" utility), and update
622 * the environment accordingly.
623 */
624static void parse_spl_header(const uint32_t spl_addr)
625{
d96ebc46 626 struct boot_file_head *spl = (void *)(ulong)spl_addr;
320e0570
BN		 627 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
628 return; /* signature mismatch, no usable header */
629
630 uint8_t spl_header_version = spl->spl_signature[3];
631 if (spl_header_version != SPL_HEADER_VERSION) {
af654d14
BN		 632 printf("sunxi SPL version mismatch: expected %u, got %u\n",
633 SPL_HEADER_VERSION, spl_header_version);
320e0570
BN		 634 return;
635 }
636 if (!spl->fel_script_address)
637 return;
638
639 if (spl->fel_uEnv_length != 0) {
640 /*
641 * data is expected in uEnv.txt compatible format, so "env
642 * import -t" the string(s) at fel_script_address right away.
643 */
5a74a391 644 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
320e0570
BN		 645 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
646 return;
af654d14 647 }
320e0570
BN		 648 /* otherwise assume .scr format (mkimage-type script) */
649 setenv_hex("fel_scriptaddr", spl->fel_script_address);
af654d14 650}
af654d14 651
f221961e
HG		 652/*
653 * Note this function gets called multiple times.
654 * It must not make any changes to env variables which already exist.
655 */
656static void setup_environment(const void *fdt)
b41d7d05 657{
8c816573 658 char serial_string[17] = { 0 };
cac5b1cc 659 unsigned int sid[4];
8c816573 660 uint8_t mac_addr[6];
f221961e
HG		 661 char ethaddr[16];
662 int i, ret;
af654d14 663
8c816573 664 ret = sunxi_get_sid(sid);
3f8ea3b0
HG		 665 if (ret == 0 && sid[0] != 0) {
666 /*
667 * The single words 1 - 3 of the SID have quite a few bits
668 * which are the same on many models, so we take a crc32
669 * of all 3 words, to get a more unique value.
670 *
671 * Note we only do this on newer SoCs as we cannot change
672 * the algorithm on older SoCs since those have been using
673 * fixed mac-addresses based on only using word 3 for a
674 * long time and changing a fixed mac-address with an
675 * u-boot update is not good.
676 */
677#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
678 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
679 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
680 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
681#endif
682
97322c3e
HG		 683 /* Ensure the NIC specific bytes of the mac are not all 0 */
684 if ((sid[3] & 0xffffff) == 0)
685 sid[3] |= 0x800000;
686
f221961e
HG		 687 for (i = 0; i < 4; i++) {
688 sprintf(ethaddr, "ethernet%d", i);
689 if (!fdt_get_alias(fdt, ethaddr))
690 continue;
691
692 if (i == 0)
693 strcpy(ethaddr, "ethaddr");
694 else
695 sprintf(ethaddr, "eth%daddr", i);
696
697 if (getenv(ethaddr))
698 continue;
699
8c816573 700 /* Non OUI / registered MAC address */
f221961e 701 mac_addr[0] = (i << 4) | 0x02;
8c816573
PK		 702 mac_addr[1] = (sid[0] >> 0) & 0xff;
703 mac_addr[2] = (sid[3] >> 24) & 0xff;
704 mac_addr[3] = (sid[3] >> 16) & 0xff;
705 mac_addr[4] = (sid[3] >> 8) & 0xff;
706 mac_addr[5] = (sid[3] >> 0) & 0xff;
707
f221961e 708 eth_setenv_enetaddr(ethaddr, mac_addr);
8c816573 709 }
b41d7d05 710
8c816573
PK		 711 if (!getenv("serial#")) {
712 snprintf(serial_string, sizeof(serial_string),
713 "%08x%08x", sid[0], sid[3]);
b41d7d05 714
8c816573
PK		 715 setenv("serial#", serial_string);
716 }
b41d7d05 717 }
f221961e
HG		 718}
719
f221961e
HG		 720int misc_init_r(void)
721{
722 __maybe_unused int ret;
723
f221961e
HG		 724 setenv("fel_booted", NULL);
725 setenv("fel_scriptaddr", NULL);
726 /* determine if we are running in FEL mode */
727 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
728 setenv("fel_booted", "1");
729 parse_spl_header(SPL_ADDR);
730 }
f221961e
HG		 731
732 setup_environment(gd->fdt_blob);
b41d7d05 733
1871a8ca 734#ifndef CONFIG_MACH_SUN9I
e13afeef
HG		 735 ret = sunxi_usb_phy_probe();
736 if (ret)
737 return ret;
1871a8ca 738#endif
d42faf31
HG		 739 sunxi_musb_board_init();
740
b41d7d05
JL		 741 return 0;
742}
2d7a084b 743
2d7a084b
LV		 744int ft_board_setup(void *blob, bd_t *bd)
745{
d75111a7
HG		 746 int __maybe_unused r;
747
f221961e
HG		 748 /*
749 * Call setup_environment again in case the boot fdt has
750 * ethernet aliases the u-boot copy does not have.
751 */
752 setup_environment(blob);
753
2d7a084b 754#ifdef CONFIG_VIDEO_DT_SIMPLEFB
d75111a7
HG		 755 r = sunxi_simplefb_setup(blob);
756 if (r)
757 return r;
2d7a084b 758#endif
d75111a7 759 return 0;
2d7a084b 760}
"Das U-Boot" Source Tree