[people/ms/u-boot.git] / board / sunxi / board.c

/*
 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some board init for the Allwinner A10-evb board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#ifdef CONFIG_AXP152_POWER
#include <axp152.h>
#endif
#ifdef CONFIG_AXP209_POWER
#include <axp209.h>
#endif
#ifdef CONFIG_AXP221_POWER
#include <axp221.h>
#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/display.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/usb_phy.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/usb/musb.h>
#include <net.h>

#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
int soft_i2c_gpio_sda;
int soft_i2c_gpio_scl;

static int soft_i2c_board_init(void)
{
	int ret;

	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
	if (soft_i2c_gpio_sda < 0) {
		printf("Error invalid soft i2c sda pin: '%s', err %d\n",
		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
		return soft_i2c_gpio_sda;
	}
	ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
	if (ret) {
		printf("Error requesting soft i2c sda pin: '%s', err %d\n",
		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
		return ret;
	}

	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
	if (soft_i2c_gpio_scl < 0) {
		printf("Error invalid soft i2c scl pin: '%s', err %d\n",
		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
		return soft_i2c_gpio_scl;
	}
	ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
	if (ret) {
		printf("Error requesting soft i2c scl pin: '%s', err %d\n",
		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
		return ret;
	}

	return 0;
}
#else
static int soft_i2c_board_init(void) { return 0; }
#endif

DECLARE_GLOBAL_DATA_PTR;

/* add board specific code here */
int board_init(void)
{
	int id_pfr1, ret;

	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);

	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
	debug("id_pfr1: 0x%08x\n", id_pfr1);
	/* Generic Timer Extension available? */
	if ((id_pfr1 >> 16) & 0xf) {
		debug("Setting CNTFRQ\n");
		/* CNTFRQ == 24 MHz */
		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
	}

	ret = axp_gpio_init();
	if (ret)
		return ret;

	/* Uses dm gpio code so do this here and not in i2c_init_board() */
	return soft_i2c_board_init();
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);

	return 0;
}

#ifdef CONFIG_GENERIC_MMC
static void mmc_pinmux_setup(int sdc)
{
	unsigned int pin;
	__maybe_unused int pins;

	switch (sdc) {
	case 0:
		/* SDC0: PF0-PF5 */
		for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
		break;

	case 1:
		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);

#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
		if (pins == SUNXI_GPIO_H) {
			/* SDC1: PH22-PH-27 */
			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		} else {
			/* SDC1: PG0-PG5 */
			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		}
#elif defined(CONFIG_MACH_SUN5I)
		/* SDC1: PG3-PG8 */
		for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
#elif defined(CONFIG_MACH_SUN6I)
		/* SDC1: PG0-PG5 */
		for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
#elif defined(CONFIG_MACH_SUN8I)
		if (pins == SUNXI_GPIO_D) {
			/* SDC1: PD2-PD7 */
			for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		} else {
			/* SDC1: PG0-PG5 */
			for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		}
#endif
		break;

	case 2:
		pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);

#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
		/* SDC2: PC6-PC11 */
		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
#elif defined(CONFIG_MACH_SUN5I)
		if (pins == SUNXI_GPIO_E) {
			/* SDC2: PE4-PE9 */
			for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		} else {
			/* SDC2: PC6-PC15 */
			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		}
#elif defined(CONFIG_MACH_SUN6I)
		if (pins == SUNXI_GPIO_A) {
			/* SDC2: PA9-PA14 */
			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		} else {
			/* SDC2: PC6-PC15, PC24 */
			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}

			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
		}
#elif defined(CONFIG_MACH_SUN8I)
		/* SDC2: PC5-PC6, PC8-PC16 */
		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}

		for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
#endif
		break;

	case 3:
		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);

#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
		/* SDC3: PI4-PI9 */
		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(pin, 2);
		}
#elif defined(CONFIG_MACH_SUN6I)
		if (pins == SUNXI_GPIO_A) {
			/* SDC3: PA9-PA14 */
			for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}
		} else {
			/* SDC3: PC6-PC15, PC24 */
			for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
				sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
				sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
				sunxi_gpio_set_drv(pin, 2);
			}

			sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
		}
#endif
		break;

	default:
		printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
		break;
	}
}

int board_mmc_init(bd_t *bis)
{
	__maybe_unused struct mmc *mmc0, *mmc1;
	__maybe_unused char buf[512];

	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
	mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
	if (!mmc0)
		return -1;

#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
	mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
	if (!mmc1)
		return -1;
#endif

#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
	/*
	 * Both mmc0 and mmc2 are bootable, figure out where we're booting
	 * from. Try mmc0 first, just like the brom does.
	 */
	if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
	    mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
		buf[12] = 0;
		if (strcmp(&buf[4], "eGON.BT0") == 0)
			return 0;
	}

	/* no bootable card in mmc0, so we must be booting from mmc2, swap */
	mmc0->block_dev.dev = 1;
	mmc1->block_dev.dev = 0;
#endif

	return 0;
}
#endif

void i2c_init_board(void)
{
#ifdef CONFIG_I2C0_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
	clock_twi_onoff(0, 1);
#elif defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
	clock_twi_onoff(0, 1);
#elif defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
	clock_twi_onoff(0, 1);
#endif
#endif

#ifdef CONFIG_I2C1_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
	clock_twi_onoff(1, 1);
#elif defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
	clock_twi_onoff(1, 1);
#elif defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
	clock_twi_onoff(1, 1);
#elif defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
	clock_twi_onoff(1, 1);
#endif
#endif

#ifdef CONFIG_I2C2_ENABLE
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
	clock_twi_onoff(2, 1);
#elif defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
	clock_twi_onoff(2, 1);
#elif defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
	clock_twi_onoff(2, 1);
#elif defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
	clock_twi_onoff(2, 1);
#endif
#endif

#ifdef CONFIG_I2C3_ENABLE
#if defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
	clock_twi_onoff(3, 1);
#elif defined(CONFIG_MACH_SUN7I)
	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
	clock_twi_onoff(3, 1);
#endif
#endif

#ifdef CONFIG_I2C4_ENABLE
#if defined(CONFIG_MACH_SUN7I)
	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
	clock_twi_onoff(4, 1);
#endif
#endif
}

#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
	int power_failed = 0;
	unsigned long ramsize;

#ifdef CONFIG_AXP152_POWER
	power_failed = axp152_init();
	power_failed |= axp152_set_dcdc2(1400);
	power_failed |= axp152_set_dcdc3(1500);
	power_failed |= axp152_set_dcdc4(1250);
	power_failed |= axp152_set_ldo2(3000);
#endif
#ifdef CONFIG_AXP209_POWER
	power_failed |= axp209_init();
	power_failed |= axp209_set_dcdc2(1400);
	power_failed |= axp209_set_dcdc3(1250);
	power_failed |= axp209_set_ldo2(3000);
	power_failed |= axp209_set_ldo3(2800);
	power_failed |= axp209_set_ldo4(2800);
#endif
#ifdef CONFIG_AXP221_POWER
	power_failed = axp221_init();
	power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
	power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
	power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
#ifdef CONFIG_MACH_SUN6I
	power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
#else
	power_failed |= axp221_set_dcdc4(0);    /* A23:unused */
#endif
	power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */
	power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
	power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
	power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
	power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
	power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
	power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
#endif

	printf("DRAM:");
	ramsize = sunxi_dram_init();
	printf(" %lu MiB\n", ramsize >> 20);
	if (!ramsize)
		hang();

	/*
	 * Only clock up the CPU to full speed if we are reasonably
	 * assured it's being powered with suitable core voltage
	 */
	if (!power_failed)
		clock_set_pll1(CONFIG_SYS_CLK_FREQ);
	else
		printf("Failed to set core voltage! Can't set CPU frequency\n");
}
#endif

#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
extern const struct musb_platform_ops sunxi_musb_ops;

static struct musb_hdrc_config musb_config = {
	.multipoint     = 1,
	.dyn_fifo       = 1,
	.num_eps        = 6,
	.ram_bits       = 11,
};

static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_MUSB_HOST)
	.mode           = MUSB_HOST,
#else
	.mode		= MUSB_PERIPHERAL,
#endif
	.config         = &musb_config,
	.power          = 250,
	.platform_ops	= &sunxi_musb_ops,
};
#endif

#ifdef CONFIG_USB_GADGET
int g_dnl_board_usb_cable_connected(void)
{
	return sunxi_usb_phy_vbus_detect(0);
}
#endif

#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
	char *serial_string;
	unsigned long long serial;

	serial_string = getenv("serial#");

	if (serial_string) {
		serial = simple_strtoull(serial_string, NULL, 16);

		serialnr->high = (unsigned int) (serial >> 32);
		serialnr->low = (unsigned int) (serial & 0xffffffff);
	} else {
		serialnr->high = 0;
		serialnr->low = 0;
	}
}
#endif

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	char serial_string[17] = { 0 };
	unsigned int sid[4];
	uint8_t mac_addr[6];
	int ret;

	ret = sunxi_get_sid(sid);
	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
		if (!getenv("ethaddr")) {
			/* Non OUI / registered MAC address */
			mac_addr[0] = 0x02;
			mac_addr[1] = (sid[0] >>  0) & 0xff;
			mac_addr[2] = (sid[3] >> 24) & 0xff;
			mac_addr[3] = (sid[3] >> 16) & 0xff;
			mac_addr[4] = (sid[3] >>  8) & 0xff;
			mac_addr[5] = (sid[3] >>  0) & 0xff;

			eth_setenv_enetaddr("ethaddr", mac_addr);
		}

		if (!getenv("serial#")) {
			snprintf(serial_string, sizeof(serial_string),
				"%08x%08x", sid[0], sid[3]);

			setenv("serial#", serial_string);
		}
	}

#ifndef CONFIG_MACH_SUN9I
	ret = sunxi_usb_phy_probe();
	if (ret)
		return ret;
#endif
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
	musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
#endif
	return 0;
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
	return sunxi_simplefb_setup(blob);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	4	*
	5	* (C) Copyright 2007-2011
	6	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	7	* Tom Cubie <tangliang@allwinnertech.com>
	8	*
	9	* Some board init for the Allwinner A10-evb board.
	10	*
	11	* SPDX-License-Identifier: GPL-2.0+
	12	*/
	13
	14	#include <common.h>
e79c7c88	15	#include <mmc.h>
24289208 HG	16	#ifdef CONFIG_AXP152_POWER
	17	#include <axp152.h>
	18	#endif
14bc66bd HN	19	#ifdef CONFIG_AXP209_POWER
	20	#include <axp209.h>
	21	#endif
5c7f10fd OS	22	#ifdef CONFIG_AXP221_POWER
	23	#include <axp221.h>
	24	#endif
cba69eee	25	#include <asm/arch/clock.h>
b41d7d05	26	#include <asm/arch/cpu.h>
2d7a084b	27	#include <asm/arch/display.h>
cba69eee	28	#include <asm/arch/dram.h>
e24ea55c IC	29	#include <asm/arch/gpio.h>
e24ea55c IC	30	#include <asm/arch/mmc.h>
2aacc423	31	#include <asm/arch/usb_phy.h>
4f7e01c9	32	#include <asm/gpio.h>
b41d7d05	33	#include <asm/io.h>
1a800f7a	34	#include <linux/usb/musb.h>
b41d7d05	35	#include <net.h>
cba69eee	36
55410089 HG	37	#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
	38	/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
	39	int soft_i2c_gpio_sda;
	40	int soft_i2c_gpio_scl;
4f7e01c9 HG	41
	42	static int soft_i2c_board_init(void)
	43	{
	44	int ret;
	45
	46	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
	47	if (soft_i2c_gpio_sda < 0) {
	48	printf("Error invalid soft i2c sda pin: '%s', err %d\n",
	49	CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
	50	return soft_i2c_gpio_sda;
	51	}
	52	ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
	53	if (ret) {
	54	printf("Error requesting soft i2c sda pin: '%s', err %d\n",
	55	CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
	56	return ret;
	57	}
	58
	59	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
	60	if (soft_i2c_gpio_scl < 0) {
	61	printf("Error invalid soft i2c scl pin: '%s', err %d\n",
	62	CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
	63	return soft_i2c_gpio_scl;
	64	}
	65	ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
	66	if (ret) {
	67	printf("Error requesting soft i2c scl pin: '%s', err %d\n",
	68	CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
	69	return ret;
	70	}
	71
	72	return 0;
	73	}
	74	#else
	75	static int soft_i2c_board_init(void) { return 0; }
55410089 HG	76	#endif
55410089 HG	77
cba69eee IC	78	DECLARE_GLOBAL_DATA_PTR;
	79
	80	/* add board specific code here */
	81	int board_init(void)
	82	{
2fcf033d	83	int id_pfr1, ret;
cba69eee IC	84
	85	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
	86
	87	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
	88	debug("id_pfr1: 0x%08x\n", id_pfr1);
	89	/* Generic Timer Extension available? */
	90	if ((id_pfr1 >> 16) & 0xf) {
	91	debug("Setting CNTFRQ\n");
	92	/* CNTFRQ == 24 MHz */
	93	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
	94	}
	95
2fcf033d HG	96	ret = axp_gpio_init();
	97	if (ret)
	98	return ret;
	99
4f7e01c9 HG	100	/* Uses dm gpio code so do this here and not in i2c_init_board() */
4f7e01c9 HG	101	return soft_i2c_board_init();
cba69eee IC	102	}
	103
	104	int dram_init(void)
	105	{
	106	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
	107
	108	return 0;
	109	}
	110
e24ea55c IC	111	#ifdef CONFIG_GENERIC_MMC
	112	static void mmc_pinmux_setup(int sdc)
	113	{
	114	unsigned int pin;
8deacca9	115	__maybe_unused int pins;
e24ea55c IC	116
	117	switch (sdc) {
	118	case 0:
8deacca9	119	/* SDC0: PF0-PF5 */
e24ea55c	120	for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
487b3277	121	sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
e24ea55c IC	122	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	123	sunxi_gpio_set_drv(pin, 2);
	124	}
	125	break;
	126
	127	case 1:
8deacca9 PK	128	pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
	129
	130	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
	131	if (pins == SUNXI_GPIO_H) {
	132	/* SDC1: PH22-PH-27 */
	133	for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
	134	sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
	135	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	136	sunxi_gpio_set_drv(pin, 2);
	137	}
	138	} else {
	139	/* SDC1: PG0-PG5 */
	140	for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
	141	sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
	142	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	143	sunxi_gpio_set_drv(pin, 2);
	144	}
	145	}
	146	#elif defined(CONFIG_MACH_SUN5I)
	147	/* SDC1: PG3-PG8 */
bbff84b3	148	for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
487b3277	149	sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
e24ea55c IC	150	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	151	sunxi_gpio_set_drv(pin, 2);
	152	}
8deacca9 PK	153	#elif defined(CONFIG_MACH_SUN6I)
	154	/* SDC1: PG0-PG5 */
	155	for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
	156	sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
	157	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	158	sunxi_gpio_set_drv(pin, 2);
	159	}
	160	#elif defined(CONFIG_MACH_SUN8I)
	161	if (pins == SUNXI_GPIO_D) {
	162	/* SDC1: PD2-PD7 */
	163	for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
	164	sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
	165	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	166	sunxi_gpio_set_drv(pin, 2);
	167	}
	168	} else {
	169	/* SDC1: PG0-PG5 */
	170	for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
	171	sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
	172	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	173	sunxi_gpio_set_drv(pin, 2);
	174	}
	175	}
	176	#endif
e24ea55c IC	177	break;
	178
	179	case 2:
8deacca9 PK	180	pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
	181
	182	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
	183	/* SDC2: PC6-PC11 */
e24ea55c	184	for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487b3277	185	sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
e24ea55c IC	186	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	187	sunxi_gpio_set_drv(pin, 2);
	188	}
8deacca9 PK	189	#elif defined(CONFIG_MACH_SUN5I)
	190	if (pins == SUNXI_GPIO_E) {
	191	/* SDC2: PE4-PE9 */
	192	for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
	193	sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
	194	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	195	sunxi_gpio_set_drv(pin, 2);
	196	}
	197	} else {
	198	/* SDC2: PC6-PC15 */
	199	for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
	200	sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
	201	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	202	sunxi_gpio_set_drv(pin, 2);
	203	}
	204	}
	205	#elif defined(CONFIG_MACH_SUN6I)
	206	if (pins == SUNXI_GPIO_A) {
	207	/* SDC2: PA9-PA14 */
	208	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
	209	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
	210	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	211	sunxi_gpio_set_drv(pin, 2);
	212	}
	213	} else {
	214	/* SDC2: PC6-PC15, PC24 */
	215	for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
	216	sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
	217	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	218	sunxi_gpio_set_drv(pin, 2);
	219	}
	220
	221	sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
	222	sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
	223	sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
	224	}
	225	#elif defined(CONFIG_MACH_SUN8I)
	226	/* SDC2: PC5-PC6, PC8-PC16 */
	227	for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
	228	sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
	229	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	230	sunxi_gpio_set_drv(pin, 2);
	231	}
	232
	233	for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
	234	sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
	235	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	236	sunxi_gpio_set_drv(pin, 2);
	237	}
	238	#endif
e24ea55c IC	239	break;
	240
	241	case 3:
8deacca9 PK	242	pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
	243
	244	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
	245	/* SDC3: PI4-PI9 */
e24ea55c	246	for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
8deacca9	247	sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
e24ea55c IC	248	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	249	sunxi_gpio_set_drv(pin, 2);
	250	}
8deacca9 PK	251	#elif defined(CONFIG_MACH_SUN6I)
	252	if (pins == SUNXI_GPIO_A) {
	253	/* SDC3: PA9-PA14 */
	254	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
	255	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
	256	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	257	sunxi_gpio_set_drv(pin, 2);
	258	}
	259	} else {
	260	/* SDC3: PC6-PC15, PC24 */
	261	for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
	262	sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
	263	sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
	264	sunxi_gpio_set_drv(pin, 2);
	265	}
	266
	267	sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
	268	sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
	269	sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
	270	}
	271	#endif
e24ea55c IC	272	break;
	273
	274	default:
	275	printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
	276	break;
	277	}
	278	}
	279
	280	int board_mmc_init(bd_t *bis)
	281	{
e79c7c88 HG	282	__maybe_unused struct mmc mmc0, mmc1;
	283	__maybe_unused char buf[512];
	284
e24ea55c	285	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
e79c7c88 HG	286	mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
	287	if (!mmc0)
	288	return -1;
	289
2ccfac01	290	#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
e24ea55c	291	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
e79c7c88 HG	292	mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
	293	if (!mmc1)
	294	return -1;
	295	#endif
	296
	297	#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
	298	/*
	299	* Both mmc0 and mmc2 are bootable, figure out where we're booting
	300	* from. Try mmc0 first, just like the brom does.
	301	*/
	302	if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
	303	mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
	304	buf[12] = 0;
	305	if (strcmp(&buf[4], "eGON.BT0") == 0)
	306	return 0;
	307	}
	308
	309	/* no bootable card in mmc0, so we must be booting from mmc2, swap */
	310	mmc0->block_dev.dev = 1;
	311	mmc1->block_dev.dev = 0;
e24ea55c IC	312	#endif
	313
	314	return 0;
	315	}
	316	#endif
	317
6620377e HG	318	void i2c_init_board(void)
6620377e HG	319	{
6c739c5d PK	320	#ifdef CONFIG_I2C0_ENABLE
	321	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN5I) \|\| defined(CONFIG_MACH_SUN7I)
	322	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
	323	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
6620377e	324	clock_twi_onoff(0, 1);
6c739c5d PK	325	#elif defined(CONFIG_MACH_SUN6I)
	326	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
	327	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
	328	clock_twi_onoff(0, 1);
	329	#elif defined(CONFIG_MACH_SUN8I)
	330	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
	331	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
	332	clock_twi_onoff(0, 1);
	333	#endif
	334	#endif
	335
	336	#ifdef CONFIG_I2C1_ENABLE
	337	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
	338	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
	339	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
	340	clock_twi_onoff(1, 1);
	341	#elif defined(CONFIG_MACH_SUN5I)
	342	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
	343	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
	344	clock_twi_onoff(1, 1);
	345	#elif defined(CONFIG_MACH_SUN6I)
	346	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
	347	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
	348	clock_twi_onoff(1, 1);
	349	#elif defined(CONFIG_MACH_SUN8I)
	350	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
	351	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
	352	clock_twi_onoff(1, 1);
	353	#endif
	354	#endif
	355
	356	#ifdef CONFIG_I2C2_ENABLE
	357	#if defined(CONFIG_MACH_SUN4I) \|\| defined(CONFIG_MACH_SUN7I)
	358	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
	359	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
	360	clock_twi_onoff(2, 1);
	361	#elif defined(CONFIG_MACH_SUN5I)
	362	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
	363	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
	364	clock_twi_onoff(2, 1);
	365	#elif defined(CONFIG_MACH_SUN6I)
	366	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
	367	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
	368	clock_twi_onoff(2, 1);
	369	#elif defined(CONFIG_MACH_SUN8I)
	370	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
	371	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
	372	clock_twi_onoff(2, 1);
	373	#endif
	374	#endif
	375
	376	#ifdef CONFIG_I2C3_ENABLE
	377	#if defined(CONFIG_MACH_SUN6I)
	378	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
	379	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
	380	clock_twi_onoff(3, 1);
	381	#elif defined(CONFIG_MACH_SUN7I)
	382	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
	383	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
	384	clock_twi_onoff(3, 1);
	385	#endif
	386	#endif
	387
	388	#ifdef CONFIG_I2C4_ENABLE
389	#if defined(CONFIG_MACH_SUN7I)
390	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
391	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
392	clock_twi_onoff(4, 1);
393	#endif
394	#endif
6620377e HG	395	}
6620377e HG	396
cba69eee IC	397	#ifdef CONFIG_SPL_BUILD
	398	void sunxi_board_init(void)
	399	{
14bc66bd	400	int power_failed = 0;
cba69eee IC	401	unsigned long ramsize;
cba69eee IC	402
24289208 HG	403	#ifdef CONFIG_AXP152_POWER
	404	power_failed = axp152_init();
	405	power_failed \|= axp152_set_dcdc2(1400);
	406	power_failed \|= axp152_set_dcdc3(1500);
	407	power_failed \|= axp152_set_dcdc4(1250);
	408	power_failed \|= axp152_set_ldo2(3000);
	409	#endif
14bc66bd HN	410	#ifdef CONFIG_AXP209_POWER
	411	power_failed \|= axp209_init();
	412	power_failed \|= axp209_set_dcdc2(1400);
	413	power_failed \|= axp209_set_dcdc3(1250);
	414	power_failed \|= axp209_set_ldo2(3000);
	415	power_failed \|= axp209_set_ldo3(2800);
	416	power_failed \|= axp209_set_ldo4(2800);
5c7f10fd OS	417	#endif
	418	#ifdef CONFIG_AXP221_POWER
	419	power_failed = axp221_init();
1262a85f	420	power_failed \|= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
d3a96f7a HG	421	power_failed \|= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
	422	power_failed \|= axp221_set_dcdc3(1200); /* VDD-CPU */
	423	#ifdef CONFIG_MACH_SUN6I
	424	power_failed \|= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
	425	#else
	426	power_failed \|= axp221_set_dcdc4(0); /* A23:unused */
	427	#endif
	428	power_failed \|= axp221_set_dcdc5(1500); /* VCC-DRAM */
5c7f10fd	429	power_failed \|= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
5c7f10fd	430	power_failed \|= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
5c7f10fd	431	power_failed \|= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
5c7f10fd	432	power_failed \|= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
5c7f10fd	433	power_failed \|= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
6906df1a	434	power_failed \|= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
14bc66bd HN	435	#endif
14bc66bd HN	436
cba69eee IC	437	printf("DRAM:");
	438	ramsize = sunxi_dram_init();
	439	printf(" %lu MiB\n", ramsize >> 20);
	440	if (!ramsize)
	441	hang();
14bc66bd HN	442
	443	/*
	444	* Only clock up the CPU to full speed if we are reasonably
	445	* assured it's being powered with suitable core voltage
	446	*/
	447	if (!power_failed)
e71b422b	448	clock_set_pll1(CONFIG_SYS_CLK_FREQ);
14bc66bd HN	449	else
14bc66bd HN	450	printf("Failed to set core voltage! Can't set CPU frequency\n");
cba69eee IC	451	}
cba69eee IC	452	#endif
b41d7d05	453
1a800f7a	454	#if defined(CONFIG_MUSB_HOST) \|\| defined(CONFIG_MUSB_GADGET)
7b798658 HG	455	extern const struct musb_platform_ops sunxi_musb_ops;
7b798658 HG	456
1a800f7a HG	457	static struct musb_hdrc_config musb_config = {
	458	.multipoint = 1,
	459	.dyn_fifo = 1,
	460	.num_eps = 6,
	461	.ram_bits = 11,
	462	};
	463
	464	static struct musb_hdrc_platform_data musb_plat = {
	465	#if defined(CONFIG_MUSB_HOST)
	466	.mode = MUSB_HOST,
	467	#else
	468	.mode = MUSB_PERIPHERAL,
	469	#endif
	470	.config = &musb_config,
	471	.power = 250,
	472	.platform_ops = &sunxi_musb_ops,
	473	};
	474	#endif
	475
f1df758d PK	476	#ifdef CONFIG_USB_GADGET
	477	int g_dnl_board_usb_cable_connected(void)
	478	{
5bfdca0d	479	return sunxi_usb_phy_vbus_detect(0);
f1df758d PK	480	}
	481	#endif
	482
9f852211 PK	483	#ifdef CONFIG_SERIAL_TAG
	484	void get_board_serial(struct tag_serialnr *serialnr)
	485	{
	486	char *serial_string;
	487	unsigned long long serial;
	488
	489	serial_string = getenv("serial#");
	490
	491	if (serial_string) {
	492	serial = simple_strtoull(serial_string, NULL, 16);
	493
	494	serialnr->high = (unsigned int) (serial >> 32);
	495	serialnr->low = (unsigned int) (serial & 0xffffffff);
	496	} else {
	497	serialnr->high = 0;
	498	serialnr->low = 0;
	499	}
	500	}
	501	#endif
	502
b41d7d05 JL	503	#ifdef CONFIG_MISC_INIT_R
	504	int misc_init_r(void)
	505	{
8c816573	506	char serial_string[17] = { 0 };
cac5b1cc	507	unsigned int sid[4];
8c816573 PK	508	uint8_t mac_addr[6];
	509	int ret;
	510
	511	ret = sunxi_get_sid(sid);
	512	if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
	513	if (!getenv("ethaddr")) {
	514	/* Non OUI / registered MAC address */
	515	mac_addr[0] = 0x02;
	516	mac_addr[1] = (sid[0] >> 0) & 0xff;
	517	mac_addr[2] = (sid[3] >> 24) & 0xff;
	518	mac_addr[3] = (sid[3] >> 16) & 0xff;
	519	mac_addr[4] = (sid[3] >> 8) & 0xff;
	520	mac_addr[5] = (sid[3] >> 0) & 0xff;
	521
	522	eth_setenv_enetaddr("ethaddr", mac_addr);
	523	}
b41d7d05	524
8c816573 PK	525	if (!getenv("serial#")) {
	526	snprintf(serial_string, sizeof(serial_string),
	527	"%08x%08x", sid[0], sid[3]);
b41d7d05	528
8c816573 PK	529	setenv("serial#", serial_string);
8c816573 PK	530	}
b41d7d05 JL	531	}
b41d7d05 JL	532
1871a8ca	533	#ifndef CONFIG_MACH_SUN9I
e13afeef HG	534	ret = sunxi_usb_phy_probe();
	535	if (ret)
	536	return ret;
1871a8ca	537	#endif
1a800f7a HG	538	#if defined(CONFIG_MUSB_HOST) \|\| defined(CONFIG_MUSB_GADGET)
	539	musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
	540	#endif
b41d7d05 JL	541	return 0;
	542	}
	543	#endif
2d7a084b LV	544
	545	#ifdef CONFIG_OF_BOARD_SETUP
	546	int ft_board_setup(void blob, bd_t bd)
	547	{
	548	#ifdef CONFIG_VIDEO_DT_SIMPLEFB
	549	return sunxi_simplefb_setup(blob);
	550	#endif
	551	}
	552	#endif /* CONFIG_OF_BOARD_SETUP */