[people/ms/u-boot.git] / board / sunxi / gmac.c

#include <common.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>

int sunxi_gmac_initialize(bd_t *bis)
{
	int pin;
	struct sunxi_ccm_reg *const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

	/* Set up clock gating */
#ifdef CONFIG_SUNXI_GEN_SUN6I
	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
#else
	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
#endif

	/* Set MII clock */
#ifdef CONFIG_RGMII
	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
		CCM_GMAC_CTRL_GPIT_RGMII);
	setbits_le32(&ccm->gmac_clk_cfg,
		     CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
#else
	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
		CCM_GMAC_CTRL_GPIT_MII);
#endif

#ifndef CONFIG_MACH_SUN6I
	/* Configure pin mux settings for GMAC */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
		/* skip unused pins in RGMII mode */
		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
			continue;
#endif
		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
#elif defined CONFIG_RGMII
	/* Configure sun6i RGMII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 3);
	}
#elif defined CONFIG_GMII
	/* Configure sun6i GMII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
		sunxi_gpio_set_drv(pin, 2);
	}
#else
	/* Configure sun6i MII mode pin mux settings */
	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif

#ifdef CONFIG_DM_ETH
	return 0;
#else
# ifdef CONFIG_RGMII
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
# elif defined CONFIG_GMII
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
# else
	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
# endif
#endif
}
Commit	Line	Data
5835823d IC	1	#include <common.h>
	2	#include <netdev.h>
	3	#include <miiphy.h>
	4	#include <asm/gpio.h>
	5	#include <asm/io.h>
	6	#include <asm/arch/clock.h>
	7	#include <asm/arch/gpio.h>
	8
	9	int sunxi_gmac_initialize(bd_t *bis)
	10	{
	11	int pin;
	12	struct sunxi_ccm_reg *const ccm =
	13	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	14
	15	/* Set up clock gating */
44d8ae5b	16	#ifdef CONFIG_SUNXI_GEN_SUN6I
eafec320 HG	17	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
eafec320 HG	18	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
44d8ae5b HG	19	#else
44d8ae5b HG	20	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
eafec320	21	#endif
5835823d IC	22
5835823d IC	23	/* Set MII clock */
ef7e723b	24	#ifdef CONFIG_RGMII
5835823d IC	25	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII \|
5835823d IC	26	CCM_GMAC_CTRL_GPIT_RGMII);
c13f60d9 HG	27	setbits_le32(&ccm->gmac_clk_cfg,
c13f60d9 HG	28	CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
ef7e723b CYT	29	#else
	30	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII \|
	31	CCM_GMAC_CTRL_GPIT_MII);
	32	#endif
5835823d	33
eafec320	34	#ifndef CONFIG_MACH_SUN6I
5835823d IC	35	/* Configure pin mux settings for GMAC */
5835823d IC	36	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
ef7e723b	37	#ifdef CONFIG_RGMII
5835823d IC	38	/* skip unused pins in RGMII mode */
	39	if (pin == SUNXI_GPA(9) \|\| pin == SUNXI_GPA(14))
	40	continue;
ef7e723b	41	#endif
487b3277	42	sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
5835823d IC	43	sunxi_gpio_set_drv(pin, 3);
5835823d IC	44	}
eafec320 HG	45	#elif defined CONFIG_RGMII
	46	/* Configure sun6i RGMII mode pin mux settings */
	47	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
487b3277	48	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320 HG	49	sunxi_gpio_set_drv(pin, 3);
	50	}
	51	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
487b3277	52	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320 HG	53	sunxi_gpio_set_drv(pin, 3);
	54	}
	55	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
487b3277	56	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320 HG	57	sunxi_gpio_set_drv(pin, 3);
	58	}
	59	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
487b3277	60	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320 HG	61	sunxi_gpio_set_drv(pin, 3);
	62	}
	63	#elif defined CONFIG_GMII
	64	/* Configure sun6i GMII mode pin mux settings */
	65	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
487b3277	66	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320 HG	67	sunxi_gpio_set_drv(pin, 2);
	68	}
	69	#else
	70	/* Configure sun6i MII mode pin mux settings */
	71	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
487b3277	72	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320	73	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
487b3277	74	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320	75	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
487b3277	76	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320	77	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
487b3277	78	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320	79	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
487b3277	80	sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
eafec320	81	#endif
5835823d	82
5b4c6f29 SG	83	#ifdef CONFIG_DM_ETH
	84	return 0;
	85	#else
	86	# ifdef CONFIG_RGMII
5835823d	87	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
5b4c6f29	88	# elif defined CONFIG_GMII
eafec320	89	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
5b4c6f29	90	# else
ef7e723b	91	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
5b4c6f29	92	# endif
ef7e723b	93	#endif
5835823d	94	}