[people/ms/u-boot.git] / board / synopsys / axs101 / axs101.c

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <malloc.h>
#include <netdev.h>
#include <phy.h>
#include "axs10x.h"

DECLARE_GLOBAL_DATA_PTR;

int board_mmc_init(bd_t *bis)
{
	struct dwmci_host *host = NULL;

	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		printf("dwmci_host malloc fail!\n");
		return 1;
	}

	memset(host, 0, sizeof(struct dwmci_host));
	host->name = "Synopsys Mobile storage";
	host->ioaddr = (void *)ARC_DWMMC_BASE;
	host->buswidth = 4;
	host->dev_index = 0;
	host->bus_hz = 50000000;

	add_dwmci(host, host->bus_hz, 400000);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	if (designware_initialize(ARC_DWGMAC_BASE,
				  PHY_INTERFACE_MODE_RGMII) >= 0)
		return 1;

	return 0;
}


#define AXS_MB_CREG	0xE0011000

int board_early_init_f(void)
{
	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
		gd->board_type = AXS_MB_V3;
	else
		gd->board_type = AXS_MB_V2;

	return 0;
}

#ifdef CONFIG_ISA_ARCV2
#define RESET_VECTOR_ADDR	0x0

void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
	/* All cores have reset vector pointing to 0 */
	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);

	/* Make sure other cores see written value in memory */
	flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
}

void smp_kick_all_cpus(void)
{
/* CPU start CREG */
#define AXC003_CREG_CPU_START	0xF0001400

/* Bits positions in CPU start CREG */
#define BITS_START	0
#define BITS_POLARITY	8
#define BITS_CORE_SEL	9
#define BITS_MULTICORE	12

#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
		(1 << BITS_POLARITY) | (1 << BITS_START)

	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
}
#endif
Commit	Line	Data
a7069ddf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dwmmc.h>
	9	#include <malloc.h>
	10	#include <netdev.h>
	11	#include <phy.h>
0241c313	12	#include "axs10x.h"
a7069ddf AB	13
	14	DECLARE_GLOBAL_DATA_PTR;
	15
	16	int board_mmc_init(bd_t *bis)
	17	{
	18	struct dwmci_host *host = NULL;
	19
	20	host = malloc(sizeof(struct dwmci_host));
	21	if (!host) {
	22	printf("dwmci_host malloc fail!\n");
	23	return 1;
	24	}
	25
	26	memset(host, 0, sizeof(struct dwmci_host));
	27	host->name = "Synopsys Mobile storage";
	28	host->ioaddr = (void *)ARC_DWMMC_BASE;
	29	host->buswidth = 4;
	30	host->dev_index = 0;
d5717e89	31	host->bus_hz = 50000000;
a7069ddf	32
d5717e89	33	add_dwmci(host, host->bus_hz, 400000);
a7069ddf AB	34
	35	return 0;
	36	}
	37
	38	int board_eth_init(bd_t *bis)
	39	{
f39b2a6e	40	if (designware_initialize(ARC_DWGMAC_BASE,
a7069ddf AB	41	PHY_INTERFACE_MODE_RGMII) >= 0)
	42	return 1;
	43
	44	return 0;
	45	}
0241c313 AB	46
	47
	48	#define AXS_MB_CREG 0xE0011000
	49
	50	int board_early_init_f(void)
	51	{
	52	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
	53	gd->board_type = AXS_MB_V3;
	54	else
	55	gd->board_type = AXS_MB_V2;
	56
	57	return 0;
	58	}
8b2eb776 AB	59
	60	#ifdef CONFIG_ISA_ARCV2
	61	#define RESET_VECTOR_ADDR 0x0
	62
	63	void smp_set_core_boot_addr(unsigned long addr, int corenr)
	64	{
	65	/* All cores have reset vector pointing to 0 */
	66	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
	67
	68	/* Make sure other cores see written value in memory */
	69	flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
	70	}
	71
	72	void smp_kick_all_cpus(void)
	73	{
	74	/* CPU start CREG */
	75	#define AXC003_CREG_CPU_START 0xF0001400
	76
	77	/* Bits positions in CPU start CREG */
	78	#define BITS_START 0
	79	#define BITS_POLARITY 8
	80	#define BITS_CORE_SEL 9
	81	#define BITS_MULTICORE 12
	82
	83	#define CMD (1 << BITS_MULTICORE) \| (1 << BITS_CORE_SEL) \| \
	84	(1 << BITS_POLARITY) \| (1 << BITS_START)
	85
	86	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
	87	}
	88	#endif