board: axs10x: Flush entire cache after programming reset vector
[people/ms/u-boot.git] / board / synopsys / axs101 / axs101.c
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1/*
2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dwmmc.h>
9#include <malloc.h>
0241c313 10#include "axs10x.h"
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11
12DECLARE_GLOBAL_DATA_PTR;
13
14int board_mmc_init(bd_t *bis)
15{
16 struct dwmci_host *host = NULL;
17
18 host = malloc(sizeof(struct dwmci_host));
19 if (!host) {
20 printf("dwmci_host malloc fail!\n");
21 return 1;
22 }
23
24 memset(host, 0, sizeof(struct dwmci_host));
25 host->name = "Synopsys Mobile storage";
26 host->ioaddr = (void *)ARC_DWMMC_BASE;
27 host->buswidth = 4;
28 host->dev_index = 0;
d5717e89 29 host->bus_hz = 50000000;
a7069ddf 30
f6e27ba5 31 add_dwmci(host, host->bus_hz / 2, 400000);
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32
33 return 0;
34}
35
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36#define AXS_MB_CREG 0xE0011000
37
38int board_early_init_f(void)
39{
40 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
41 gd->board_type = AXS_MB_V3;
42 else
43 gd->board_type = AXS_MB_V2;
44
45 return 0;
46}
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47
48#ifdef CONFIG_ISA_ARCV2
49#define RESET_VECTOR_ADDR 0x0
50
51void smp_set_core_boot_addr(unsigned long addr, int corenr)
52{
53 /* All cores have reset vector pointing to 0 */
54 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
55
56 /* Make sure other cores see written value in memory */
c7d8db66 57 flush_dcache_all();
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58}
59
60void smp_kick_all_cpus(void)
61{
62/* CPU start CREG */
63#define AXC003_CREG_CPU_START 0xF0001400
64
65/* Bits positions in CPU start CREG */
66#define BITS_START 0
67#define BITS_POLARITY 8
68#define BITS_CORE_SEL 9
69#define BITS_MULTICORE 12
70
71#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
72 (1 << BITS_POLARITY) | (1 << BITS_START)
73
74 writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
75}
76#endif