[people/ms/u-boot.git] / board / synopsys / axs10x / axs10x.c

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <malloc.h>
#include <asm/arcregs.h>
#include "axs10x.h"

DECLARE_GLOBAL_DATA_PTR;

int board_mmc_init(bd_t *bis)
{
	struct dwmci_host *host = NULL;

	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		printf("dwmci_host malloc fail!\n");
		return 1;
	}

	memset(host, 0, sizeof(struct dwmci_host));
	host->name = "Synopsys Mobile storage";
	host->ioaddr = (void *)ARC_DWMMC_BASE;
	host->buswidth = 4;
	host->dev_index = 0;
	host->bus_hz = 50000000;

	add_dwmci(host, host->bus_hz / 2, 400000);

	return 0;
}

#define AXS_MB_CREG	0xE0011000

int board_early_init_f(void)
{
	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
		gd->board_type = AXS_MB_V3;
	else
		gd->board_type = AXS_MB_V2;

	return 0;
}

#ifdef CONFIG_ISA_ARCV2
#define RESET_VECTOR_ADDR	0x0

void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
	/* All cores have reset vector pointing to 0 */
	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);

	/* Make sure other cores see written value in memory */
	flush_dcache_all();
}

void smp_kick_all_cpus(void)
{
/* CPU start CREG */
#define AXC003_CREG_CPU_START	0xF0001400
/* Bits positions in CPU start CREG */
#define BITS_START	0
#define BITS_START_MODE	4
#define BITS_CORE_SEL	9

/*
 * In axs103 v1.1 START bits semantics has changed quite a bit.
 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
 * for each core:
 *     bit 0: Core 0 (master)
 *     bit 1: Core 1 (slave)
 */
#define BITS_START_CORE1	1

#define ARCVER_HS38_3_0	0x53

	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);

	if (core_family < ARCVER_HS38_3_0) {
		cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
		cmd &= ~(1 << BITS_START_MODE);
	} else {
		cmd |= (1 << BITS_START_CORE1);
	}
	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
}
#endif
Commit	Line	Data
a7069ddf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dwmmc.h>
	9	#include <malloc.h>
2a5062ca	10	#include <asm/arcregs.h>
0241c313	11	#include "axs10x.h"
a7069ddf AB	12
	13	DECLARE_GLOBAL_DATA_PTR;
	14
	15	int board_mmc_init(bd_t *bis)
	16	{
	17	struct dwmci_host *host = NULL;
	18
	19	host = malloc(sizeof(struct dwmci_host));
	20	if (!host) {
	21	printf("dwmci_host malloc fail!\n");
	22	return 1;
	23	}
	24
	25	memset(host, 0, sizeof(struct dwmci_host));
	26	host->name = "Synopsys Mobile storage";
	27	host->ioaddr = (void *)ARC_DWMMC_BASE;
	28	host->buswidth = 4;
	29	host->dev_index = 0;
d5717e89	30	host->bus_hz = 50000000;
a7069ddf	31
f6e27ba5	32	add_dwmci(host, host->bus_hz / 2, 400000);
a7069ddf AB	33
	34	return 0;
	35	}
	36
0241c313 AB	37	#define AXS_MB_CREG 0xE0011000
	38
	39	int board_early_init_f(void)
	40	{
	41	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
	42	gd->board_type = AXS_MB_V3;
	43	else
	44	gd->board_type = AXS_MB_V2;
	45
	46	return 0;
	47	}
8b2eb776 AB	48
	49	#ifdef CONFIG_ISA_ARCV2
	50	#define RESET_VECTOR_ADDR 0x0
	51
	52	void smp_set_core_boot_addr(unsigned long addr, int corenr)
	53	{
	54	/* All cores have reset vector pointing to 0 */
	55	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
	56
	57	/* Make sure other cores see written value in memory */
c7d8db66	58	flush_dcache_all();
8b2eb776 AB	59	}
	60
	61	void smp_kick_all_cpus(void)
	62	{
	63	/* CPU start CREG */
	64	#define AXC003_CREG_CPU_START 0xF0001400
8b2eb776 AB	65	/* Bits positions in CPU start CREG */
8b2eb776 AB	66	#define BITS_START 0
0b0db98b	67	#define BITS_START_MODE 4
8b2eb776	68	#define BITS_CORE_SEL 9
8b2eb776	69
2a5062ca AB	70	/*
	71	* In axs103 v1.1 START bits semantics has changed quite a bit.
	72	* We used to have a generic START bit for all cores selected by CORE_SEL mask.
	73	* But now we don't touch CORE_SEL at all because we have a dedicated START bit
	74	* for each core:
	75	* bit 0: Core 0 (master)
	76	* bit 1: Core 1 (slave)
	77	*/
	78	#define BITS_START_CORE1 1
	79
	80	#define ARCVER_HS38_3_0 0x53
	81
	82	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
0b0db98b	83	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
2a5062ca AB	84
	85	if (core_family < ARCVER_HS38_3_0) {
	86	cmd \|= (1 << BITS_CORE_SEL) \| (1 << BITS_START);
	87	cmd &= ~(1 << BITS_START_MODE);
	88	} else {
	89	cmd \|= (1 << BITS_START_CORE1);
	90	}
0b0db98b	91	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
8b2eb776 AB	92	}
8b2eb776 AB	93	#endif