projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 273ed037 SR |
1 | /* |
| 2 | * (C) Copyright 2010 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 273ed037 SR |
6 | */ |
| 7 | ||
| 25ddd1fb | 8 | #include <asm-offsets.h> |
| 273ed037 SR |
9 | #include <ppc_asm.tmpl> |
| 10 | #include <config.h> | |
| 11 | #include <asm/mmu.h> | |
| 12 | ||
| 13 | /* | |
| 14 | * TLB TABLE | |
| 15 | * | |
| 16 | * This table is used by the cpu boot code to setup the initial tlb | |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 18 | * this table lets each board set things up however they like. | |
| 19 | * | |
| 20 | * Pointer to the table is returned in r1 | |
| 21 | * | |
| 22 | */ | |
| 23 | .section .bootpg,"ax" | |
| 24 | .globl tlbtab | |
| 25 | ||
| 26 | tlbtab: | |
| 27 | tlbtab_start | |
| 28 | ||
| 29 | /* | |
| 30 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
| 31 | * use the speed up boot process. It is patched after relocation to | |
| 32 | * enable SA_I | |
| 33 | */ | |
| 34 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, | |
| 35 | CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) | |
| 36 | ||
| 37 | /* | |
| 38 | * TLB entries for SDRAM are not needed on this platform. | |
| 39 | * They are dynamically generated in the DDR(2) detection | |
| 40 | * routine. | |
| 41 | */ | |
| 42 | ||
| 43 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE | |
| 44 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ | |
| 45 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, | |
| 46 | AC_RWX | SA_G) | |
| 47 | #endif | |
| 48 | ||
| 49 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc, | |
| 50 | AC_RW | SA_IG) | |
| 51 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc, | |
| 52 | AC_RW | SA_IG) | |
| 53 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd, | |
| 54 | AC_RW | SA_IG) | |
| 55 | ||
| 56 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd, | |
| 57 | AC_RW | SA_IG) | |
| 58 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd, | |
| 59 | AC_RW | SA_IG) | |
| 60 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd, | |
| 61 | AC_RW | SA_IG) | |
| 62 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd, | |
| 63 | AC_RW | SA_IG) | |
| 64 | ||
| 65 | /* PCIe UTL register */ | |
| 66 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG) | |
| 67 | ||
| 68 | /* TLB-entry for FPGA(s) */ | |
| 5bf39a96 | 69 | tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4, |
| 273ed037 | 70 | AC_RW | SA_IG) |
| 5bf39a96 SR |
71 | tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M, |
| 72 | CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG) | |
| 73 | tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4, | |
| 273ed037 | 74 | AC_RW | SA_IG) |
| 5bf39a96 | 75 | tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4, |
| 273ed037 SR |
76 | AC_RW | SA_IG) |
| 77 | ||
| 78 | /* TLB-entry for OCM */ | |
| 79 | tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, | |
| 80 | AC_RWX | SA_I) | |
| 81 | ||
| 82 | /* TLB-entry for Local Configuration registers => peripherals */ | |
| 83 | tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, | |
| 84 | CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) | |
| 85 | ||
| 86 | tlbtab_end |