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1fdabedd SB |
1 | /* |
2 | * Copyright (C) 2011 Stefano Babic <sbabic@denx.de> | |
3 | * | |
4 | * Author: Hardy Weng <hardy.weng@technexion.com> | |
5 | * | |
6 | * Copyright (C) 2010 TechNexion Ltd. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
1fdabedd SB |
9 | */ |
10 | ||
11 | #ifndef _MT_VENTOUX_H_ | |
12 | #define _MT_VENTOUX_H_ | |
13 | ||
14 | const omap3_sysinfo sysinfo = { | |
15 | DDR_DISCRETE, | |
16 | "Teejet MT_VENTOUX Board", | |
17 | "NAND", | |
18 | }; | |
19 | ||
20 | /* FPGA CS1 configuration */ | |
21 | #define FPGA_GPMC_CONFIG1 0x00001200 | |
c2afbb50 SB |
22 | #define FPGA_GPMC_CONFIG2 0x00161f00 |
23 | #define FPGA_GPMC_CONFIG3 0x00040400 | |
24 | #define FPGA_GPMC_CONFIG4 0x120c1f08 | |
25 | #define FPGA_GPMC_CONFIG5 0x001e161f | |
26 | #define FPGA_GPMC_CONFIG6 0x96080fcf | |
1fdabedd SB |
27 | |
28 | #define FPGA_BASE_ADDR 0x20000000 | |
29 | ||
30 | /* | |
31 | * IEN - Input Enable | |
32 | * IDIS - Input Disable | |
33 | * PTD - Pull type Down | |
34 | * PTU - Pull type Up | |
35 | * DIS - Pull type selection is inactive | |
36 | * EN - Pull type selection is active | |
37 | * M0 - Mode 0 | |
38 | * The commented string gives the final mux configuration for that pin | |
39 | */ | |
40 | #define MUX_MT_VENTOUX() \ | |
41 | /* SDRC */\ | |
42 | MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ | |
43 | MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ | |
44 | MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ | |
45 | MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ | |
46 | MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ | |
47 | MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ | |
48 | MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ | |
49 | MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ | |
50 | MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ | |
51 | MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ | |
52 | MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ | |
53 | MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ | |
54 | MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ | |
55 | MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ | |
56 | MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ | |
57 | MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ | |
58 | MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ | |
59 | MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ | |
60 | MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ | |
61 | MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ | |
62 | MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ | |
63 | MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ | |
64 | MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ | |
65 | MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ | |
66 | MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ | |
67 | MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ | |
68 | MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ | |
69 | MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ | |
70 | MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ | |
71 | MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ | |
72 | MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ | |
73 | MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ | |
74 | MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ | |
75 | MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ | |
76 | MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ | |
77 | MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ | |
78 | MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ | |
79 | MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ | |
80 | MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ | |
81 | MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ | |
82 | MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ | |
83 | MUX_VAL(CP(SDRC_CKE0), (M0)) \ | |
84 | MUX_VAL(CP(SDRC_CKE1), (M0)) \ | |
85 | MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ | |
86 | MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ | |
87 | /* GPMC */\ | |
88 | MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ | |
89 | MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ | |
90 | MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ | |
91 | MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ | |
92 | MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ | |
93 | MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ | |
94 | MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ | |
95 | MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ | |
96 | MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ | |
97 | MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ | |
98 | MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ | |
99 | MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ | |
100 | MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ | |
101 | MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ | |
102 | MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ | |
103 | MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ | |
104 | MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ | |
105 | MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ | |
106 | MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ | |
107 | MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ | |
108 | MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ | |
109 | MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ | |
110 | MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ | |
111 | MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ | |
112 | MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ | |
113 | MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ | |
114 | MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ | |
115 | MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ | |
116 | MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\ | |
117 | MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\ | |
118 | MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ | |
119 | /* GPIO 55 : NFS */\ | |
120 | MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \ | |
121 | MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ | |
122 | MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ | |
123 | MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ | |
124 | MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ | |
125 | MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ | |
126 | MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ | |
127 | MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ | |
128 | MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ | |
129 | MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \ | |
130 | /*GPIO_62: FPGA_RESET */ \ | |
131 | MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ | |
132 | MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ | |
e40f6c4a SB |
133 | MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ |
134 | /* GPIO_64*/ \ | |
1fdabedd SB |
135 | MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ |
136 | /* DSS */\ | |
137 | MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ | |
138 | MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ | |
139 | MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ | |
140 | MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ | |
141 | MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ | |
142 | MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ | |
143 | MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ | |
144 | MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ | |
145 | MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ | |
146 | MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ | |
147 | MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ | |
148 | MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ | |
149 | MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ | |
150 | MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ | |
151 | MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ | |
152 | MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ | |
153 | MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ | |
154 | MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ | |
155 | MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ | |
156 | MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ | |
157 | MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ | |
158 | MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ | |
159 | MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ | |
160 | MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ | |
161 | MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ | |
162 | MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ | |
163 | MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ | |
164 | MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ | |
165 | /* CAMERA */\ | |
1fdabedd SB |
166 | MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ |
167 | MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ | |
168 | MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ | |
169 | MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ | |
170 | /* MMC */\ | |
171 | MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ | |
172 | MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ | |
173 | MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ | |
174 | MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ | |
175 | MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ | |
176 | MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ | |
177 | MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ | |
178 | /* GPIO_126: CardDetect */\ | |
179 | MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ | |
180 | MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ | |
e40f6c4a | 181 | /*GPIO_128 */ \ |
1fdabedd SB |
182 | MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ |
183 | \ | |
184 | MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ | |
185 | MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ | |
186 | MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ | |
187 | MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ | |
188 | MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ | |
189 | MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ | |
190 | MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ | |
191 | MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ | |
192 | MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ | |
193 | /* GPIO_138: LCD_ENVD */\ | |
62986875 | 194 | MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ |
1fdabedd SB |
195 | /* GPIO_139: LCD_PON */\ |
196 | /* McBSP */\ | |
197 | MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ | |
198 | MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ | |
199 | MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ | |
200 | MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ | |
201 | MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ | |
202 | MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ | |
203 | MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ | |
204 | \ | |
205 | MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \ | |
206 | /* GPIO_116: FPGA_PROG */ \ | |
207 | MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ | |
208 | /* GPIO_117: FPGA_CCLK */ \ | |
209 | MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ | |
210 | /* GPIO_118: FPGA_DIN */ \ | |
211 | MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ | |
212 | /* GPIO_119: FPGA_INIT */ \ | |
213 | \ | |
1fdabedd SB |
214 | MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ |
215 | MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ | |
216 | \ | |
217 | MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ | |
218 | /*GPIO_152: Ignition Sense */ \ | |
e40f6c4a | 219 | MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ |
1fdabedd SB |
220 | /*GPIO_153: Power Button Sense */ \ |
221 | MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ | |
222 | /* GPIO_154: FPGA_DONE */ \ | |
223 | MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \ | |
224 | /* GPIO_155: CA8_irq */ \ | |
225 | /* UART */\ | |
226 | MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ | |
227 | MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ | |
228 | /* GPIO_149: USB status 2 */\ | |
229 | MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ | |
230 | /* GPIO_150: USB status 1 */\ | |
231 | \ | |
232 | MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ | |
e40f6c4a SB |
233 | MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ |
234 | /* gpt9_pwm */\ | |
235 | MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ | |
236 | /* gpt10_pwm */\ | |
237 | MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ | |
238 | /* gpt8_pwm */\ | |
239 | MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ | |
240 | /* gpt11_pwm */\ | |
1fdabedd SB |
241 | \ |
242 | MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ | |
243 | /*GPIO_163 : TS_PENIRQ*/ \ | |
244 | MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \ | |
245 | /*GPIO_164 : MMC */\ | |
246 | MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ | |
247 | MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ | |
248 | /* I2C */\ | |
249 | MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ | |
250 | MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ | |
251 | MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ | |
252 | MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ | |
253 | MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ | |
254 | MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ | |
255 | MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ | |
256 | MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ | |
257 | /* McSPI */\ | |
258 | MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ | |
259 | MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ | |
260 | MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ | |
261 | MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ | |
262 | MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ | |
263 | MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ | |
264 | MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ | |
265 | \ | |
266 | MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ | |
267 | MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ | |
268 | MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ | |
269 | MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ | |
270 | MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ | |
271 | /* CCDC */\ | |
e40f6c4a SB |
272 | MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ |
273 | /* GPIO94 */\ | |
1fdabedd SB |
274 | MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ |
275 | /* GPIO95: #Enable Output */\ | |
e40f6c4a SB |
276 | MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ |
277 | MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ | |
1fdabedd SB |
278 | MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ |
279 | /* GPIO 99: #SOM_PWR_OFF */\ | |
e40f6c4a | 280 | MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ |
1fdabedd SB |
281 | MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ |
282 | /* GPIO_100: #power out */\ | |
e40f6c4a SB |
283 | MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ |
284 | MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ | |
285 | /* GPIO_102 */\ | |
286 | MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ | |
287 | MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ | |
288 | MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ | |
289 | MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ | |
1fdabedd SB |
290 | /* RMII */\ |
291 | MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ | |
292 | MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ | |
293 | MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ | |
294 | MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ | |
295 | MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ | |
296 | MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ | |
297 | MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ | |
298 | MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ | |
299 | MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ | |
300 | MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ | |
301 | /* HECC */\ | |
302 | MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ | |
303 | MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ | |
304 | /* HSUSB */\ | |
305 | MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ | |
306 | MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ | |
307 | MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ | |
308 | MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ | |
309 | MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ | |
310 | MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ | |
311 | MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ | |
312 | MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ | |
313 | MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ | |
314 | MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ | |
315 | MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ | |
316 | MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ | |
317 | MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ | |
318 | /* HDQ */\ | |
319 | MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ | |
320 | /* GPIO_170: auto update */\ | |
321 | /* Control and debug */\ | |
322 | MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ | |
323 | MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ | |
324 | MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ | |
325 | MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ | |
326 | /* - GPIO30 */\ | |
327 | MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ | |
328 | MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ | |
329 | MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ | |
330 | MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ | |
331 | MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ | |
332 | MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ | |
333 | MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ | |
334 | MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ | |
335 | MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ | |
336 | \ | |
337 | MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ | |
e40f6c4a SB |
338 | MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ |
339 | /* gpio_10 */\ | |
1fdabedd SB |
340 | MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ |
341 | /* JTAG */\ | |
342 | MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ | |
343 | MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ | |
344 | MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ | |
345 | MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ | |
346 | MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ | |
347 | MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ | |
348 | /* ETK (ES2 onwards) */\ | |
349 | MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ | |
350 | /* hsusb1_stp */ \ | |
351 | MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ | |
352 | /* hsusb1_clk */\ | |
353 | MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ | |
354 | MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ | |
355 | MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ | |
356 | MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ | |
357 | MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ | |
358 | MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ | |
359 | MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ | |
360 | MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ | |
361 | MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ | |
362 | MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ | |
e40f6c4a SB |
363 | MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ |
364 | /* gpio_24 */\ | |
1fdabedd | 365 | MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ |
e40f6c4a SB |
366 | MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ |
367 | /* gpio_26 */\ | |
1fdabedd | 368 | MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ |
e40f6c4a SB |
369 | MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ |
370 | MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ | |
371 | /* gpio_29 */\ | |
1fdabedd SB |
372 | /* Die to Die */\ |
373 | MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ | |
374 | MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ | |
375 | MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ | |
376 | MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ | |
377 | MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ | |
378 | MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ | |
379 | MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ | |
380 | MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ | |
381 | MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ | |
382 | MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ | |
383 | MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ | |
384 | MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ | |
385 | MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ | |
386 | MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ | |
387 | MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ | |
388 | MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ | |
389 | MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ | |
390 | MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ | |
391 | MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ | |
392 | MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ | |
393 | MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ | |
394 | MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ | |
395 | MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ | |
396 | MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ | |
397 | MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ | |
398 | MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ | |
399 | MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ | |
400 | MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ | |
401 | MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ | |
402 | MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ | |
403 | ||
404 | #endif |