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[people/ms/u-boot.git] / board / ti / am43xx / board.c
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fbf2728d
LV		 1/*
2 * board.c
3 *
4 * Board functions for TI AM43XX based boards
5 *
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
9f1a8cd3
SN		 12#include <i2c.h>
13#include <asm/errno.h>
fbf2728d 14#include <spl.h>
9f81eb77 15#include <usb.h>
3b34ac13 16#include <asm/arch/clock.h>
fbf2728d
LV		 17#include <asm/arch/sys_proto.h>
18#include <asm/arch/mux.h>
d3daba10 19#include <asm/arch/ddr_defs.h>
b5e01eec 20#include <asm/arch/gpio.h>
d3daba10 21#include <asm/emif.h>
fbf2728d 22#include "board.h"
7aa5598a 23#include <power/pmic.h>
83bad102 24#include <power/tps65218.h>
403d70ab 25#include <power/tps62362.h>
4cdd7fda
M		 26#include <miiphy.h>
27#include <cpsw.h>
9f81eb77
KVA		 28#include <linux/usb/gadget.h>
29#include <dwc3-uboot.h>
30#include <dwc3-omap-uboot.h>
31#include <ti-usb-phy-uboot.h>
fbf2728d
LV		 32
33DECLARE_GLOBAL_DATA_PTR;
34
4cdd7fda 35static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
4cdd7fda 36
9f1a8cd3
SN		 37/*
38 * Read header information from EEPROM into global structure.
39 */
40static int read_eeprom(struct am43xx_board_id *header)
41{
42 /* Check if baseboard eeprom is available */
43 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
44 printf("Could not probe the EEPROM at 0x%x\n",
45 CONFIG_SYS_I2C_EEPROM_ADDR);
46 return -ENODEV;
47 }
48
49 /* read the eeprom using i2c */
50 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
51 sizeof(struct am43xx_board_id))) {
52 printf("Could not read the EEPROM\n");
53 return -EIO;
54 }
55
56 if (header->magic != 0xEE3355AA) {
57 /*
58 * read the eeprom using i2c again,
59 * but use only a 1 byte address
60 */
61 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
62 sizeof(struct am43xx_board_id))) {
63 printf("Could not read the EEPROM at 0x%x\n",
64 CONFIG_SYS_I2C_EEPROM_ADDR);
65 return -EIO;
66 }
67
68 if (header->magic != 0xEE3355AA) {
69 printf("Incorrect magic number (0x%x) in EEPROM\n",
70 header->magic);
71 return -EINVAL;
72 }
73 }
74
75 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
76 am43xx_board_name[sizeof(header->name)] = 0;
77
2c952111
FCJ		 78 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
79 am43xx_board_rev[sizeof(header->version)] = 0;
80
9f1a8cd3
SN		 81 return 0;
82}
83
7a5f71bc 84#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fbf2728d 85
cf04d032
LV		 86#define NUM_OPPS 6
87
88const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
89 { /* 19.2 MHz */
e2a6207b 90 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
cf04d032 91 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
e2a6207b
JD		 92 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
93 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
94 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
95 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
cf04d032
LV		 96 },
97 { /* 24 MHz */
98 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
99 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
100 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
101 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
102 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
103 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
104 },
105 { /* 25 MHz */
106 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
107 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
108 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
109 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
110 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
111 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
112 },
113 { /* 26 MHz */
114 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
115 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
116 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
117 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
118 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
119 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
120 },
121};
122
123const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
e2a6207b 124 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
cf04d032
LV		 125 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
126 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
127 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
128};
129
130const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
e2a6207b
JD		 131 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
132 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
c87b6a96 133 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
e2a6207b 134 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
cf04d032
LV		 135};
136
e2a6207b
JD		 137const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
138 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
139 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
140 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
141 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
142};
cf04d032
LV		 143
144const struct dpll_params gp_evm_dpll_ddr = {
e2a6207b 145 50, 2, 1, -1, 2, -1, -1};
fbf2728d 146
403d70ab
FB		 147static const struct dpll_params idk_dpll_ddr = {
148 400, 23, 1, -1, 2, -1, -1
149};
150
d3daba10
LV		 151const struct ctrl_ioregs ioregs_lpddr2 = {
152 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
153 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
154 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
155 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
156 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
157 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
158 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
159 .emif_sdram_config_ext = 0x1,
160};
161
162const struct emif_regs emif_regs_lpddr2 = {
163 .sdram_config = 0x808012BA,
164 .ref_ctrl = 0x0000040D,
165 .sdram_tim1 = 0xEA86B411,
166 .sdram_tim2 = 0x103A094A,
167 .sdram_tim3 = 0x0F6BA37F,
168 .read_idle_ctrl = 0x00050000,
169 .zq_config = 0x50074BE4,
170 .temp_alert_config = 0x0,
171 .emif_rd_wr_lvl_rmp_win = 0x0,
172 .emif_rd_wr_lvl_rmp_ctl = 0x0,
173 .emif_rd_wr_lvl_ctl = 0x0,
e2a6207b 174 .emif_ddr_phy_ctlr_1 = 0x0E284006,
8038b497 175 .emif_rd_wr_exec_thresh = 0x80000405,
d3daba10
LV		 176 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
177 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
178 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
179 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
8038b497
CJF		 180 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
181 .emif_prio_class_serv_map = 0x80000001,
182 .emif_connect_id_serv_1_map = 0x80000094,
183 .emif_connect_id_serv_2_map = 0x00000000,
184 .emif_cos_config = 0x000FFFFF
d3daba10
LV		 185};
186
b5e01eec
LV		 187const struct ctrl_ioregs ioregs_ddr3 = {
188 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
189 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
190 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
191 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
192 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
193 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
194 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
e2a6207b 195 .emif_sdram_config_ext = 0xc163,
b5e01eec
LV		 196};
197
198const struct emif_regs ddr3_emif_regs_400Mhz = {
199 .sdram_config = 0x638413B2,
200 .ref_ctrl = 0x00000C30,
201 .sdram_tim1 = 0xEAAAD4DB,
202 .sdram_tim2 = 0x266B7FDA,
203 .sdram_tim3 = 0x107F8678,
204 .read_idle_ctrl = 0x00050000,
205 .zq_config = 0x50074BE4,
206 .temp_alert_config = 0x0,
e27f2dd7 207 .emif_ddr_phy_ctlr_1 = 0x0E004008,
b5e01eec
LV		 208 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
209 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
210 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
211 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
212 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
213 .emif_rd_wr_lvl_rmp_win = 0x0,
214 .emif_rd_wr_lvl_rmp_ctl = 0x0,
215 .emif_rd_wr_lvl_ctl = 0x0,
8038b497
CJF		 216 .emif_rd_wr_exec_thresh = 0x80000405,
217 .emif_prio_class_serv_map = 0x80000001,
218 .emif_connect_id_serv_1_map = 0x80000094,
219 .emif_connect_id_serv_2_map = 0x00000000,
220 .emif_cos_config = 0x000FFFFF
b5e01eec
LV		 221};
222
2c952111
FCJ		 223/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
224const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
225 .sdram_config = 0x638413B2,
226 .ref_ctrl = 0x00000C30,
227 .sdram_tim1 = 0xEAAAD4DB,
228 .sdram_tim2 = 0x266B7FDA,
229 .sdram_tim3 = 0x107F8678,
230 .read_idle_ctrl = 0x00050000,
231 .zq_config = 0x50074BE4,
232 .temp_alert_config = 0x0,
233 .emif_ddr_phy_ctlr_1 = 0x0E004008,
234 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
235 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
236 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
237 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
238 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
8038b497
CJF		 239 .emif_rd_wr_exec_thresh = 0x80000405,
240 .emif_prio_class_serv_map = 0x80000001,
241 .emif_connect_id_serv_1_map = 0x80000094,
242 .emif_connect_id_serv_2_map = 0x00000000,
243 .emif_cos_config = 0x000FFFFF
2c952111
FCJ		 244};
245
246/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
247const struct emif_regs ddr3_emif_regs_400Mhz_production = {
248 .sdram_config = 0x638413B2,
249 .ref_ctrl = 0x00000C30,
250 .sdram_tim1 = 0xEAAAD4DB,
251 .sdram_tim2 = 0x266B7FDA,
252 .sdram_tim3 = 0x107F8678,
253 .read_idle_ctrl = 0x00050000,
254 .zq_config = 0x50074BE4,
255 .temp_alert_config = 0x0,
256 .emif_ddr_phy_ctlr_1 = 0x0E004008,
257 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
258 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
259 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
260 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
261 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
8038b497
CJF		 262 .emif_rd_wr_exec_thresh = 0x80000405,
263 .emif_prio_class_serv_map = 0x80000001,
264 .emif_connect_id_serv_1_map = 0x80000094,
265 .emif_connect_id_serv_2_map = 0x00000000,
266 .emif_cos_config = 0x000FFFFF
2c952111
FCJ		 267};
268
9cb9f333
FB		 269static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
270 .sdram_config = 0x638413b2,
271 .sdram_config2 = 0x00000000,
272 .ref_ctrl = 0x00000c30,
273 .sdram_tim1 = 0xeaaad4db,
274 .sdram_tim2 = 0x266b7fda,
275 .sdram_tim3 = 0x107f8678,
276 .read_idle_ctrl = 0x00050000,
277 .zq_config = 0x50074be4,
278 .temp_alert_config = 0x0,
279 .emif_ddr_phy_ctlr_1 = 0x0e084008,
280 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
281 .emif_ddr_ext_phy_ctrl_2 = 0x89,
282 .emif_ddr_ext_phy_ctrl_3 = 0x90,
283 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
284 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
285 .emif_rd_wr_lvl_rmp_win = 0x0,
286 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
287 .emif_rd_wr_lvl_ctl = 0x00000000,
8038b497
CJF		 288 .emif_rd_wr_exec_thresh = 0x80000000,
289 .emif_prio_class_serv_map = 0x80000001,
290 .emif_connect_id_serv_1_map = 0x80000094,
291 .emif_connect_id_serv_2_map = 0x00000000,
292 .emif_cos_config = 0x000FFFFF
9cb9f333
FB		 293};
294
403d70ab
FB		 295static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
296 .sdram_config = 0x61a11b32,
297 .sdram_config2 = 0x00000000,
298 .ref_ctrl = 0x00000c30,
299 .sdram_tim1 = 0xeaaad4db,
300 .sdram_tim2 = 0x266b7fda,
301 .sdram_tim3 = 0x107f8678,
302 .read_idle_ctrl = 0x00050000,
303 .zq_config = 0x50074be4,
304 .temp_alert_config = 0x00000000,
305 .emif_ddr_phy_ctlr_1 = 0x00008009,
306 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
307 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
308 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
309 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
310 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
311 .emif_rd_wr_lvl_rmp_win = 0x00000000,
312 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
313 .emif_rd_wr_lvl_ctl = 0x00000000,
314 .emif_rd_wr_exec_thresh = 0x00000405,
315 .emif_prio_class_serv_map = 0x00000000,
316 .emif_connect_id_serv_1_map = 0x00000000,
317 .emif_connect_id_serv_2_map = 0x00000000,
318 .emif_cos_config = 0x00ffffff
319};
320
cf04d032
LV		 321/*
322 * get_sys_clk_index : returns the index of the sys_clk read from
323 * ctrl status register. This value is either
324 * read from efuse or sysboot pins.
325 */
326static u32 get_sys_clk_index(void)
327{
328 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
329 u32 ind = readl(&ctrl->statusreg), src;
330
331 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
332 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
333 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
334 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
335 else /* Value read from SYS BOOT pins */
336 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
337 CTRL_SYSBOOT_15_14_SHIFT);
338}
339
e2a6207b
JD		 340const struct dpll_params *get_dpll_ddr_params(void)
341{
342 int ind = get_sys_clk_index();
343
344 if (board_is_eposevm())
345 return &epos_evm_dpll_ddr[ind];
346 else if (board_is_gpevm() || board_is_sk())
347 return &gp_evm_dpll_ddr;
403d70ab
FB		 348 else if (board_is_idk())
349 return &idk_dpll_ddr;
e2a6207b
JD		 350
351 printf(" Board '%s' not supported\n", am43xx_board_name);
352 return NULL;
353}
354
355
cf04d032
LV		 356/*
357 * get_opp_offset:
358 * Returns the index for safest OPP of the device to boot.
359 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
360 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
361 * This data is read from dev_attribute register which is e-fused.
362 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
363 * OPP available. Lowest OPP starts with min_off. So returning the
364 * bit with rightmost '0'.
365 */
366static int get_opp_offset(int max_off, int min_off)
367{
368 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
feca6e67
TR		 369 int opp, offset, i;
370
371 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
372 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
cf04d032
LV		 373
374 for (i = max_off; i >= min_off; i--) {
375 offset = opp & (1 << i);
376 if (!offset)
377 return i;
378 }
379
380 return min_off;
381}
382
383const struct dpll_params *get_dpll_mpu_params(void)
384{
385 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
386 u32 ind = get_sys_clk_index();
387
388 return &dpll_mpu[ind][opp];
389}
390
391const struct dpll_params *get_dpll_core_params(void)
392{
393 int ind = get_sys_clk_index();
394
395 return &dpll_core[ind];
396}
397
398const struct dpll_params *get_dpll_per_params(void)
399{
400 int ind = get_sys_clk_index();
401
402 return &dpll_per[ind];
fbf2728d
LV		 403}
404
403d70ab 405void scale_vcores_generic(u32 m)
83bad102 406{
83bad102 407 int mpu_vdd;
83bad102
TR		 408
409 if (i2c_probe(TPS65218_CHIP_PM))
410 return;
411
403d70ab 412 switch (m) {
068ea0a8 413 case 1000:
83bad102 414 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
068ea0a8 415 break;
d5c082a3
FB		 416 case 800:
417 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
418 break;
419 case 720:
420 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
421 break;
068ea0a8 422 case 600:
83bad102 423 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
068ea0a8 424 break;
d5c082a3
FB		 425 case 300:
426 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
427 break;
068ea0a8 428 default:
83bad102
TR		 429 puts("Unknown MPU clock, not scaling\n");
430 return;
431 }
432
433 /* Set DCDC1 (CORE) voltage to 1.1V */
434 if (tps65218_voltage_update(TPS65218_DCDC1,
435 TPS65218_DCDC_VOLT_SEL_1100MV)) {
403d70ab 436 printf("%s failure\n", __func__);
83bad102
TR		 437 return;
438 }
439
440 /* Set DCDC2 (MPU) voltage */
441 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
403d70ab 442 printf("%s failure\n", __func__);
83bad102
TR		 443 return;
444 }
445}
446
403d70ab
FB		 447void scale_vcores_idk(u32 m)
448{
449 int mpu_vdd;
450
451 if (i2c_probe(TPS62362_I2C_ADDR))
452 return;
453
454 switch (m) {
455 case 1000:
456 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
457 break;
458 case 800:
459 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
460 break;
461 case 720:
462 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
463 break;
464 case 600:
465 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
466 break;
467 case 300:
468 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
469 break;
470 default:
471 puts("Unknown MPU clock, not scaling\n");
472 return;
473 }
474
475 /* Set VDD_MPU voltage */
476 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
477 printf("%s failure\n", __func__);
478 return;
479 }
480}
481
482void scale_vcores(void)
483{
484 const struct dpll_params *mpu_params;
485 struct am43xx_board_id header;
486
487 enable_i2c0_pin_mux();
488 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
489 if (read_eeprom(&header) < 0)
490 puts("Could not get board ID.\n");
491
492 /* Get the frequency */
493 mpu_params = get_dpll_mpu_params();
494
495 if (board_is_idk())
496 scale_vcores_idk(mpu_params->m);
497 else
498 scale_vcores_generic(mpu_params->m);
499}
500
fbf2728d
LV		 501void set_uart_mux_conf(void)
502{
503 enable_uart0_pin_mux();
504}
505
506void set_mux_conf_regs(void)
507{
508 enable_board_pin_mux();
509}
510
b5e01eec
LV		 511static void enable_vtt_regulator(void)
512{
513 u32 temp;
514
515 /* enable module */
cd8341b7
DG		 516 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
517
518 /* enable output for GPIO5_7 */
519 writel(GPIO_SETDATAOUT(7),
520 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
521 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
522 temp = temp & ~(GPIO_OE_ENABLE(7));
523 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
b5e01eec
LV		 524}
525
fbf2728d
LV		 526void sdram_init(void)
527{
b5e01eec
LV		 528 /*
529 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
530 * GP EMV has 1GB DDR3 connected to EMIF
531 * along with VTT regulator.
532 */
533 if (board_is_eposevm()) {
534 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
2c952111
FCJ		 535 } else if (board_is_evm_14_or_later()) {
536 enable_vtt_regulator();
537 config_ddr(0, &ioregs_ddr3, NULL, NULL,
538 &ddr3_emif_regs_400Mhz_production, 0);
539 } else if (board_is_evm_12_or_later()) {
540 enable_vtt_regulator();
541 config_ddr(0, &ioregs_ddr3, NULL, NULL,
542 &ddr3_emif_regs_400Mhz_beta, 0);
b5e01eec
LV		 543 } else if (board_is_gpevm()) {
544 enable_vtt_regulator();
545 config_ddr(0, &ioregs_ddr3, NULL, NULL,
546 &ddr3_emif_regs_400Mhz, 0);
9cb9f333
FB		 547 } else if (board_is_sk()) {
548 config_ddr(400, &ioregs_ddr3, NULL, NULL,
549 &ddr3_sk_emif_regs_400Mhz, 0);
403d70ab
FB		 550 } else if (board_is_idk()) {
551 config_ddr(400, &ioregs_ddr3, NULL, NULL,
552 &ddr3_idk_emif_regs_400Mhz, 0);
b5e01eec 553 }
fbf2728d
LV		 554}
555#endif
556
7aa5598a
TR		 557/* setup board specific PMIC */
558int power_init_board(void)
559{
560 struct pmic *p;
561
403d70ab
FB		 562 if (board_is_idk()) {
563 power_tps62362_init(I2C_PMIC);
564 p = pmic_get("TPS62362");
565 if (p && !pmic_probe(p))
566 puts("PMIC: TPS62362\n");
567 } else {
568 power_tps65218_init(I2C_PMIC);
569 p = pmic_get("TPS65218_PMIC");
570 if (p && !pmic_probe(p))
571 puts("PMIC: TPS65218\n");
572 }
7aa5598a
TR		 573
574 return 0;
575}
576
fbf2728d
LV		 577int board_init(void)
578{
8038b497
CJF		 579 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
580 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
581 modena_init0_bw_integer, modena_init0_watermark_0;
582
369cbe1e 583 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
e53ad4b4 584 gpmc_init();
fbf2728d 585
8038b497
CJF		 586 /* Clear all important bits for DSS errata that may need to be tweaked*/
587 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
588 MREQPRIO_0_SAB_INIT0_MASK;
589
590 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
591
592 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
593 BW_LIMITER_BW_FRAC_MASK;
594
595 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
596 BW_LIMITER_BW_INT_MASK;
597
598 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
599 BW_LIMITER_BW_WATERMARK_MASK;
600
601 /* Setting MReq Priority of the DSS*/
602 mreqprio_0 |= 0x77;
603
604 /*
605 * Set L3 Fast Configuration Register
606 * Limiting bandwith for ARM core to 700 MBPS
607 */
608 modena_init0_bw_fractional |= 0x10;
609 modena_init0_bw_integer |= 0x3;
610
611 writel(mreqprio_0, &cdev->mreqprio_0);
612 writel(mreqprio_1, &cdev->mreqprio_1);
613
614 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
615 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
616 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
617
fbf2728d
LV		 618 return 0;
619}
620
621#ifdef CONFIG_BOARD_LATE_INIT
622int board_late_init(void)
623{
f4af163e
SN		 624#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
625 char safe_string[HDR_NAME_LEN + 1];
626 struct am43xx_board_id header;
627
628 if (read_eeprom(&header) < 0)
629 puts("Could not get board ID.\n");
630
631 /* Now set variables based on the header. */
632 strncpy(safe_string, (char *)header.name, sizeof(header.name));
633 safe_string[sizeof(header.name)] = 0;
634 setenv("board_name", safe_string);
635
636 strncpy(safe_string, (char *)header.version, sizeof(header.version));
637 safe_string[sizeof(header.version)] = 0;
638 setenv("board_rev", safe_string);
639#endif
fbf2728d
LV		 640 return 0;
641}
642#endif
4cdd7fda 643
9f81eb77
KVA		 644#ifdef CONFIG_USB_DWC3
645static struct dwc3_device usb_otg_ss1 = {
646 .maximum_speed = USB_SPEED_HIGH,
647 .base = USB_OTG_SS1_BASE,
648 .tx_fifo_resize = false,
649 .index = 0,
650};
651
652static struct dwc3_omap_device usb_otg_ss1_glue = {
653 .base = (void *)USB_OTG_SS1_GLUE_BASE,
654 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
655 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
656 .index = 0,
657};
658
659static struct ti_usb_phy_device usb_phy1_device = {
660 .usb2_phy_power = (void *)USB2_PHY1_POWER,
661 .index = 0,
662};
663
664static struct dwc3_device usb_otg_ss2 = {
665 .maximum_speed = USB_SPEED_HIGH,
666 .base = USB_OTG_SS2_BASE,
667 .tx_fifo_resize = false,
668 .index = 1,
669};
670
671static struct dwc3_omap_device usb_otg_ss2_glue = {
672 .base = (void *)USB_OTG_SS2_GLUE_BASE,
673 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
674 .vbus_id_status = OMAP_DWC3_VBUS_VALID,
675 .index = 1,
676};
677
678static struct ti_usb_phy_device usb_phy2_device = {
679 .usb2_phy_power = (void *)USB2_PHY2_POWER,
680 .index = 1,
681};
682
683int board_usb_init(int index, enum usb_init_type init)
684{
685 switch (index) {
686 case 0:
687 if (init == USB_INIT_DEVICE) {
688 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
689 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
690 } else {
691 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
692 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
693 }
694
695 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
696 ti_usb_phy_uboot_init(&usb_phy1_device);
697 dwc3_uboot_init(&usb_otg_ss1);
698 break;
699 case 1:
700 if (init == USB_INIT_DEVICE) {
701 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
702 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
703 } else {
704 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
705 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
706 }
707
708 ti_usb_phy_uboot_init(&usb_phy2_device);
709 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
710 dwc3_uboot_init(&usb_otg_ss2);
711 break;
712 default:
713 printf("Invalid Controller Index\n");
714 }
715
716 return 0;
717}
718
719int board_usb_cleanup(int index, enum usb_init_type init)
720{
721 switch (index) {
722 case 0:
723 case 1:
724 ti_usb_phy_uboot_exit(index);
725 dwc3_uboot_exit(index);
726 dwc3_omap_uboot_exit(index);
727 break;
728 default:
729 printf("Invalid Controller Index\n");
730 }
731
732 return 0;
733}
734
2d48aa69 735int usb_gadget_handle_interrupts(int index)
9f81eb77
KVA		 736{
737 u32 status;
738
2d48aa69 739 status = dwc3_omap_uboot_interrupt_status(index);
9f81eb77 740 if (status)
2d48aa69 741 dwc3_uboot_handle_interrupt(index);
9f81eb77
KVA		 742
743 return 0;
744}
745#endif
746
4cdd7fda
M		 747#ifdef CONFIG_DRIVER_TI_CPSW
748
749static void cpsw_control(int enabled)
750{
751 /* Additional controls can be added here */
752 return;
753}
754
755static struct cpsw_slave_data cpsw_slaves[] = {
756 {
757 .slave_reg_ofs = 0x208,
758 .sliver_reg_ofs = 0xd80,
759 .phy_addr = 16,
760 },
761 {
762 .slave_reg_ofs = 0x308,
763 .sliver_reg_ofs = 0xdc0,
764 .phy_addr = 1,
765 },
766};
767
768static struct cpsw_platform_data cpsw_data = {
769 .mdio_base = CPSW_MDIO_BASE,
770 .cpsw_base = CPSW_BASE,
771 .mdio_div = 0xff,
772 .channels = 8,
773 .cpdma_reg_ofs = 0x800,
774 .slaves = 1,
775 .slave_data = cpsw_slaves,
776 .ale_reg_ofs = 0xd00,
777 .ale_entries = 1024,
778 .host_port_reg_ofs = 0x108,
779 .hw_stats_reg_ofs = 0x900,
780 .bd_ram_ofs = 0x2000,
781 .mac_control = (1 << 5),
782 .control = cpsw_control,
783 .host_port_num = 0,
784 .version = CPSW_CTRL_VERSION_2,
785};
786
787int board_eth_init(bd_t *bis)
788{
789 int rv;
790 uint8_t mac_addr[6];
791 uint32_t mac_hi, mac_lo;
792
793 /* try reading mac address from efuse */
794 mac_lo = readl(&cdev->macid0l);
795 mac_hi = readl(&cdev->macid0h);
796 mac_addr[0] = mac_hi & 0xFF;
797 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
798 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
799 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
800 mac_addr[4] = mac_lo & 0xFF;
801 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
802
803 if (!getenv("ethaddr")) {
804 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
0adb5b76 805 if (is_valid_ethaddr(mac_addr))
4cdd7fda
M		 806 eth_setenv_enetaddr("ethaddr", mac_addr);
807 }
808
809 mac_lo = readl(&cdev->macid1l);
810 mac_hi = readl(&cdev->macid1h);
811 mac_addr[0] = mac_hi & 0xFF;
812 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
813 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
814 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
815 mac_addr[4] = mac_lo & 0xFF;
816 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
817
818 if (!getenv("eth1addr")) {
0adb5b76 819 if (is_valid_ethaddr(mac_addr))
4cdd7fda
M		 820 eth_setenv_enetaddr("eth1addr", mac_addr);
821 }
822
823 if (board_is_eposevm()) {
824 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
825 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
826 cpsw_slaves[0].phy_addr = 16;
619ce62d
FB		 827 } else if (board_is_sk()) {
828 writel(RGMII_MODE_ENABLE, &cdev->miisel);
829 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
830 cpsw_slaves[0].phy_addr = 4;
831 cpsw_slaves[1].phy_addr = 5;
403d70ab
FB		 832 } else if (board_is_idk()) {
833 writel(RGMII_MODE_ENABLE, &cdev->miisel);
834 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
835 cpsw_slaves[0].phy_addr = 0;
4cdd7fda
M		 836 } else {
837 writel(RGMII_MODE_ENABLE, &cdev->miisel);
838 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
839 cpsw_slaves[0].phy_addr = 0;
840 }
841
842 rv = cpsw_register(&cpsw_data);
843 if (rv < 0)
844 printf("Error %d registering CPSW switch\n", rv);
845
846 return rv;
847}
848#endif
"Das U-Boot" Source Tree