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Merge branch 'master' of git://git.denx.de/u-boot-socfpga
[people/ms/u-boot.git] / board / ti / dra7xx / evm.c
CommitLineData
687054a7
LV		 1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
687054a7
LV		 12 */
13#include <common.h>
cb199102 14#include <palmas.h>
e9024ef2 15#include <sata.h>
25afe55d 16#include <linux/string.h>
7b922523 17#include <asm/gpio.h>
a17188c1
KVA		 18#include <usb.h>
19#include <linux/usb/gadget.h>
7b922523 20#include <asm/arch/gpio.h>
706dd348 21#include <asm/arch/dra7xx_iodelay.h>
a7638833 22#include <asm/emif.h>
687054a7
LV		 23#include <asm/arch/sys_proto.h>
24#include <asm/arch/mmc_host_def.h>
21914ee6 25#include <asm/arch/sata.h>
79b079f3 26#include <environment.h>
a17188c1
KVA		 27#include <dwc3-uboot.h>
28#include <dwc3-omap-uboot.h>
29#include <ti-usb-phy-uboot.h>
39fbac91 30#include <miiphy.h>
687054a7
LV		 31
32#include "mux_data.h"
25afe55d
LV		 33#include "../common/board_detect.h"
34
35#define board_is_dra74x_evm() board_ti_is("5777xCPU")
6b1c14bb 36#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
25afe55d
LV		 37#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
38 (strncmp("H", board_ti_get_rev(), 1) <= 0)
6b1c14bb
RB		 39#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
40 (strncmp("C", board_ti_get_rev(), 1) <= 0)
c4a2736c
LV		 41#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
42 board_ti_get_emif2_size()
687054a7 43
b1e26e3b
M		 44#ifdef CONFIG_DRIVER_TI_CPSW
45#include <cpsw.h>
46#endif
47
687054a7
LV		 48DECLARE_GLOBAL_DATA_PTR;
49
7b922523
LV		 50/* GPIO 7_11 */
51#define GPIO_DDR_VTT_EN 203
52
25afe55d
LV		 53#define SYSINFO_BOARD_NAME_MAX_LEN 37
54
687054a7 55const struct omap_sysinfo sysinfo = {
25afe55d 56 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
687054a7
LV		 57};
58
a7638833
LV		 59static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
60 .sdram_config_init = 0x61851ab2,
61 .sdram_config = 0x61851ab2,
62 .sdram_config2 = 0x08000000,
63 .ref_ctrl = 0x000040F1,
64 .ref_ctrl_final = 0x00001035,
65 .sdram_tim1 = 0xCCCF36B3,
66 .sdram_tim2 = 0x308F7FDA,
67 .sdram_tim3 = 0x427F88A8,
68 .read_idle_ctrl = 0x00050000,
69 .zq_config = 0x0007190B,
70 .temp_alert_config = 0x00000000,
71 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
72 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
73 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
74 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
75 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
76 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
77 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
78 .emif_rd_wr_lvl_rmp_win = 0x00000000,
79 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
80 .emif_rd_wr_lvl_ctl = 0x00000000,
81 .emif_rd_wr_exec_thresh = 0x00000305
82};
83
84static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
85 .sdram_config_init = 0x61851B32,
86 .sdram_config = 0x61851B32,
87 .sdram_config2 = 0x08000000,
88 .ref_ctrl = 0x000040F1,
89 .ref_ctrl_final = 0x00001035,
90 .sdram_tim1 = 0xCCCF36B3,
91 .sdram_tim2 = 0x308F7FDA,
92 .sdram_tim3 = 0x427F88A8,
93 .read_idle_ctrl = 0x00050000,
94 .zq_config = 0x0007190B,
95 .temp_alert_config = 0x00000000,
96 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
97 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
98 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
99 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
100 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
101 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
102 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
103 .emif_rd_wr_lvl_rmp_win = 0x00000000,
104 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
105 .emif_rd_wr_lvl_ctl = 0x00000000,
106 .emif_rd_wr_exec_thresh = 0x00000305
107};
108
109static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
110 .sdram_config_init = 0x61862B32,
111 .sdram_config = 0x61862B32,
112 .sdram_config2 = 0x08000000,
113 .ref_ctrl = 0x0000514C,
114 .ref_ctrl_final = 0x0000144A,
115 .sdram_tim1 = 0xD113781C,
116 .sdram_tim2 = 0x30717FE3,
117 .sdram_tim3 = 0x409F86A8,
118 .read_idle_ctrl = 0x00050000,
119 .zq_config = 0x5007190B,
120 .temp_alert_config = 0x00000000,
121 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
122 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
123 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
124 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
125 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
126 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
127 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
128 .emif_rd_wr_lvl_rmp_win = 0x00000000,
129 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
130 .emif_rd_wr_lvl_ctl = 0x00000000,
131 .emif_rd_wr_exec_thresh = 0x00000305
132};
133
6b1c14bb
RB		 134const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
135 .sdram_config_init = 0x61862BB2,
136 .sdram_config = 0x61862BB2,
137 .sdram_config2 = 0x00000000,
138 .ref_ctrl = 0x0000514D,
139 .ref_ctrl_final = 0x0000144A,
140 .sdram_tim1 = 0xD1137824,
141 .sdram_tim2 = 0x30B37FE3,
142 .sdram_tim3 = 0x409F8AD8,
143 .read_idle_ctrl = 0x00050000,
144 .zq_config = 0x5007190B,
145 .temp_alert_config = 0x00000000,
146 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
147 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
148 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
149 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
150 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
151 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
152 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
153 .emif_rd_wr_lvl_rmp_win = 0x00000000,
154 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
155 .emif_rd_wr_lvl_ctl = 0x00000000,
156 .emif_rd_wr_exec_thresh = 0x00000305
157};
158
c4a2736c
LV		 159const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
160 .sdram_config_init = 0x61851ab2,
161 .sdram_config = 0x61851ab2,
162 .sdram_config2 = 0x08000000,
163 .ref_ctrl = 0x000040F1,
164 .ref_ctrl_final = 0x00001035,
165 .sdram_tim1 = 0xCCCF36B3,
166 .sdram_tim2 = 0x30BF7FDA,
167 .sdram_tim3 = 0x427F8BA8,
168 .read_idle_ctrl = 0x00050000,
169 .zq_config = 0x0007190B,
170 .temp_alert_config = 0x00000000,
171 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
172 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
173 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
174 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
175 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
176 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
177 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
178 .emif_rd_wr_lvl_rmp_win = 0x00000000,
179 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
180 .emif_rd_wr_lvl_ctl = 0x00000000,
181 .emif_rd_wr_exec_thresh = 0x00000305
182};
183
184const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
185 .sdram_config_init = 0x61851B32,
186 .sdram_config = 0x61851B32,
187 .sdram_config2 = 0x08000000,
188 .ref_ctrl = 0x000040F1,
189 .ref_ctrl_final = 0x00001035,
190 .sdram_tim1 = 0xCCCF36B3,
191 .sdram_tim2 = 0x308F7FDA,
192 .sdram_tim3 = 0x427F88A8,
193 .read_idle_ctrl = 0x00050000,
194 .zq_config = 0x0007190B,
195 .temp_alert_config = 0x00000000,
196 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
197 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
198 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
199 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
200 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
201 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
202 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
203 .emif_rd_wr_lvl_rmp_win = 0x00000000,
204 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
205 .emif_rd_wr_lvl_ctl = 0x00000000,
206 .emif_rd_wr_exec_thresh = 0x00000305
207};
208
a7638833
LV		 209void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
210{
c4a2736c
LV		 211 u64 ram_size;
212
213 ram_size = board_ti_get_emif_size();
214
a7638833
LV		 215 switch (omap_revision()) {
216 case DRA752_ES1_0:
217 case DRA752_ES1_1:
218 case DRA752_ES2_0:
219 switch (emif_nr) {
220 case 1:
c4a2736c
LV		 221 if (ram_size > CONFIG_MAX_MEM_MAPPED)
222 *regs = &emif1_ddr3_532_mhz_1cs_2G;
223 else
224 *regs = &emif1_ddr3_532_mhz_1cs;
a7638833
LV		 225 break;
226 case 2:
c4a2736c
LV		 227 if (ram_size > CONFIG_MAX_MEM_MAPPED)
228 *regs = &emif2_ddr3_532_mhz_1cs_2G;
229 else
230 *regs = &emif2_ddr3_532_mhz_1cs;
a7638833
LV		 231 break;
232 }
233 break;
234 case DRA722_ES1_0:
6b1c14bb
RB		 235 case DRA722_ES2_0:
236 if (ram_size < CONFIG_MAX_MEM_MAPPED)
237 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
238 else
239 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
a7638833
LV		 240 break;
241 default:
242 *regs = &emif1_ddr3_532_mhz_1cs;
243 }
244}
245
246static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
247 .dmm_lisa_map_0 = 0x0,
248 .dmm_lisa_map_1 = 0x80640300,
249 .dmm_lisa_map_2 = 0xC0500220,
250 .dmm_lisa_map_3 = 0xFF020100,
251 .is_ma_present = 0x1
252};
253
254static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
255 .dmm_lisa_map_0 = 0x0,
256 .dmm_lisa_map_1 = 0x0,
257 .dmm_lisa_map_2 = 0x80600100,
258 .dmm_lisa_map_3 = 0xFF020100,
259 .is_ma_present = 0x1
260};
261
c4a2736c
LV		 262const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
263 .dmm_lisa_map_0 = 0x0,
264 .dmm_lisa_map_1 = 0x0,
265 .dmm_lisa_map_2 = 0x80740300,
266 .dmm_lisa_map_3 = 0xFF020100,
267 .is_ma_present = 0x1
268};
269
6b1c14bb
RB		 270/*
271 * DRA722 EVM EMIF1 2GB CONFIGURATION
272 * EMIF1 4 devices of 512Mb x 8 Micron
273 */
274const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
275 .dmm_lisa_map_0 = 0x0,
276 .dmm_lisa_map_1 = 0x0,
277 .dmm_lisa_map_2 = 0x80700100,
278 .dmm_lisa_map_3 = 0xFF020100,
279 .is_ma_present = 0x1
280};
281
a7638833
LV		 282void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
283{
c4a2736c
LV		 284 u64 ram_size;
285
286 ram_size = board_ti_get_emif_size();
287
a7638833
LV		 288 switch (omap_revision()) {
289 case DRA752_ES1_0:
290 case DRA752_ES1_1:
291 case DRA752_ES2_0:
c4a2736c
LV		 292 if (ram_size > CONFIG_MAX_MEM_MAPPED)
293 *dmm_lisa_regs = &lisa_map_dra7_2GB;
294 else
295 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
a7638833
LV		 296 break;
297 case DRA722_ES1_0:
6b1c14bb 298 case DRA722_ES2_0:
a7638833 299 default:
6b1c14bb
RB		 300 if (ram_size < CONFIG_MAX_MEM_MAPPED)
301 *dmm_lisa_regs = &lisa_map_2G_x_2;
302 else
303 *dmm_lisa_regs = &lisa_map_2G_x_4;
304 break;
a7638833
LV		 305 }
306}
307
1428d832
K		 308struct vcores_data dra752_volts = {
309 .mpu.value = VDD_MPU_DRA7,
310 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
311 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
312 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
313 .mpu.pmic = &tps659038,
314 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
315
316 .eve.value = VDD_EVE_DRA7,
317 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
318 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
319 .eve.addr = TPS659038_REG_ADDR_SMPS45,
320 .eve.pmic = &tps659038,
321 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
322
323 .gpu.value = VDD_GPU_DRA7,
324 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
325 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
326 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
327 .gpu.pmic = &tps659038,
328 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
329
330 .core.value = VDD_CORE_DRA7,
331 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
332 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
333 .core.addr = TPS659038_REG_ADDR_SMPS7,
334 .core.pmic = &tps659038,
335
336 .iva.value = VDD_IVA_DRA7,
337 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
338 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
339 .iva.addr = TPS659038_REG_ADDR_SMPS8,
340 .iva.pmic = &tps659038,
341 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
342};
343
344struct vcores_data dra722_volts = {
345 .mpu.value = VDD_MPU_DRA7,
346 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
347 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
348 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
349 .mpu.pmic = &tps659038,
350 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
351
352 .core.value = VDD_CORE_DRA7,
353 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
354 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .core.addr = TPS65917_REG_ADDR_SMPS2,
356 .core.pmic = &tps659038,
357
358 /*
359 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
360 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
361 */
362 .gpu.value = VDD_GPU_DRA7,
363 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
364 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
365 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
366 .gpu.pmic = &tps659038,
367 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
368
369 .eve.value = VDD_EVE_DRA7,
370 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
371 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
372 .eve.addr = TPS65917_REG_ADDR_SMPS3,
373 .eve.pmic = &tps659038,
374 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
375
376 .iva.value = VDD_IVA_DRA7,
377 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
378 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
379 .iva.addr = TPS65917_REG_ADDR_SMPS3,
380 .iva.pmic = &tps659038,
381 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
382};
383
687054a7
LV		 384/**
385 * @brief board_init
386 *
387 * @return 0
388 */
389int board_init(void)
390{
391 gpmc_init();
392 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
393
394 return 0;
395}
396
d468b178
LV		 397void dram_init_banksize(void)
398{
399 u64 ram_size;
400
401 ram_size = board_ti_get_emif_size();
402
403 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
404 gd->bd->bi_dram[0].size = get_effective_memsize();
405 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
406 gd->bd->bi_dram[1].start = 0x200000000;
407 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
408 }
409}
410
21914ee6
RQ		 411int board_late_init(void)
412{
4ec3f6e5 413#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
25afe55d
LV		 414 char *name = "unknown";
415
df6b506f
LV		 416 if (is_dra72x()) {
417 if (board_is_dra72x_revc_or_later())
418 name = "dra72x-revc";
419 else
420 name = "dra72x";
421 } else {
25afe55d 422 name = "dra7xx";
df6b506f 423 }
25afe55d
LV		 424
425 set_board_info_env(name);
f12467d1 426
07815eb9 427 omap_die_id_serial();
4ec3f6e5 428#endif
21914ee6
RQ		 429 return 0;
430}
431
25afe55d
LV		 432#ifdef CONFIG_SPL_BUILD
433void do_board_detect(void)
434{
435 int rc;
436
437 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
438 CONFIG_EEPROM_CHIP_ADDRESS);
439 if (rc)
440 printf("ti_i2c_eeprom_init failed %d\n", rc);
441}
442
443#else
444
445void do_board_detect(void)
446{
447 char *bname = NULL;
448 int rc;
449
450 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
451 CONFIG_EEPROM_CHIP_ADDRESS);
452 if (rc)
453 printf("ti_i2c_eeprom_init failed %d\n", rc);
454
455 if (board_is_dra74x_evm()) {
456 bname = "DRA74x EVM";
6b1c14bb
RB		 457 } else if (board_is_dra72x_evm()) {
458 bname = "DRA72x EVM";
25afe55d 459 } else {
6b1c14bb 460 /* If EEPROM is not populated */
25afe55d
LV		 461 if (is_dra72x())
462 bname = "DRA72x EVM";
463 else
464 bname = "DRA74x EVM";
465 }
466
467 if (bname)
468 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
469 "Board: %s REV %s\n", bname, board_ti_get_rev());
470}
471#endif /* CONFIG_SPL_BUILD */
472
1428d832
K		 473void vcores_init(void)
474{
475 if (board_is_dra74x_evm()) {
476 *omap_vcores = &dra752_volts;
477 } else if (board_is_dra72x_evm()) {
478 *omap_vcores = &dra722_volts;
479 } else {
480 /* If EEPROM is not populated */
481 if (is_dra72x())
482 *omap_vcores = &dra722_volts;
483 else
484 *omap_vcores = &dra752_volts;
485 }
486}
487
3ef56e61 488void set_muxconf_regs(void)
687054a7
LV		 489{
490 do_set_mux32((*ctrl)->control_padconf_core_base,
706dd348 491 early_padconf, ARRAY_SIZE(early_padconf));
687054a7
LV		 492}
493
706dd348
LV		 494#ifdef CONFIG_IODELAY_RECALIBRATION
495void recalibrate_iodelay(void)
496{
8cac1471 497 struct pad_conf_entry const *pads, *delta_pads = NULL;
03589234 498 struct iodelay_cfg_entry const *iodelay;
8cac1471
NM		 499 int npads, niodelays, delta_npads = 0;
500 int ret;
03589234
NM		 501
502 switch (omap_revision()) {
503 case DRA722_ES1_0:
8cac1471
NM		 504 case DRA722_ES2_0:
505 pads = dra72x_core_padconf_array_common;
506 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
507 if (board_is_dra72x_revc_or_later()) {
508 delta_pads = dra72x_rgmii_padconf_array_revc;
509 delta_npads =
510 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
511 iodelay = dra72_iodelay_cfg_array_revc;
512 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
513 } else {
514 delta_pads = dra72x_rgmii_padconf_array_revb;
515 delta_npads =
516 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
517 iodelay = dra72_iodelay_cfg_array_revb;
518 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
519 }
03589234
NM		 520 break;
521 case DRA752_ES1_0:
522 case DRA752_ES1_1:
523 pads = dra74x_core_padconf_array;
524 npads = ARRAY_SIZE(dra74x_core_padconf_array);
525 iodelay = dra742_es1_1_iodelay_cfg_array;
526 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
527 break;
528 default:
529 case DRA752_ES2_0:
530 pads = dra74x_core_padconf_array;
531 npads = ARRAY_SIZE(dra74x_core_padconf_array);
532 iodelay = dra742_es2_0_iodelay_cfg_array;
533 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
76cff2b1
NM		 534 /* Setup port1 and port2 for rgmii with 'no-id' mode */
535 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
536 RGMII1_ID_MODE_N_MASK);
03589234 537 break;
27d170af 538 }
8cac1471
NM		 539 /* Setup I/O isolation */
540 ret = __recalibrate_iodelay_start();
541 if (ret)
542 goto err;
543
544 /* Do the muxing here */
545 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
546
547 /* Now do the weird minor deltas that should be safe */
548 if (delta_npads)
549 do_set_mux32((*ctrl)->control_padconf_core_base,
550 delta_pads, delta_npads);
551
552 /* Setup IOdelay configuration */
553 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
554err:
555 /* Closeup.. remove isolation */
556 __recalibrate_iodelay_end(ret);
706dd348
LV		 557}
558#endif
559
687054a7
LV		 560#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
561int board_mmc_init(bd_t *bis)
562{
563 omap_mmc_init(0, 0, 0, -1, -1);
564 omap_mmc_init(1, 0, 0, -1, -1);
565 return 0;
566}
567#endif
b1e26e3b 568
a17188c1
KVA		 569#ifdef CONFIG_USB_DWC3
570static struct dwc3_device usb_otg_ss1 = {
571 .maximum_speed = USB_SPEED_SUPER,
572 .base = DRA7_USB_OTG_SS1_BASE,
573 .tx_fifo_resize = false,
574 .index = 0,
575};
576
577static struct dwc3_omap_device usb_otg_ss1_glue = {
578 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
579 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 580 .index = 0,
581};
582
583static struct ti_usb_phy_device usb_phy1_device = {
584 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
585 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
586 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
587 .index = 0,
588};
589
590static struct dwc3_device usb_otg_ss2 = {
591 .maximum_speed = USB_SPEED_SUPER,
592 .base = DRA7_USB_OTG_SS2_BASE,
593 .tx_fifo_resize = false,
594 .index = 1,
595};
596
597static struct dwc3_omap_device usb_otg_ss2_glue = {
598 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
599 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 600 .index = 1,
601};
602
603static struct ti_usb_phy_device usb_phy2_device = {
604 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
605 .index = 1,
606};
607
608int board_usb_init(int index, enum usb_init_type init)
609{
6f1af1e3 610 enable_usb_clocks(index);
a17188c1
KVA		 611 switch (index) {
612 case 0:
613 if (init == USB_INIT_DEVICE) {
614 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
615 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
616 } else {
617 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
618 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
619 }
620
621 ti_usb_phy_uboot_init(&usb_phy1_device);
622 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
623 dwc3_uboot_init(&usb_otg_ss1);
624 break;
625 case 1:
626 if (init == USB_INIT_DEVICE) {
627 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
628 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
629 } else {
630 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
631 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
632 }
633
634 ti_usb_phy_uboot_init(&usb_phy2_device);
635 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
636 dwc3_uboot_init(&usb_otg_ss2);
637 break;
638 default:
639 printf("Invalid Controller Index\n");
640 }
641
642 return 0;
643}
644
645int board_usb_cleanup(int index, enum usb_init_type init)
646{
647 switch (index) {
648 case 0:
649 case 1:
650 ti_usb_phy_uboot_exit(index);
651 dwc3_uboot_exit(index);
652 dwc3_omap_uboot_exit(index);
653 break;
654 default:
655 printf("Invalid Controller Index\n");
656 }
6f1af1e3 657 disable_usb_clocks(index);
a17188c1
KVA		 658 return 0;
659}
660
2d48aa69 661int usb_gadget_handle_interrupts(int index)
a17188c1
KVA		 662{
663 u32 status;
664
2d48aa69 665 status = dwc3_omap_uboot_interrupt_status(index);
a17188c1 666 if (status)
2d48aa69 667 dwc3_uboot_handle_interrupt(index);
a17188c1
KVA		 668
669 return 0;
670}
671#endif
672
79b079f3
TR		 673#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
674int spl_start_uboot(void)
675{
676 /* break into full u-boot on 'c' */
677 if (serial_tstc() && serial_getc() == 'c')
678 return 1;
679
680#ifdef CONFIG_SPL_ENV_SUPPORT
681 env_init();
682 env_relocate_spec();
683 if (getenv_yesno("boot_os") != 1)
684 return 1;
685#endif
686
687 return 0;
688}
689#endif
690
b1e26e3b 691#ifdef CONFIG_DRIVER_TI_CPSW
4c8014b9
M		 692extern u32 *const omap_si_rev;
693
b1e26e3b
M		 694static void cpsw_control(int enabled)
695{
696 /* VTP can be added here */
697
698 return;
699}
700
701static struct cpsw_slave_data cpsw_slaves[] = {
702 {
703 .slave_reg_ofs = 0x208,
704 .sliver_reg_ofs = 0xd80,
9c653aad 705 .phy_addr = 2,
b1e26e3b
M		 706 },
707 {
708 .slave_reg_ofs = 0x308,
709 .sliver_reg_ofs = 0xdc0,
9c653aad 710 .phy_addr = 3,
b1e26e3b
M		 711 },
712};
713
714static struct cpsw_platform_data cpsw_data = {
715 .mdio_base = CPSW_MDIO_BASE,
716 .cpsw_base = CPSW_BASE,
717 .mdio_div = 0xff,
718 .channels = 8,
719 .cpdma_reg_ofs = 0x800,
4c8014b9 720 .slaves = 2,
b1e26e3b
M		 721 .slave_data = cpsw_slaves,
722 .ale_reg_ofs = 0xd00,
723 .ale_entries = 1024,
724 .host_port_reg_ofs = 0x108,
725 .hw_stats_reg_ofs = 0x900,
726 .bd_ram_ofs = 0x2000,
727 .mac_control = (1 << 5),
728 .control = cpsw_control,
729 .host_port_num = 0,
730 .version = CPSW_CTRL_VERSION_2,
731};
732
733int board_eth_init(bd_t *bis)
734{
735 int ret;
736 uint8_t mac_addr[6];
737 uint32_t mac_hi, mac_lo;
738 uint32_t ctrl_val;
b1e26e3b
M		 739
740 /* try reading mac address from efuse */
741 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
742 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
e0a1d598 743 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
b1e26e3b 744 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
e0a1d598
M		 745 mac_addr[2] = mac_hi & 0xFF;
746 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
b1e26e3b 747 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
e0a1d598 748 mac_addr[5] = mac_lo & 0xFF;
b1e26e3b
M		 749
750 if (!getenv("ethaddr")) {
751 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
752
0adb5b76 753 if (is_valid_ethaddr(mac_addr))
b1e26e3b
M		 754 eth_setenv_enetaddr("ethaddr", mac_addr);
755 }
8feb37b9
M		 756
757 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
758 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
759 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
760 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
761 mac_addr[2] = mac_hi & 0xFF;
762 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
763 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
764 mac_addr[5] = mac_lo & 0xFF;
765
766 if (!getenv("eth1addr")) {
0adb5b76 767 if (is_valid_ethaddr(mac_addr))
8feb37b9
M		 768 eth_setenv_enetaddr("eth1addr", mac_addr);
769 }
770
b1e26e3b
M		 771 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
772 ctrl_val |= 0x22;
773 writel(ctrl_val, (*ctrl)->control_core_control_io1);
774
4c8014b9
M		 775 if (*omap_si_rev == DRA722_ES1_0)
776 cpsw_data.active_slave = 1;
777
39fbac91
DM		 778 if (board_is_dra72x_revc_or_later()) {
779 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
780 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
781 }
782
b1e26e3b
M		 783 ret = cpsw_register(&cpsw_data);
784 if (ret < 0)
785 printf("Error %d registering CPSW switch\n", ret);
786
787 return ret;
788}
789#endif
7b922523
LV		 790
791#ifdef CONFIG_BOARD_EARLY_INIT_F
792/* VTT regulator enable */
793static inline void vtt_regulator_enable(void)
794{
795 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
796 return;
797
798 /* Do not enable VTT for DRA722 */
6b1c14bb 799 if (is_dra72x())
7b922523
LV		 800 return;
801
802 /*
803 * EVM Rev G and later use gpio7_11 for DDR3 termination.
804 * This is safe enough to do on older revs.
805 */
806 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
807 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
808}
809
810int board_early_init_f(void)
811{
812 vtt_regulator_enable();
813 return 0;
814}
815#endif
62a09f05
DA		 816
817#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
818int ft_board_setup(void *blob, bd_t *bd)
819{
820 ft_cpu_setup(blob, bd);
821
822 return 0;
823}
824#endif
09da87da
LV		 825
826#ifdef CONFIG_SPL_LOAD_FIT
827int board_fit_config_name_match(const char *name)
828{
829 if (is_dra72x() && !strcmp(name, "dra72-evm"))
830 return 0;
831 else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
832 return 0;
833 else
834 return -1;
835}
836#endif
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