[people/ms/u-boot.git] / board / ti / dra7xx / evm.c

/*
 * (C) Copyright 2013
 * Texas Instruments Incorporated, <www.ti.com>
 *
 * Lokesh Vutla <lokeshvutla@ti.com>
 *
 * Based on previous work by:
 * Aneesh V       <aneesh@ti.com>
 * Steve Sakoman  <steve@sakoman.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <asm/gpio.h>
#include <usb.h>
#include <linux/usb/gadget.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <environment.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>

#include "mux_data.h"

#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203

const struct omap_sysinfo sysinfo = {
	"Board: DRA7xx\n"
};

/*
 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
 * essentially need to counteract the DRA7xx internal delay, and we do this
 * by delaying the control and data lines. If not using this PHY, you probably
 * don't need to do this stuff!
 */
static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
{
	int i = 0;
	u32 reg_val;
	u32 delta;
	u32 coarse;
	u32 fine;

	writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);

	while(io_dly[i].addr) {
		writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
		       io_dly[i].addr);
		delta = io_dly[i].dly;
		reg_val = readl(io_dly[i].addr) & 0x3ff;
		coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
		coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
		fine = (reg_val & 0x1F) + (delta & 0x1F);
		fine = (fine > 0x1F) ? (0x1F) : (fine);
		reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
				CFG_IO_DELAY_LOCK_MASK |
				((coarse << 5) | (fine));
		writel(reg_val, io_dly[i].addr);
		i++;
	}

	writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
}

/**
 * @brief board_init
 *
 * @return 0
 */
int board_init(void)
{
	gpmc_init();
	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */

	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (omap_revision() == DRA722_ES1_0)
		setenv("board_name", "dra72x");
	else
		setenv("board_name", "dra7xx");
#endif
	return 0;
}

static void do_set_mux32(u32 base,
			 struct pad_conf_entry const *array, int size)
{
	int i;
	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;

	for (i = 0; i < size; i++, pad++)
		writel(pad->val, base + pad->offset);
}

void set_muxconf_regs_essential(void)
{
	do_set_mux32((*ctrl)->control_padconf_core_base,
		     core_padconf_array_essential,
		     sizeof(core_padconf_array_essential) /
		     sizeof(struct pad_conf_entry));
}

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = DRA7_USB_OTG_SS1_BASE,
	.tx_fifo_resize = false,
	.index = 0,
};

static struct dwc3_omap_device usb_otg_ss1_glue = {
	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
	.index = 0,
};

static struct ti_usb_phy_device usb_phy1_device = {
	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
	.index = 0,
};

static struct dwc3_device usb_otg_ss2 = {
	.maximum_speed = USB_SPEED_SUPER,
	.base = DRA7_USB_OTG_SS2_BASE,
	.tx_fifo_resize = false,
	.index = 1,
};

static struct dwc3_omap_device usb_otg_ss2_glue = {
	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
	.index = 1,
};

static struct ti_usb_phy_device usb_phy2_device = {
	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
	.index = 1,
};

int board_usb_init(int index, enum usb_init_type init)
{
	switch (index) {
	case 0:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
		} else {
			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
		}

		ti_usb_phy_uboot_init(&usb_phy1_device);
		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
		dwc3_uboot_init(&usb_otg_ss1);
		break;
	case 1:
		if (init == USB_INIT_DEVICE) {
			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
		} else {
			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
		}

		ti_usb_phy_uboot_init(&usb_phy2_device);
		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
		dwc3_uboot_init(&usb_otg_ss2);
		break;
	default:
		printf("Invalid Controller Index\n");
	}

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	switch (index) {
	case 0:
	case 1:
		ti_usb_phy_uboot_exit(index);
		dwc3_uboot_exit(index);
		dwc3_omap_uboot_exit(index);
		break;
	default:
		printf("Invalid Controller Index\n");
	}
	return 0;
}

int usb_gadget_handle_interrupts(void)
{
	u32 status;

	status = dwc3_omap_uboot_interrupt_status(0);
	if (status)
		dwc3_uboot_handle_interrupt(0);

	return 0;
}
#endif

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	if (serial_tstc() && serial_getc() == 'c')
		return 1;

#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	if (getenv_yesno("boot_os") != 1)
		return 1;
#endif

	return 0;
}
#endif

#ifdef CONFIG_DRIVER_TI_CPSW

/* Delay value to add to calibrated value */
#define RGMII0_TXCTL_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD0_DLY_VAL		((0x3 << 5) + 0x8)
#define RGMII0_TXD1_DLY_VAL		((0x3 << 5) + 0x2)
#define RGMII0_TXD2_DLY_VAL		((0x4 << 5) + 0x0)
#define RGMII0_TXD3_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D13_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D17_DLY_VAL		((0x3 << 5) + 0x8)
#define VIN2A_D16_DLY_VAL		((0x3 << 5) + 0x2)
#define VIN2A_D15_DLY_VAL		((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL		((0x4 << 5) + 0x0)

extern u32 *const omap_si_rev;

static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 2,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 3,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 2,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int ret;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	uint32_t ctrl_val;
	const struct io_delay io_dly[] = {
		{CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
		{CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
		{CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
		{CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
		{CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
		{CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
		{CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
		{CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
		{CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
		{CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
		{0}
	};

	/* Adjust IO delay for RGMII tx path */
	dra7xx_adj_io_delay(io_dly);

	/* try reading mac address from efuse */
	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = mac_hi & 0xFF;
	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	mac_addr[5] = mac_lo & 0xFF;

	if (!getenv("eth1addr")) {
		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("eth1addr", mac_addr);
	}

	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	ctrl_val |= 0x22;
	writel(ctrl_val, (*ctrl)->control_core_control_io1);

	if (*omap_si_rev == DRA722_ES1_0)
		cpsw_data.active_slave = 1;

	ret = cpsw_register(&cpsw_data);
	if (ret < 0)
		printf("Error %d registering CPSW switch\n", ret);

	return ret;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
		return;

	/* Do not enable VTT for DRA722 */
	if (omap_revision() == DRA722_ES1_0)
		return;

	/*
	 * EVM Rev G and later use gpio7_11 for DDR3 termination.
	 * This is safe enough to do on older revs.
	 */
	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}

int board_early_init_f(void)
{
	vtt_regulator_enable();
	return 0;
}
#endif
Commit	Line	Data
687054a7 LV	1	/*
	2	* (C) Copyright 2013
	3	* Texas Instruments Incorporated, <www.ti.com>
	4	*
	5	* Lokesh Vutla <lokeshvutla@ti.com>
	6	*
	7	* Based on previous work by:
	8	* Aneesh V <aneesh@ti.com>
	9	* Steve Sakoman <steve@sakoman.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
687054a7 LV	12	*/
687054a7 LV	13	#include <common.h>
cb199102	14	#include <palmas.h>
e9024ef2	15	#include <sata.h>
7b922523	16	#include <asm/gpio.h>
a17188c1 KVA	17	#include <usb.h>
a17188c1 KVA	18	#include <linux/usb/gadget.h>
7b922523	19	#include <asm/arch/gpio.h>
687054a7 LV	20	#include <asm/arch/sys_proto.h>
687054a7 LV	21	#include <asm/arch/mmc_host_def.h>
21914ee6	22	#include <asm/arch/sata.h>
79b079f3	23	#include <environment.h>
a17188c1 KVA	24	#include <dwc3-uboot.h>
	25	#include <dwc3-omap-uboot.h>
	26	#include <ti-usb-phy-uboot.h>
687054a7 LV	27
	28	#include "mux_data.h"
	29
b1e26e3b M	30	#ifdef CONFIG_DRIVER_TI_CPSW
	31	#include <cpsw.h>
	32	#endif
	33
687054a7 LV	34	DECLARE_GLOBAL_DATA_PTR;
687054a7 LV	35
7b922523 LV	36	/* GPIO 7_11 */
	37	#define GPIO_DDR_VTT_EN 203
	38
687054a7 LV	39	const struct omap_sysinfo sysinfo = {
	40	"Board: DRA7xx\n"
	41	};
	42
b1e26e3b M	43	/*
	44	* Adjust I/O delays on the Tx control and data lines of each MAC port. This
	45	* is a workaround in order to work properly with the DP83865 PHYs on the EVM.
	46	* In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
	47	* essentially need to counteract the DRA7xx internal delay, and we do this
	48	* by delaying the control and data lines. If not using this PHY, you probably
	49	* don't need to do this stuff!
	50	*/
	51	static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
	52	{
	53	int i = 0;
	54	u32 reg_val;
	55	u32 delta;
	56	u32 coarse;
	57	u32 fine;
	58
	59	writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
	60
	61	while(io_dly[i].addr) {
	62	writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
	63	io_dly[i].addr);
	64	delta = io_dly[i].dly;
	65	reg_val = readl(io_dly[i].addr) & 0x3ff;
	66	coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
	67	coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
	68	fine = (reg_val & 0x1F) + (delta & 0x1F);
	69	fine = (fine > 0x1F) ? (0x1F) : (fine);
	70	reg_val = CFG_IO_DELAY_ACCESS_PATTERN \|
	71	CFG_IO_DELAY_LOCK_MASK \|
	72	((coarse << 5) \| (fine));
	73	writel(reg_val, io_dly[i].addr);
	74	i++;
	75	}
	76
	77	writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
	78	}
	79
687054a7 LV	80	/**
	81	* @brief board_init
	82	*
	83	* @return 0
	84	*/
	85	int board_init(void)
	86	{
	87	gpmc_init();
	88	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
	89
	90	return 0;
	91	}
	92
21914ee6 RQ	93	int board_late_init(void)
21914ee6 RQ	94	{
4ec3f6e5 LV	95	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	96	if (omap_revision() == DRA722_ES1_0)
	97	setenv("board_name", "dra72x");
	98	else
	99	setenv("board_name", "dra7xx");
	100	#endif
21914ee6 RQ	101	return 0;
	102	}
	103
687054a7 LV	104	static void do_set_mux32(u32 base,
	105	struct pad_conf_entry const *array, int size)
	106	{
	107	int i;
	108	struct pad_conf_entry pad = (struct pad_conf_entry )array;
	109
	110	for (i = 0; i < size; i++, pad++)
	111	writel(pad->val, base + pad->offset);
	112	}
	113
	114	void set_muxconf_regs_essential(void)
	115	{
	116	do_set_mux32((*ctrl)->control_padconf_core_base,
	117	core_padconf_array_essential,
	118	sizeof(core_padconf_array_essential) /
	119	sizeof(struct pad_conf_entry));
	120	}
	121
	122	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	123	int board_mmc_init(bd_t *bis)
	124	{
	125	omap_mmc_init(0, 0, 0, -1, -1);
	126	omap_mmc_init(1, 0, 0, -1, -1);
	127	return 0;
	128	}
	129	#endif
b1e26e3b	130
a17188c1 KVA	131	#ifdef CONFIG_USB_DWC3
	132	static struct dwc3_device usb_otg_ss1 = {
	133	.maximum_speed = USB_SPEED_SUPER,
	134	.base = DRA7_USB_OTG_SS1_BASE,
	135	.tx_fifo_resize = false,
	136	.index = 0,
	137	};
	138
	139	static struct dwc3_omap_device usb_otg_ss1_glue = {
	140	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
	141	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	142	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
	143	.index = 0,
	144	};
	145
	146	static struct ti_usb_phy_device usb_phy1_device = {
	147	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
	148	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
	149	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
	150	.index = 0,
	151	};
	152
	153	static struct dwc3_device usb_otg_ss2 = {
	154	.maximum_speed = USB_SPEED_SUPER,
	155	.base = DRA7_USB_OTG_SS2_BASE,
	156	.tx_fifo_resize = false,
	157	.index = 1,
	158	};
	159
	160	static struct dwc3_omap_device usb_otg_ss2_glue = {
	161	.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
	162	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
	163	.vbus_id_status = OMAP_DWC3_VBUS_VALID,
	164	.index = 1,
	165	};
	166
	167	static struct ti_usb_phy_device usb_phy2_device = {
	168	.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
	169	.index = 1,
	170	};
	171
	172	int board_usb_init(int index, enum usb_init_type init)
	173	{
	174	switch (index) {
	175	case 0:
	176	if (init == USB_INIT_DEVICE) {
	177	usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
	178	usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	179	} else {
	180	usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
	181	usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
	182	}
	183
	184	ti_usb_phy_uboot_init(&usb_phy1_device);
	185	dwc3_omap_uboot_init(&usb_otg_ss1_glue);
	186	dwc3_uboot_init(&usb_otg_ss1);
	187	break;
	188	case 1:
	189	if (init == USB_INIT_DEVICE) {
	190	usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
	191	usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
	192	} else {
	193	usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
	194	usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
195	}
196
197	ti_usb_phy_uboot_init(&usb_phy2_device);
198	dwc3_omap_uboot_init(&usb_otg_ss2_glue);
199	dwc3_uboot_init(&usb_otg_ss2);
200	break;
201	default:
202	printf("Invalid Controller Index\n");
203	}
204
205	return 0;
206	}
207
208	int board_usb_cleanup(int index, enum usb_init_type init)
209	{
210	switch (index) {
211	case 0:
212	case 1:
213	ti_usb_phy_uboot_exit(index);
214	dwc3_uboot_exit(index);
215	dwc3_omap_uboot_exit(index);
216	break;
217	default:
218	printf("Invalid Controller Index\n");
219	}
220	return 0;
221	}
222
223	int usb_gadget_handle_interrupts(void)
224	{
225	u32 status;
226
227	status = dwc3_omap_uboot_interrupt_status(0);
228	if (status)
229	dwc3_uboot_handle_interrupt(0);
230
231	return 0;
232	}
233	#endif
234
79b079f3 TR	235	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
	236	int spl_start_uboot(void)
	237	{
	238	/* break into full u-boot on 'c' */
	239	if (serial_tstc() && serial_getc() == 'c')
	240	return 1;
	241
	242	#ifdef CONFIG_SPL_ENV_SUPPORT
	243	env_init();
	244	env_relocate_spec();
	245	if (getenv_yesno("boot_os") != 1)
	246	return 1;
	247	#endif
	248
	249	return 0;
	250	}
	251	#endif
	252
b1e26e3b M	253	#ifdef CONFIG_DRIVER_TI_CPSW
	254
	255	/* Delay value to add to calibrated value */
	256	#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
	257	#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
	258	#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
	259	#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
	260	#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
	261	#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
	262	#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
	263	#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
	264	#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
	265	#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
	266
4c8014b9 M	267	extern u32 *const omap_si_rev;
4c8014b9 M	268
b1e26e3b M	269	static void cpsw_control(int enabled)
	270	{
	271	/* VTP can be added here */
	272
	273	return;
	274	}
	275
	276	static struct cpsw_slave_data cpsw_slaves[] = {
	277	{
	278	.slave_reg_ofs = 0x208,
	279	.sliver_reg_ofs = 0xd80,
9c653aad	280	.phy_addr = 2,
b1e26e3b M	281	},
	282	{
	283	.slave_reg_ofs = 0x308,
	284	.sliver_reg_ofs = 0xdc0,
9c653aad	285	.phy_addr = 3,
b1e26e3b M	286	},
	287	};
	288
	289	static struct cpsw_platform_data cpsw_data = {
	290	.mdio_base = CPSW_MDIO_BASE,
	291	.cpsw_base = CPSW_BASE,
	292	.mdio_div = 0xff,
	293	.channels = 8,
	294	.cpdma_reg_ofs = 0x800,
4c8014b9	295	.slaves = 2,
b1e26e3b M	296	.slave_data = cpsw_slaves,
	297	.ale_reg_ofs = 0xd00,
	298	.ale_entries = 1024,
	299	.host_port_reg_ofs = 0x108,
	300	.hw_stats_reg_ofs = 0x900,
	301	.bd_ram_ofs = 0x2000,
	302	.mac_control = (1 << 5),
	303	.control = cpsw_control,
	304	.host_port_num = 0,
	305	.version = CPSW_CTRL_VERSION_2,
	306	};
	307
	308	int board_eth_init(bd_t *bis)
	309	{
	310	int ret;
	311	uint8_t mac_addr[6];
	312	uint32_t mac_hi, mac_lo;
	313	uint32_t ctrl_val;
	314	const struct io_delay io_dly[] = {
	315	{CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
	316	{CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
	317	{CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
	318	{CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
	319	{CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
	320	{CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
	321	{CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
	322	{CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
	323	{CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
	324	{CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
	325	{0}
	326	};
	327
	328	/* Adjust IO delay for RGMII tx path */
	329	dra7xx_adj_io_delay(io_dly);
	330
	331	/* try reading mac address from efuse */
	332	mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
	333	mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
e0a1d598	334	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
b1e26e3b	335	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
e0a1d598 M	336	mac_addr[2] = mac_hi & 0xFF;
e0a1d598 M	337	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
b1e26e3b	338	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
e0a1d598	339	mac_addr[5] = mac_lo & 0xFF;
b1e26e3b M	340
	341	if (!getenv("ethaddr")) {
	342	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
	343
	344	if (is_valid_ether_addr(mac_addr))
	345	eth_setenv_enetaddr("ethaddr", mac_addr);
	346	}
8feb37b9 M	347
	348	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
	349	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
	350	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
	351	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	352	mac_addr[2] = mac_hi & 0xFF;
	353	mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
	354	mac_addr[4] = (mac_lo & 0xFF00) >> 8;
	355	mac_addr[5] = mac_lo & 0xFF;
	356
	357	if (!getenv("eth1addr")) {
	358	if (is_valid_ether_addr(mac_addr))
	359	eth_setenv_enetaddr("eth1addr", mac_addr);
	360	}
	361
b1e26e3b M	362	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
	363	ctrl_val \|= 0x22;
	364	writel(ctrl_val, (*ctrl)->control_core_control_io1);
	365
4c8014b9 M	366	if (*omap_si_rev == DRA722_ES1_0)
	367	cpsw_data.active_slave = 1;
	368
b1e26e3b M	369	ret = cpsw_register(&cpsw_data);
	370	if (ret < 0)
	371	printf("Error %d registering CPSW switch\n", ret);
	372
	373	return ret;
	374	}
	375	#endif
7b922523 LV	376
	377	#ifdef CONFIG_BOARD_EARLY_INIT_F
	378	/* VTT regulator enable */
	379	static inline void vtt_regulator_enable(void)
	380	{
	381	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
	382	return;
	383
	384	/* Do not enable VTT for DRA722 */
	385	if (omap_revision() == DRA722_ES1_0)
	386	return;
	387
	388	/*
	389	* EVM Rev G and later use gpio7_11 for DDR3 termination.
	390	* This is safe enough to do on older revs.
	391	*/
	392	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	393	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	394	}
	395
	396	int board_early_init_f(void)
	397	{
	398	vtt_regulator_enable();
	399	return 0;
	400	}
	401	#endif