]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/ti/dra7xx/evm.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
board: ti: dra76: Add dt support
[people/ms/u-boot.git] / board / ti / dra7xx / evm.c
CommitLineData
687054a7
LV		 1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
687054a7
LV		 12 */
13#include <common.h>
cb199102 14#include <palmas.h>
e9024ef2 15#include <sata.h>
25afe55d 16#include <linux/string.h>
7b922523 17#include <asm/gpio.h>
a17188c1
KVA		 18#include <usb.h>
19#include <linux/usb/gadget.h>
17c29873
AD		 20#include <asm/omap_common.h>
21#include <asm/omap_sec_common.h>
7b922523 22#include <asm/arch/gpio.h>
706dd348 23#include <asm/arch/dra7xx_iodelay.h>
a7638833 24#include <asm/emif.h>
687054a7
LV		 25#include <asm/arch/sys_proto.h>
26#include <asm/arch/mmc_host_def.h>
21914ee6 27#include <asm/arch/sata.h>
79b079f3 28#include <environment.h>
a17188c1
KVA		 29#include <dwc3-uboot.h>
30#include <dwc3-omap-uboot.h>
31#include <ti-usb-phy-uboot.h>
39fbac91 32#include <miiphy.h>
687054a7
LV		 33
34#include "mux_data.h"
25afe55d
LV		 35#include "../common/board_detect.h"
36
c8c04eca 37#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
25afe55d 38#define board_is_dra74x_evm() board_ti_is("5777xCPU")
6b1c14bb 39#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
463dd225 40#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
1053a769
M		 41#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
42 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
44 (strncmp("C", board_ti_get_rev(), 1) <= 0))
c4a2736c
LV		 45#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
46 board_ti_get_emif2_size()
687054a7 47
b1e26e3b
M		 48#ifdef CONFIG_DRIVER_TI_CPSW
49#include <cpsw.h>
50#endif
51
687054a7
LV		 52DECLARE_GLOBAL_DATA_PTR;
53
7b922523
LV		 54/* GPIO 7_11 */
55#define GPIO_DDR_VTT_EN 203
56
25afe55d
LV		 57#define SYSINFO_BOARD_NAME_MAX_LEN 37
58
687054a7 59const struct omap_sysinfo sysinfo = {
25afe55d 60 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
687054a7
LV		 61};
62
a7638833
LV		 63static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
64 .sdram_config_init = 0x61851ab2,
65 .sdram_config = 0x61851ab2,
66 .sdram_config2 = 0x08000000,
67 .ref_ctrl = 0x000040F1,
68 .ref_ctrl_final = 0x00001035,
69 .sdram_tim1 = 0xCCCF36B3,
70 .sdram_tim2 = 0x308F7FDA,
71 .sdram_tim3 = 0x427F88A8,
72 .read_idle_ctrl = 0x00050000,
73 .zq_config = 0x0007190B,
74 .temp_alert_config = 0x00000000,
75 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
76 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
77 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
78 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
79 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
80 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
81 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
82 .emif_rd_wr_lvl_rmp_win = 0x00000000,
83 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
84 .emif_rd_wr_lvl_ctl = 0x00000000,
85 .emif_rd_wr_exec_thresh = 0x00000305
86};
87
88static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
89 .sdram_config_init = 0x61851B32,
90 .sdram_config = 0x61851B32,
91 .sdram_config2 = 0x08000000,
92 .ref_ctrl = 0x000040F1,
93 .ref_ctrl_final = 0x00001035,
94 .sdram_tim1 = 0xCCCF36B3,
95 .sdram_tim2 = 0x308F7FDA,
96 .sdram_tim3 = 0x427F88A8,
97 .read_idle_ctrl = 0x00050000,
98 .zq_config = 0x0007190B,
99 .temp_alert_config = 0x00000000,
100 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
101 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
102 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
103 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
104 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
105 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
106 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
107 .emif_rd_wr_lvl_rmp_win = 0x00000000,
108 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
109 .emif_rd_wr_lvl_ctl = 0x00000000,
110 .emif_rd_wr_exec_thresh = 0x00000305
111};
112
113static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
114 .sdram_config_init = 0x61862B32,
115 .sdram_config = 0x61862B32,
116 .sdram_config2 = 0x08000000,
117 .ref_ctrl = 0x0000514C,
118 .ref_ctrl_final = 0x0000144A,
119 .sdram_tim1 = 0xD113781C,
120 .sdram_tim2 = 0x30717FE3,
121 .sdram_tim3 = 0x409F86A8,
122 .read_idle_ctrl = 0x00050000,
123 .zq_config = 0x5007190B,
124 .temp_alert_config = 0x00000000,
125 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
126 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
127 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
128 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
129 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
130 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
131 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
132 .emif_rd_wr_lvl_rmp_win = 0x00000000,
133 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
134 .emif_rd_wr_lvl_ctl = 0x00000000,
135 .emif_rd_wr_exec_thresh = 0x00000305
136};
137
6b1c14bb
RB		 138const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
139 .sdram_config_init = 0x61862BB2,
140 .sdram_config = 0x61862BB2,
141 .sdram_config2 = 0x00000000,
142 .ref_ctrl = 0x0000514D,
143 .ref_ctrl_final = 0x0000144A,
144 .sdram_tim1 = 0xD1137824,
145 .sdram_tim2 = 0x30B37FE3,
146 .sdram_tim3 = 0x409F8AD8,
147 .read_idle_ctrl = 0x00050000,
148 .zq_config = 0x5007190B,
149 .temp_alert_config = 0x00000000,
150 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
151 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
152 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
153 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
154 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
155 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
156 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
157 .emif_rd_wr_lvl_rmp_win = 0x00000000,
158 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
159 .emif_rd_wr_lvl_ctl = 0x00000000,
160 .emif_rd_wr_exec_thresh = 0x00000305
161};
162
c4a2736c
LV		 163const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
164 .sdram_config_init = 0x61851ab2,
165 .sdram_config = 0x61851ab2,
166 .sdram_config2 = 0x08000000,
167 .ref_ctrl = 0x000040F1,
168 .ref_ctrl_final = 0x00001035,
169 .sdram_tim1 = 0xCCCF36B3,
170 .sdram_tim2 = 0x30BF7FDA,
171 .sdram_tim3 = 0x427F8BA8,
172 .read_idle_ctrl = 0x00050000,
173 .zq_config = 0x0007190B,
174 .temp_alert_config = 0x00000000,
175 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
176 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
177 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
181 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
182 .emif_rd_wr_lvl_rmp_win = 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
184 .emif_rd_wr_lvl_ctl = 0x00000000,
185 .emif_rd_wr_exec_thresh = 0x00000305
186};
187
188const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
189 .sdram_config_init = 0x61851B32,
190 .sdram_config = 0x61851B32,
191 .sdram_config2 = 0x08000000,
192 .ref_ctrl = 0x000040F1,
193 .ref_ctrl_final = 0x00001035,
194 .sdram_tim1 = 0xCCCF36B3,
195 .sdram_tim2 = 0x308F7FDA,
196 .sdram_tim3 = 0x427F88A8,
197 .read_idle_ctrl = 0x00050000,
198 .zq_config = 0x0007190B,
199 .temp_alert_config = 0x00000000,
200 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
201 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
202 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
203 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
204 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
205 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
206 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
207 .emif_rd_wr_lvl_rmp_win = 0x00000000,
208 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
209 .emif_rd_wr_lvl_ctl = 0x00000000,
210 .emif_rd_wr_exec_thresh = 0x00000305
211};
212
c9a7c17a
LV		 213const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
214 .sdram_config_init = 0x61862B32,
215 .sdram_config = 0x61862B32,
216 .sdram_config2 = 0x00000000,
217 .ref_ctrl = 0x0000514C,
218 .ref_ctrl_final = 0x0000144A,
219 .sdram_tim1 = 0xD113783C,
220 .sdram_tim2 = 0x30B47FE3,
221 .sdram_tim3 = 0x409F8AD8,
222 .read_idle_ctrl = 0x00050000,
223 .zq_config = 0x5007190B,
224 .temp_alert_config = 0x00000000,
225 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
226 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
227 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
228 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
229 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
230 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
231 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
232 .emif_rd_wr_lvl_rmp_win = 0x00000000,
233 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
234 .emif_rd_wr_lvl_ctl = 0x00000000,
235 .emif_rd_wr_exec_thresh = 0x00000305
236};
237
238const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
239 .sdram_config_init = 0x61862B32,
240 .sdram_config = 0x61862B32,
241 .sdram_config2 = 0x00000000,
242 .ref_ctrl = 0x0000514C,
243 .ref_ctrl_final = 0x0000144A,
244 .sdram_tim1 = 0xD113781C,
245 .sdram_tim2 = 0x30B47FE3,
246 .sdram_tim3 = 0x409F8AD8,
247 .read_idle_ctrl = 0x00050000,
248 .zq_config = 0x5007190B,
249 .temp_alert_config = 0x00000000,
250 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
251 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
252 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
253 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
254 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
255 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
256 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
257 .emif_rd_wr_lvl_rmp_win = 0x00000000,
258 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
259 .emif_rd_wr_lvl_ctl = 0x00000000,
260 .emif_rd_wr_exec_thresh = 0x00000305
261};
262
a7638833
LV		 263void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
264{
c4a2736c
LV		 265 u64 ram_size;
266
267 ram_size = board_ti_get_emif_size();
268
a7638833
LV		 269 switch (omap_revision()) {
270 case DRA752_ES1_0:
271 case DRA752_ES1_1:
272 case DRA752_ES2_0:
273 switch (emif_nr) {
274 case 1:
c4a2736c
LV		 275 if (ram_size > CONFIG_MAX_MEM_MAPPED)
276 *regs = &emif1_ddr3_532_mhz_1cs_2G;
277 else
278 *regs = &emif1_ddr3_532_mhz_1cs;
a7638833
LV		 279 break;
280 case 2:
c4a2736c
LV		 281 if (ram_size > CONFIG_MAX_MEM_MAPPED)
282 *regs = &emif2_ddr3_532_mhz_1cs_2G;
283 else
284 *regs = &emif2_ddr3_532_mhz_1cs;
a7638833
LV		 285 break;
286 }
287 break;
c9a7c17a
LV		 288 case DRA762_ES1_0:
289 if (emif_nr == 1)
290 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
291 else
292 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
293 break;
a7638833 294 case DRA722_ES1_0:
6b1c14bb
RB		 295 case DRA722_ES2_0:
296 if (ram_size < CONFIG_MAX_MEM_MAPPED)
297 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
298 else
299 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
a7638833
LV		 300 break;
301 default:
302 *regs = &emif1_ddr3_532_mhz_1cs;
303 }
304}
305
306static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
307 .dmm_lisa_map_0 = 0x0,
308 .dmm_lisa_map_1 = 0x80640300,
309 .dmm_lisa_map_2 = 0xC0500220,
310 .dmm_lisa_map_3 = 0xFF020100,
311 .is_ma_present = 0x1
312};
313
314static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
315 .dmm_lisa_map_0 = 0x0,
316 .dmm_lisa_map_1 = 0x0,
317 .dmm_lisa_map_2 = 0x80600100,
318 .dmm_lisa_map_3 = 0xFF020100,
319 .is_ma_present = 0x1
320};
321
c4a2736c
LV		 322const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
323 .dmm_lisa_map_0 = 0x0,
324 .dmm_lisa_map_1 = 0x0,
325 .dmm_lisa_map_2 = 0x80740300,
326 .dmm_lisa_map_3 = 0xFF020100,
327 .is_ma_present = 0x1
328};
329
6b1c14bb
RB		 330/*
331 * DRA722 EVM EMIF1 2GB CONFIGURATION
332 * EMIF1 4 devices of 512Mb x 8 Micron
333 */
334const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
335 .dmm_lisa_map_0 = 0x0,
336 .dmm_lisa_map_1 = 0x0,
337 .dmm_lisa_map_2 = 0x80700100,
338 .dmm_lisa_map_3 = 0xFF020100,
339 .is_ma_present = 0x1
340};
341
a7638833
LV		 342void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
343{
c4a2736c
LV		 344 u64 ram_size;
345
346 ram_size = board_ti_get_emif_size();
347
a7638833 348 switch (omap_revision()) {
c9a7c17a 349 case DRA762_ES1_0:
a7638833
LV		 350 case DRA752_ES1_0:
351 case DRA752_ES1_1:
352 case DRA752_ES2_0:
c4a2736c
LV		 353 if (ram_size > CONFIG_MAX_MEM_MAPPED)
354 *dmm_lisa_regs = &lisa_map_dra7_2GB;
355 else
356 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
a7638833
LV		 357 break;
358 case DRA722_ES1_0:
6b1c14bb 359 case DRA722_ES2_0:
a7638833 360 default:
6b1c14bb
RB		 361 if (ram_size < CONFIG_MAX_MEM_MAPPED)
362 *dmm_lisa_regs = &lisa_map_2G_x_2;
363 else
364 *dmm_lisa_regs = &lisa_map_2G_x_4;
365 break;
a7638833
LV		 366 }
367}
368
1428d832 369struct vcores_data dra752_volts = {
beb71279
LV		 370 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
371 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
1428d832
K		 372 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
373 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
374 .mpu.pmic = &tps659038,
375 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
376
beb71279
LV		 377 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
378 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
379 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
380 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
381 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
382 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
1428d832
K		 383 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
384 .eve.addr = TPS659038_REG_ADDR_SMPS45,
385 .eve.pmic = &tps659038,
386 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
387
beb71279
LV		 388 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
389 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
390 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
391 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
392 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
393 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
1428d832
K		 394 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
395 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
396 .gpu.pmic = &tps659038,
397 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
398
beb71279
LV		 399 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
400 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
1428d832
K		 401 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
402 .core.addr = TPS659038_REG_ADDR_SMPS7,
403 .core.pmic = &tps659038,
404
beb71279
LV		 405 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
406 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
407 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
408 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
409 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
410 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
1428d832
K		 411 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
412 .iva.addr = TPS659038_REG_ADDR_SMPS8,
413 .iva.pmic = &tps659038,
414 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
415};
416
c2476055
K		 417struct vcores_data dra76x_volts = {
418 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
419 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
420 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
421 .mpu.addr = LP87565_REG_ADDR_BUCK01,
422 .mpu.pmic = &lp87565,
423 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
424
425 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
426 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
427 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
428 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
429 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
430 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
431 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
432 .eve.addr = TPS65917_REG_ADDR_SMPS1,
433 .eve.pmic = &tps659038,
434 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
435
436 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
437 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
438 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
439 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
440 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
441 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
442 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
443 .gpu.addr = LP87565_REG_ADDR_BUCK23,
444 .gpu.pmic = &lp87565,
445 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
446
447 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
448 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
449 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
450 .core.addr = TPS65917_REG_ADDR_SMPS3,
451 .core.pmic = &tps659038,
452
453 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
454 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
455 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
456 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
457 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
458 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
459 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
460 .iva.addr = TPS65917_REG_ADDR_SMPS4,
461 .iva.pmic = &tps659038,
462 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
463};
464
1428d832 465struct vcores_data dra722_volts = {
beb71279
LV		 466 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
467 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
1428d832
K		 468 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
469 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
470 .mpu.pmic = &tps659038,
471 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
472
beb71279
LV		 473 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
474 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
1428d832
K		 475 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
476 .core.addr = TPS65917_REG_ADDR_SMPS2,
477 .core.pmic = &tps659038,
478
479 /*
480 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
481 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
482 */
beb71279
LV		 483 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
484 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
485 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
486 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
487 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
488 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
1428d832
K		 489 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
490 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
491 .gpu.pmic = &tps659038,
492 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
493
beb71279
LV		 494 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
495 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
496 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
497 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
498 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
499 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
1428d832
K		 500 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
501 .eve.addr = TPS65917_REG_ADDR_SMPS3,
502 .eve.pmic = &tps659038,
503 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
504
beb71279
LV		 505 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
506 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
507 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
508 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
509 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
510 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
1428d832
K		 511 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
512 .iva.addr = TPS65917_REG_ADDR_SMPS3,
513 .iva.pmic = &tps659038,
514 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
515};
516
f56e6350
K		 517struct vcores_data dra718_volts = {
518 /*
519 * In the case of dra71x GPU MPU and CORE
520 * are all powered up by BUCK0 of LP873X PMIC
521 */
522 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
523 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
524 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
525 .mpu.addr = LP873X_REG_ADDR_BUCK0,
526 .mpu.pmic = &lp8733,
527 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
528
529 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
530 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
531 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
532 .core.addr = LP873X_REG_ADDR_BUCK0,
533 .core.pmic = &lp8733,
534
535 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
536 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
537 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
538 .gpu.addr = LP873X_REG_ADDR_BUCK0,
539 .gpu.pmic = &lp8733,
540 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
541
542 /*
543 * The DSPEVE and IVA rails are grouped on DRA71x-evm
544 * and are powered by BUCK1 of LP873X PMIC
545 */
546 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
6cc96bc7 547 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
f56e6350 548 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
6cc96bc7 549 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
f56e6350
K		 550 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
551 .eve.addr = LP873X_REG_ADDR_BUCK1,
552 .eve.pmic = &lp8733,
553 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
554
555 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
6cc96bc7 556 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
f56e6350 557 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
6cc96bc7 558 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
f56e6350
K		 559 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
560 .iva.addr = LP873X_REG_ADDR_BUCK1,
561 .iva.pmic = &lp8733,
562 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
563};
564
beb71279
LV		 565int get_voltrail_opp(int rail_offset)
566{
567 int opp;
568
569 switch (rail_offset) {
570 case VOLT_MPU:
571 opp = DRA7_MPU_OPP;
6cc96bc7
LV		 572 /* DRA71x supports only OPP_NOM for MPU */
573 if (board_is_dra71x_evm())
574 opp = OPP_NOM;
beb71279
LV		 575 break;
576 case VOLT_CORE:
577 opp = DRA7_CORE_OPP;
6cc96bc7
LV		 578 /* DRA71x supports only OPP_NOM for CORE */
579 if (board_is_dra71x_evm())
580 opp = OPP_NOM;
beb71279
LV		 581 break;
582 case VOLT_GPU:
583 opp = DRA7_GPU_OPP;
6cc96bc7
LV		 584 /* DRA71x supports only OPP_NOM for GPU */
585 if (board_is_dra71x_evm())
586 opp = OPP_NOM;
beb71279
LV		 587 break;
588 case VOLT_EVE:
589 opp = DRA7_DSPEVE_OPP;
6cc96bc7
LV		 590 /*
591 * DRA71x does not support OPP_OD for EVE.
592 * If OPP_OD is selected by menuconfig, fallback
593 * to OPP_NOM.
594 */
595 if (board_is_dra71x_evm() && opp == OPP_OD)
596 opp = OPP_NOM;
beb71279
LV		 597 break;
598 case VOLT_IVA:
599 opp = DRA7_IVA_OPP;
6cc96bc7
LV		 600 /*
601 * DRA71x does not support OPP_OD for IVA.
602 * If OPP_OD is selected by menuconfig, fallback
603 * to OPP_NOM.
604 */
605 if (board_is_dra71x_evm() && opp == OPP_OD)
606 opp = OPP_NOM;
beb71279
LV		 607 break;
608 default:
609 opp = OPP_NOM;
610 }
611
612 return opp;
613}
614
687054a7
LV		 615/**
616 * @brief board_init
617 *
618 * @return 0
619 */
620int board_init(void)
621{
622 gpmc_init();
623 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
624
625 return 0;
626}
627
76b00aca 628int dram_init_banksize(void)
d468b178
LV		 629{
630 u64 ram_size;
631
632 ram_size = board_ti_get_emif_size();
633
634 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
635 gd->bd->bi_dram[0].size = get_effective_memsize();
636 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
637 gd->bd->bi_dram[1].start = 0x200000000;
638 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
639 }
76b00aca
SG		 640
641 return 0;
d468b178
LV		 642}
643
21914ee6
RQ		 644int board_late_init(void)
645{
4ec3f6e5 646#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
25afe55d
LV		 647 char *name = "unknown";
648
df6b506f
LV		 649 if (is_dra72x()) {
650 if (board_is_dra72x_revc_or_later())
651 name = "dra72x-revc";
463dd225
LV		 652 else if (board_is_dra71x_evm())
653 name = "dra71x";
df6b506f
LV		 654 else
655 name = "dra72x";
c8c04eca
LV		 656 } else if (is_dra76x()) {
657 name = "dra76x";
df6b506f 658 } else {
25afe55d 659 name = "dra7xx";
df6b506f 660 }
25afe55d
LV		 661
662 set_board_info_env(name);
f12467d1 663
71c1b58e
LV		 664 /*
665 * Default FIT boot on HS devices. Non FIT images are not allowed
666 * on HS devices.
667 */
668 if (get_device_type() == HS_DEVICE)
382bee57 669 env_set("boot_fit", "1");
71c1b58e 670
07815eb9 671 omap_die_id_serial();
4a30a939 672 omap_set_fastboot_vars();
4ec3f6e5 673#endif
21914ee6
RQ		 674 return 0;
675}
676
25afe55d
LV		 677#ifdef CONFIG_SPL_BUILD
678void do_board_detect(void)
679{
680 int rc;
681
682 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
683 CONFIG_EEPROM_CHIP_ADDRESS);
684 if (rc)
685 printf("ti_i2c_eeprom_init failed %d\n", rc);
686}
687
688#else
689
690void do_board_detect(void)
691{
692 char *bname = NULL;
693 int rc;
694
695 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
696 CONFIG_EEPROM_CHIP_ADDRESS);
697 if (rc)
698 printf("ti_i2c_eeprom_init failed %d\n", rc);
699
700 if (board_is_dra74x_evm()) {
701 bname = "DRA74x EVM";
6b1c14bb
RB		 702 } else if (board_is_dra72x_evm()) {
703 bname = "DRA72x EVM";
463dd225
LV		 704 } else if (board_is_dra71x_evm()) {
705 bname = "DRA71x EVM";
c8c04eca
LV		 706 } else if (board_is_dra76x_evm()) {
707 bname = "DRA76x EVM";
25afe55d 708 } else {
6b1c14bb 709 /* If EEPROM is not populated */
25afe55d
LV		 710 if (is_dra72x())
711 bname = "DRA72x EVM";
712 else
713 bname = "DRA74x EVM";
714 }
715
716 if (bname)
717 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
718 "Board: %s REV %s\n", bname, board_ti_get_rev());
719}
720#endif /* CONFIG_SPL_BUILD */
721
1428d832
K		 722void vcores_init(void)
723{
724 if (board_is_dra74x_evm()) {
725 *omap_vcores = &dra752_volts;
726 } else if (board_is_dra72x_evm()) {
727 *omap_vcores = &dra722_volts;
f56e6350
K		 728 } else if (board_is_dra71x_evm()) {
729 *omap_vcores = &dra718_volts;
c2476055
K		 730 } else if (board_is_dra76x_evm()) {
731 *omap_vcores = &dra76x_volts;
1428d832
K		 732 } else {
733 /* If EEPROM is not populated */
734 if (is_dra72x())
735 *omap_vcores = &dra722_volts;
736 else
737 *omap_vcores = &dra752_volts;
738 }
739}
740
3ef56e61 741void set_muxconf_regs(void)
687054a7
LV		 742{
743 do_set_mux32((*ctrl)->control_padconf_core_base,
706dd348 744 early_padconf, ARRAY_SIZE(early_padconf));
687054a7
LV		 745}
746
706dd348
LV		 747#ifdef CONFIG_IODELAY_RECALIBRATION
748void recalibrate_iodelay(void)
749{
8cac1471 750 struct pad_conf_entry const *pads, *delta_pads = NULL;
03589234 751 struct iodelay_cfg_entry const *iodelay;
8cac1471
NM		 752 int npads, niodelays, delta_npads = 0;
753 int ret;
03589234
NM		 754
755 switch (omap_revision()) {
756 case DRA722_ES1_0:
8cac1471
NM		 757 case DRA722_ES2_0:
758 pads = dra72x_core_padconf_array_common;
759 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
4d748048
LV		 760 if (board_is_dra71x_evm()) {
761 pads = dra71x_core_padconf_array;
762 npads = ARRAY_SIZE(dra71x_core_padconf_array);
763 iodelay = dra71_iodelay_cfg_array;
764 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
765 } else if (board_is_dra72x_revc_or_later()) {
8cac1471
NM		 766 delta_pads = dra72x_rgmii_padconf_array_revc;
767 delta_npads =
768 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
769 iodelay = dra72_iodelay_cfg_array_revc;
770 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
771 } else {
772 delta_pads = dra72x_rgmii_padconf_array_revb;
773 delta_npads =
774 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
775 iodelay = dra72_iodelay_cfg_array_revb;
776 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
777 }
03589234
NM		 778 break;
779 case DRA752_ES1_0:
780 case DRA752_ES1_1:
781 pads = dra74x_core_padconf_array;
782 npads = ARRAY_SIZE(dra74x_core_padconf_array);
783 iodelay = dra742_es1_1_iodelay_cfg_array;
784 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
785 break;
9120ef07
LV		 786 case DRA762_ES1_0:
787 pads = dra76x_core_padconf_array;
788 npads = ARRAY_SIZE(dra76x_core_padconf_array);
789 iodelay = dra76x_es1_0_iodelay_cfg_array;
790 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
791 break;
03589234
NM		 792 default:
793 case DRA752_ES2_0:
794 pads = dra74x_core_padconf_array;
795 npads = ARRAY_SIZE(dra74x_core_padconf_array);
796 iodelay = dra742_es2_0_iodelay_cfg_array;
797 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
76cff2b1
NM		 798 /* Setup port1 and port2 for rgmii with 'no-id' mode */
799 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
800 RGMII1_ID_MODE_N_MASK);
03589234 801 break;
27d170af 802 }
8cac1471
NM		 803 /* Setup I/O isolation */
804 ret = __recalibrate_iodelay_start();
805 if (ret)
806 goto err;
807
808 /* Do the muxing here */
809 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
810
811 /* Now do the weird minor deltas that should be safe */
812 if (delta_npads)
813 do_set_mux32((*ctrl)->control_padconf_core_base,
814 delta_pads, delta_npads);
815
816 /* Setup IOdelay configuration */
817 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
818err:
819 /* Closeup.. remove isolation */
820 __recalibrate_iodelay_end(ret);
706dd348
LV		 821}
822#endif
823
4aa2ba3a 824#if defined(CONFIG_MMC)
687054a7
LV		 825int board_mmc_init(bd_t *bis)
826{
827 omap_mmc_init(0, 0, 0, -1, -1);
828 omap_mmc_init(1, 0, 0, -1, -1);
829 return 0;
830}
91d3e906
LV		 831
832void board_mmc_poweron_ldo(uint voltage)
833{
834 if (board_is_dra71x_evm()) {
835 if (voltage == LDO_VOLT_3V0)
836 voltage = 0x19;
837 else if (voltage == LDO_VOLT_1V8)
838 voltage = 0xa;
839 lp873x_mmc1_poweron_ldo(voltage);
cd43b516
LV		 840 } else if (board_is_dra76x_evm()) {
841 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
91d3e906 842 } else {
db4fce8f 843 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
91d3e906
LV		 844 }
845}
687054a7 846#endif
b1e26e3b 847
a17188c1
KVA		 848#ifdef CONFIG_USB_DWC3
849static struct dwc3_device usb_otg_ss1 = {
850 .maximum_speed = USB_SPEED_SUPER,
851 .base = DRA7_USB_OTG_SS1_BASE,
852 .tx_fifo_resize = false,
853 .index = 0,
854};
855
856static struct dwc3_omap_device usb_otg_ss1_glue = {
857 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
858 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 859 .index = 0,
860};
861
862static struct ti_usb_phy_device usb_phy1_device = {
863 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
864 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
865 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
866 .index = 0,
867};
868
869static struct dwc3_device usb_otg_ss2 = {
870 .maximum_speed = USB_SPEED_SUPER,
871 .base = DRA7_USB_OTG_SS2_BASE,
872 .tx_fifo_resize = false,
873 .index = 1,
874};
875
876static struct dwc3_omap_device usb_otg_ss2_glue = {
877 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
878 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 879 .index = 1,
880};
881
882static struct ti_usb_phy_device usb_phy2_device = {
883 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
884 .index = 1,
885};
886
1a9a5f7a 887int omap_xhci_board_usb_init(int index, enum usb_init_type init)
a17188c1 888{
6f1af1e3 889 enable_usb_clocks(index);
a17188c1
KVA		 890 switch (index) {
891 case 0:
892 if (init == USB_INIT_DEVICE) {
893 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
894 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
895 } else {
896 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
897 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
898 }
899
900 ti_usb_phy_uboot_init(&usb_phy1_device);
901 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
902 dwc3_uboot_init(&usb_otg_ss1);
903 break;
904 case 1:
905 if (init == USB_INIT_DEVICE) {
906 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
907 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
908 } else {
909 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
910 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
911 }
912
913 ti_usb_phy_uboot_init(&usb_phy2_device);
914 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
915 dwc3_uboot_init(&usb_otg_ss2);
916 break;
917 default:
918 printf("Invalid Controller Index\n");
919 }
920
921 return 0;
922}
923
1a9a5f7a 924int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
a17188c1
KVA		 925{
926 switch (index) {
927 case 0:
928 case 1:
929 ti_usb_phy_uboot_exit(index);
930 dwc3_uboot_exit(index);
931 dwc3_omap_uboot_exit(index);
932 break;
933 default:
934 printf("Invalid Controller Index\n");
935 }
6f1af1e3 936 disable_usb_clocks(index);
a17188c1
KVA		 937 return 0;
938}
939
2d48aa69 940int usb_gadget_handle_interrupts(int index)
a17188c1
KVA		 941{
942 u32 status;
943
2d48aa69 944 status = dwc3_omap_uboot_interrupt_status(index);
a17188c1 945 if (status)
2d48aa69 946 dwc3_uboot_handle_interrupt(index);
a17188c1
KVA		 947
948 return 0;
949}
950#endif
951
79b079f3
TR		 952#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
953int spl_start_uboot(void)
954{
955 /* break into full u-boot on 'c' */
956 if (serial_tstc() && serial_getc() == 'c')
957 return 1;
958
959#ifdef CONFIG_SPL_ENV_SUPPORT
960 env_init();
310fb14b 961 env_load();
bfebc8c9 962 if (env_get_yesno("boot_os") != 1)
79b079f3
TR		 963 return 1;
964#endif
965
966 return 0;
967}
968#endif
969
b1e26e3b 970#ifdef CONFIG_DRIVER_TI_CPSW
4c8014b9
M		 971extern u32 *const omap_si_rev;
972
b1e26e3b
M		 973static void cpsw_control(int enabled)
974{
975 /* VTP can be added here */
976
977 return;
978}
979
980static struct cpsw_slave_data cpsw_slaves[] = {
981 {
982 .slave_reg_ofs = 0x208,
983 .sliver_reg_ofs = 0xd80,
9c653aad 984 .phy_addr = 2,
b1e26e3b
M		 985 },
986 {
987 .slave_reg_ofs = 0x308,
988 .sliver_reg_ofs = 0xdc0,
9c653aad 989 .phy_addr = 3,
b1e26e3b
M		 990 },
991};
992
993static struct cpsw_platform_data cpsw_data = {
994 .mdio_base = CPSW_MDIO_BASE,
995 .cpsw_base = CPSW_BASE,
996 .mdio_div = 0xff,
997 .channels = 8,
998 .cpdma_reg_ofs = 0x800,
4c8014b9 999 .slaves = 2,
b1e26e3b
M		 1000 .slave_data = cpsw_slaves,
1001 .ale_reg_ofs = 0xd00,
1002 .ale_entries = 1024,
1003 .host_port_reg_ofs = 0x108,
1004 .hw_stats_reg_ofs = 0x900,
1005 .bd_ram_ofs = 0x2000,
1006 .mac_control = (1 << 5),
1007 .control = cpsw_control,
1008 .host_port_num = 0,
1009 .version = CPSW_CTRL_VERSION_2,
1010};
1011
1012int board_eth_init(bd_t *bis)
1013{
1014 int ret;
1015 uint8_t mac_addr[6];
1016 uint32_t mac_hi, mac_lo;
1017 uint32_t ctrl_val;
b1e26e3b
M		 1018
1019 /* try reading mac address from efuse */
1020 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1021 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
e0a1d598 1022 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
b1e26e3b 1023 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
e0a1d598
M		 1024 mac_addr[2] = mac_hi & 0xFF;
1025 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
b1e26e3b 1026 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
e0a1d598 1027 mac_addr[5] = mac_lo & 0xFF;
b1e26e3b 1028
00caae6d 1029 if (!env_get("ethaddr")) {
b1e26e3b
M		 1030 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1031
0adb5b76 1032 if (is_valid_ethaddr(mac_addr))
fd1e959e 1033 eth_env_set_enetaddr("ethaddr", mac_addr);
b1e26e3b 1034 }
8feb37b9
M		 1035
1036 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1037 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1038 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1039 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1040 mac_addr[2] = mac_hi & 0xFF;
1041 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1042 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1043 mac_addr[5] = mac_lo & 0xFF;
1044
00caae6d 1045 if (!env_get("eth1addr")) {
0adb5b76 1046 if (is_valid_ethaddr(mac_addr))
fd1e959e 1047 eth_env_set_enetaddr("eth1addr", mac_addr);
8feb37b9
M		 1048 }
1049
b1e26e3b
M		 1050 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1051 ctrl_val |= 0x22;
1052 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1053
4c8014b9
M		 1054 if (*omap_si_rev == DRA722_ES1_0)
1055 cpsw_data.active_slave = 1;
1056
39fbac91
DM		 1057 if (board_is_dra72x_revc_or_later()) {
1058 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1059 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1060 }
1061
b1e26e3b
M		 1062 ret = cpsw_register(&cpsw_data);
1063 if (ret < 0)
1064 printf("Error %d registering CPSW switch\n", ret);
1065
1066 return ret;
1067}
1068#endif
7b922523
LV		 1069
1070#ifdef CONFIG_BOARD_EARLY_INIT_F
1071/* VTT regulator enable */
1072static inline void vtt_regulator_enable(void)
1073{
1074 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1075 return;
1076
c9a7c17a
LV		 1077 /* Do not enable VTT for DRA722 or DRA76x */
1078 if (is_dra72x() || is_dra76x())
7b922523
LV		 1079 return;
1080
1081 /*
1082 * EVM Rev G and later use gpio7_11 for DDR3 termination.
1083 * This is safe enough to do on older revs.
1084 */
1085 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1086 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1087}
1088
1089int board_early_init_f(void)
1090{
1091 vtt_regulator_enable();
1092 return 0;
1093}
1094#endif
62a09f05
DA		 1095
1096#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1097int ft_board_setup(void *blob, bd_t *bd)
1098{
1099 ft_cpu_setup(blob, bd);
1100
1101 return 0;
1102}
1103#endif
09da87da
LV		 1104
1105#ifdef CONFIG_SPL_LOAD_FIT
1106int board_fit_config_name_match(const char *name)
1107{
e8131386 1108 if (is_dra72x()) {
40de70fb
LV		 1109 if (board_is_dra71x_evm()) {
1110 if (!strcmp(name, "dra71-evm"))
1111 return 0;
1112 }else if(board_is_dra72x_revc_or_later()) {
e8131386
M		 1113 if (!strcmp(name, "dra72-evm-revc"))
1114 return 0;
1115 } else if (!strcmp(name, "dra72-evm")) {
1116 return 0;
1117 }
fede9429
LV		 1118 } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
1119 return 0;
1120 } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
09da87da 1121 return 0;
e8131386
M		 1122 }
1123
1124 return -1;
09da87da
LV		 1125}
1126#endif
17c29873
AD		 1127
1128#ifdef CONFIG_TI_SECURE_DEVICE
1129void board_fit_image_post_process(void **p_image, size_t *p_size)
1130{
1131 secure_boot_verify_image(p_image, p_size);
1132}
0fcc5207
AD		 1133
1134void board_tee_image_process(ulong tee_image, size_t tee_size)
1135{
1136 secure_tee_install((u32)tee_image);
1137}
1138
1139U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
17c29873 1140#endif
"Das U-Boot" Source Tree