[people/ms/u-boot.git] / board / ti / ks2_evm / board_k2g.c

/*
 * K2G EVM : Board initialization
 *
 * (C) Copyright 2015
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include "mux-k2g.h"

#define SYS_CLK		24000000

unsigned int external_clk[ext_clk_count] = {
	[sys_clk]	=	SYS_CLK,
	[pa_clk]	=	SYS_CLK,
	[tetris_clk]	=	SYS_CLK,
	[ddr3a_clk]	=	SYS_CLK,
	[uart_clk]	=	SYS_CLK,
};

static int arm_speeds[DEVSPEED_NUMSPDS] = {
	SPD400,
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
	SPD200,
};

static int dev_speeds[DEVSPEED_NUMSPDS] = {
	SPD600,
	SPD800,
	SPD900,
	SPD1000,
	SPD900,
	SPD800,
	SPD600,
	SPD400,
};

static struct pll_init_data main_pll_config[NUM_SPDS] = {
	[SPD400]	= {MAIN_PLL, 100, 3, 2},
	[SPD600]	= {MAIN_PLL, 300, 6, 2},
	[SPD800]	= {MAIN_PLL, 200, 3, 2},
	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
};

static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
	[SPD200] =	{TETRIS_PLL, 250, 3, 10},
	[SPD400] =	{TETRIS_PLL, 100, 1, 6},
	[SPD600] =	{TETRIS_PLL, 100, 1, 4},
	[SPD800] =	{TETRIS_PLL, 400, 3, 4},
	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
};

static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};

struct pll_init_data *get_pll_init_data(int pll)
{
	int speed;
	struct pll_init_data *data = NULL;

	switch (pll) {
	case MAIN_PLL:
		speed = get_max_dev_speed(dev_speeds);
		data = &main_pll_config[speed];
		break;
	case TETRIS_PLL:
		speed = get_max_arm_speed(arm_speeds);
		data = &tetris_pll_config[speed];
		break;
	case NSS_PLL:
		data = &nss_pll_config;
		break;
	case UART_PLL:
		data = &uart_pll_config;
		break;
	case DDR3_PLL:
		data = &ddr3_pll_config;
		break;
	default:
		data = NULL;
	}

	return data;
}

s16 divn_val[16] = {
	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
	if (psc_enable_module(KS2_LPSC_MMC)) {
		printf("%s module enabled failed\n", __func__);
		return -1;
	}

	omap_mmc_init(0, 0, 0, -1, -1);
	omap_mmc_init(1, 0, 0, -1, -1);
	return 0;
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	init_plls();

	k2g_mux_config();

	/* deassert FLASH_HOLD */
	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
		     BIT(9));
	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
		     BIT(9));

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
	init_plls();
}
#endif

#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
	{
		.int_name	= "K2G_EMAC",
		.rx_flow	= 0,
		.phy_addr	= 0,
		.slave_port	= 1,
		.sgmii_link_type = SGMII_LINK_MAC_PHY,
		.phy_if          = PHY_INTERFACE_MODE_RGMII,
	},
};

int get_num_eth_ports(void)
{
	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
Commit	Line	Data
bda920c6 VA	1	/*
	2	* K2G EVM : Board initialization
	3	*
	4	* (C) Copyright 2015
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <asm/arch/clock.h>
91266ccb	11	#include <asm/ti-common/keystone_net.h>
3b68939f RQ	12	#include <asm/arch/psc_defs.h>
3b68939f RQ	13	#include <asm/arch/mmc_host_def.h>
dd78b8cf	14	#include "mux-k2g.h"
bda920c6	15
e6d71e1c VA	16	#define SYS_CLK 24000000
	17
	18	unsigned int external_clk[ext_clk_count] = {
	19	[sys_clk] = SYS_CLK,
	20	[pa_clk] = SYS_CLK,
	21	[tetris_clk] = SYS_CLK,
	22	[ddr3a_clk] = SYS_CLK,
	23	[uart_clk] = SYS_CLK,
	24	};
	25
ef76ebb1 LV	26	static int arm_speeds[DEVSPEED_NUMSPDS] = {
	27	SPD400,
	28	SPD600,
	29	SPD800,
	30	SPD900,
	31	SPD1000,
	32	SPD900,
	33	SPD800,
	34	SPD600,
	35	SPD400,
	36	SPD200,
	37	};
	38
	39	static int dev_speeds[DEVSPEED_NUMSPDS] = {
	40	SPD600,
	41	SPD800,
	42	SPD900,
	43	SPD1000,
	44	SPD900,
	45	SPD800,
	46	SPD600,
	47	SPD400,
	48	};
	49
	50	static struct pll_init_data main_pll_config[NUM_SPDS] = {
	51	[SPD400] = {MAIN_PLL, 100, 3, 2},
	52	[SPD600] = {MAIN_PLL, 300, 6, 2},
	53	[SPD800] = {MAIN_PLL, 200, 3, 2},
	54	[SPD900] = {TETRIS_PLL, 75, 1, 2},
	55	[SPD1000] = {TETRIS_PLL, 250, 3, 2},
	56	};
	57
	58	static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
	59	[SPD200] = {TETRIS_PLL, 250, 3, 10},
	60	[SPD400] = {TETRIS_PLL, 100, 1, 6},
	61	[SPD600] = {TETRIS_PLL, 100, 1, 4},
	62	[SPD800] = {TETRIS_PLL, 400, 3, 4},
	63	[SPD900] = {TETRIS_PLL, 75, 1, 2},
	64	[SPD1000] = {TETRIS_PLL, 250, 3, 2},
	65	};
	66
bda920c6 VA	67	static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
bda920c6 VA	68	static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
235dd6e8	69	static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
bda920c6 VA	70
	71	struct pll_init_data *get_pll_init_data(int pll)
	72	{
ef76ebb1	73	int speed;
bda920c6 VA	74	struct pll_init_data *data = NULL;
	75
	76	switch (pll) {
	77	case MAIN_PLL:
ef76ebb1 LV	78	speed = get_max_dev_speed(dev_speeds);
ef76ebb1 LV	79	data = &main_pll_config[speed];
bda920c6 VA	80	break;
bda920c6 VA	81	case TETRIS_PLL:
ef76ebb1 LV	82	speed = get_max_arm_speed(arm_speeds);
ef76ebb1 LV	83	data = &tetris_pll_config[speed];
bda920c6 VA	84	break;
	85	case NSS_PLL:
	86	data = &nss_pll_config;
	87	break;
	88	case UART_PLL:
	89	data = &uart_pll_config;
	90	break;
	91	case DDR3_PLL:
235dd6e8	92	data = &ddr3_pll_config;
bda920c6 VA	93	break;
	94	default:
	95	data = NULL;
	96	}
	97
	98	return data;
	99	}
	100
	101	s16 divn_val[16] = {
	102	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
	103	};
	104
3b68939f RQ	105	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
	106	int board_mmc_init(bd_t *bis)
	107	{
	108	if (psc_enable_module(KS2_LPSC_MMC)) {
	109	printf("%s module enabled failed\n", __func__);
	110	return -1;
	111	}
	112
	113	omap_mmc_init(0, 0, 0, -1, -1);
	114	omap_mmc_init(1, 0, 0, -1, -1);
	115	return 0;
	116	}
	117	#endif
	118
bda920c6 VA	119	#ifdef CONFIG_BOARD_EARLY_INIT_F
	120	int board_early_init_f(void)
	121	{
	122	init_plls();
	123
dd78b8cf VA	124	k2g_mux_config();
dd78b8cf VA	125
83b9bf11 LV	126	/* deassert FLASH_HOLD */
	127	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
	128	BIT(9));
	129	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
	130	BIT(9));
	131
bda920c6 VA	132	return 0;
	133	}
	134	#endif
	135
	136	#ifdef CONFIG_SPL_BUILD
	137	void spl_init_keystone_plls(void)
	138	{
	139	init_plls();
	140	}
	141	#endif
91266ccb VA	142
	143	#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
	144	struct eth_priv_t eth_priv_cfg[] = {
	145	{
	146	.int_name = "K2G_EMAC",
	147	.rx_flow = 0,
	148	.phy_addr = 0,
	149	.slave_port = 1,
	150	.sgmii_link_type = SGMII_LINK_MAC_PHY,
	151	.phy_if = PHY_INTERFACE_MODE_RGMII,
	152	},
	153	};
	154
	155	int get_num_eth_ports(void)
	156	{
	157	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
	158	}
	159	#endif