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Commit | Line | Data |
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dd78b8cf VA |
1 | /* |
2 | * K2G EVM: Pinmux configuration | |
3 | * | |
4 | * (C) Copyright 2015 | |
5 | * Texas Instruments Incorporated, <www.ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/mux-k2g.h> | |
13 | #include <asm/arch/hardware.h> | |
b9b342ea CJF |
14 | #include "board.h" |
15 | ||
16 | struct pin_cfg k2g_generic_pin_cfg[] = { | |
17 | /* UART0 */ | |
18 | { 115, MODE(0) }, /* SOC_UART0_RXD */ | |
19 | { 116, MODE(0) }, /* SOC_UART0_TXD */ | |
20 | ||
21 | /* I2C 0 */ | |
22 | { 223, MODE(0) }, /* SOC_I2C0_SCL */ | |
23 | { 224, MODE(0) }, /* SOC_I2C0_SDA */ | |
24 | ||
25 | /* I2C 1 */ | |
26 | { 225, MODE(0) }, /* SOC_I2C1_SCL */ | |
27 | { 226, MODE(0) }, /* SOC_I2C1_SDA */ | |
28 | { MAX_PIN_N, } | |
29 | }; | |
dd78b8cf VA |
30 | |
31 | struct pin_cfg k2g_evm_pin_cfg[] = { | |
32 | /* GPMC */ | |
33 | { 0, MODE(0) }, /* GPMCAD0 */ | |
34 | { 1, MODE(0) }, /* GPMCAD1 */ | |
35 | { 2, MODE(0) }, /* GPMCAD2 */ | |
36 | { 3, MODE(0) }, /* GPMCAD3 */ | |
37 | { 4, MODE(0) }, /* GPMCAD4 */ | |
38 | { 5, MODE(0) }, /* GPMCAD5 */ | |
39 | { 6, MODE(0) }, /* GPMCAD6 */ | |
40 | { 7, MODE(0) }, /* GPMCAD7 */ | |
41 | { 8, MODE(0) }, /* GPMCAD8 */ | |
42 | { 9, MODE(0) }, /* GPMCAD9 */ | |
43 | { 10, MODE(0) }, /* GPMCAD10 */ | |
44 | { 11, MODE(0) }, /* GPMCAD11 */ | |
45 | { 12, MODE(0) }, /* GPMCAD12 */ | |
46 | { 13, MODE(0) }, /* GPMCAD13 */ | |
47 | { 14, MODE(0) }, /* GPMCAD14 */ | |
48 | { 15, MODE(0) }, /* GPMCAD15 */ | |
49 | { 17, MODE(0) }, /* GPMCADVNALE */ | |
50 | { 18, MODE(0) }, /* GPMCOENREN */ | |
51 | { 19, MODE(0) }, /* GPMCWEN */ | |
52 | { 20, MODE(0) }, /* GPMCBE0NCLE */ | |
53 | { 22, MODE(0) }, /* GPMCWAIT0 */ | |
54 | { 24, MODE(0) }, /* GPMCWPN */ | |
55 | { 26, MODE(0) }, /* GPMCCSN0 */ | |
56 | ||
57 | /* GPIOs */ | |
58 | { 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */ | |
59 | { 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */ | |
60 | { 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */ | |
61 | { 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */ | |
62 | { 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */ | |
63 | { 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */ | |
64 | { 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */ | |
65 | { 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */ | |
66 | { 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */ | |
67 | { 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */ | |
68 | { 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */ | |
69 | { 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */ | |
70 | { 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/ | |
71 | { 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */ | |
72 | { 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */ | |
73 | { 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */ | |
74 | { 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */ | |
75 | { 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */ | |
76 | ||
77 | /* MLB */ | |
78 | { 23, MODE(2) }, /* SOC_MLBCLK */ | |
79 | { 25, MODE(2) }, /* SOC_MLBSIG */ | |
80 | { 27, MODE(2) }, /* SOC_MLBDAT */ | |
81 | ||
82 | /* DSS */ | |
83 | { 30, MODE(0) }, /* SOC_DSSDATA23 */ | |
84 | { 31, MODE(0) }, /* SOC_DSSDATA22 */ | |
85 | { 32, MODE(0) }, /* SOC_DSSDATA21 */ | |
86 | { 33, MODE(0) }, /* SOC_DSSDATA20 */ | |
87 | { 34, MODE(0) }, /* SOC_DSSDATA19 */ | |
88 | { 35, MODE(0) }, /* SOC_DSSDATA18 */ | |
89 | { 36, MODE(0) }, /* SOC_DSSDATA17 */ | |
90 | { 37, MODE(0) }, /* SOC_DSSDATA16 */ | |
91 | { 38, MODE(0) }, /* SOC_DSSDATA15 */ | |
92 | { 39, MODE(0) }, /* SOC_DSSDATA14 */ | |
93 | { 40, MODE(0) }, /* SOC_DSSDATA13 */ | |
94 | { 41, MODE(0) }, /* SOC_DSSDATA12 */ | |
95 | { 42, MODE(0) }, /* SOC_DSSDATA11 */ | |
96 | { 43, MODE(0) }, /* SOC_DSSDATA10 */ | |
97 | { 44, MODE(0) }, /* SOC_DSSDATA9 */ | |
98 | { 45, MODE(0) }, /* SOC_DSSDATA8 */ | |
99 | { 46, MODE(0) }, /* SOC_DSSDATA7 */ | |
100 | { 47, MODE(0) }, /* SOC_DSSDATA6 */ | |
101 | { 48, MODE(0) }, /* SOC_DSSDATA5 */ | |
102 | { 49, MODE(0) }, /* SOC_DSSDATA4 */ | |
103 | { 50, MODE(0) }, /* SOC_DSSDATA3 */ | |
104 | { 51, MODE(0) }, /* SOC_DSSDATA2 */ | |
105 | { 52, MODE(0) }, /* SOC_DSSDATA1 */ | |
106 | { 53, MODE(0) }, /* SOC_DSSDATA0 */ | |
107 | { 54, MODE(0) }, /* SOC_DSSVSYNC */ | |
108 | { 55, MODE(0) }, /* SOC_DSSHSYNC */ | |
109 | { 56, MODE(0) }, /* SOC_DSSPCLK */ | |
110 | { 57, MODE(0) }, /* SOC_DSS_DE */ | |
111 | { 58, MODE(0) }, /* SOC_DSS_FID */ | |
112 | { 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */ | |
113 | ||
114 | /* MMC1 */ | |
115 | { 59, MODE(0) }, /* SOC_MMC1_DAT7 */ | |
116 | { 60, MODE(0) }, /* SOC_MMC1_DAT6 */ | |
117 | { 61, MODE(0) }, /* SOC_MMC1_DAT5 */ | |
118 | { 62, MODE(0) }, /* SOC_MMC1_DAT4 */ | |
119 | { 63, MODE(0) }, /* SOC_MMC1_DAT3 */ | |
120 | { 64, MODE(0) }, /* SOC_MMC1_DAT2 */ | |
121 | { 65, MODE(0) }, /* SOC_MMC1_DAT1 */ | |
122 | { 66, MODE(0) }, /* SOC_MMC1_DAT0 */ | |
123 | { 67, MODE(0) }, /* SOC_MMC1_CLK */ | |
124 | { 68, MODE(0) }, /* SOC_MMC1_CMD */ | |
125 | { 69, MODE(0) }, /* MMC1SDCD TP125 */ | |
126 | { 70, MODE(0) }, /* SOC_MMC1_SDWP */ | |
127 | { 71, MODE(0) }, /* MMC1POW TP124 */ | |
128 | ||
129 | /* RGMII */ | |
130 | { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ | |
131 | { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ | |
132 | { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ | |
133 | { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ | |
134 | { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ | |
135 | { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ | |
136 | { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ | |
137 | { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ | |
138 | { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ | |
139 | { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ | |
140 | { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ | |
141 | { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ | |
142 | { 98, MODE(0) }, /* SOC_MDIO_DATA */ | |
143 | { 99, MODE(0) }, /* SOC_MDIO_CLK */ | |
144 | ||
145 | /* PWM */ | |
146 | { 73, MODE(4) }, /* SOC_EHRPWM3A */ | |
147 | { 74, MODE(4) }, /* SOC_EHRPWM3B */ | |
148 | { 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */ | |
149 | { 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */ | |
150 | { 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */ | |
151 | { 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */ | |
152 | { 199, MODE(4) }, /* SOC_EHRPWM4A */ | |
153 | { 200, MODE(4) }, /* SOC_EHRPWM4B */ | |
154 | { 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */ | |
155 | { 219, MODE(4) }, /* SOC_EHRPWM5A */ | |
156 | { 220, MODE(4) }, /* SOC_EHRPWM5B */ | |
157 | { 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */ | |
158 | ||
159 | /* SPI3 */ | |
160 | { 86, MODE(1) }, /* SOC_SPI3_SCS0 */ | |
161 | { 88, MODE(1) }, /* SOC_SPI3_CLK */ | |
162 | { 89, MODE(1) }, /* SOC_SPI3_MISO */ | |
163 | { 90, MODE(1) }, /* SOC_SPI3_MOSI */ | |
164 | ||
165 | /* CLK */ | |
166 | { 97, MODE(0) }, /* SMD - TP132 */ | |
167 | ||
168 | /* SPI0 */ | |
169 | { 100, MODE(0) }, /* SOC_SPI0_SCS0 */ | |
170 | { 101, MODE(0) }, /* SOC_SPI0_SCS1 */ | |
171 | { 102, MODE(0) }, /* SOC_SPI0_CLK */ | |
172 | { 103, MODE(0) }, /* SOC_SPI0_MISO */ | |
173 | { 104, MODE(0) }, /* SOC_SPI0_MOSI */ | |
174 | ||
175 | /* SPI1 NORFLASH */ | |
176 | { 105, MODE(0) }, /* SOC_SPI1_SCS0 */ | |
177 | { 107, MODE(0) }, /* SOC_SPI1_CLK */ | |
178 | { 108, MODE(0) }, /* SOC_SPI1_MISO */ | |
179 | { 109, MODE(0) }, /* SOC_SPI1_MOSI */ | |
180 | ||
181 | /* SPI2 */ | |
182 | { 110, MODE(0) }, /* SOC_SPI2_SCS0 */ | |
183 | { 111, MODE(1) }, /* SOC_HOUT */ | |
184 | { 112, MODE(0) }, /* SOC_SPI2_CLK */ | |
185 | { 113, MODE(0) }, /* SOC_SPI2_MISO */ | |
186 | { 114, MODE(0) }, /* SOC_SPI2_MOSI */ | |
187 | ||
188 | /* UART0 */ | |
189 | { 115, MODE(0) }, /* SOC_UART0_RXD */ | |
190 | { 116, MODE(0) }, /* SOC_UART0_TXD */ | |
191 | { 117, MODE(0) }, /* SOC_UART0_CTSn */ | |
192 | { 118, MODE(0) }, /* SOC_UART0_RTSn */ | |
193 | ||
194 | /* UART1 */ | |
195 | { 119, MODE(0) }, /* SOC_UART1_RXD */ | |
196 | { 120, MODE(0) }, /* SOC_UART1_TXD */ | |
197 | { 121, MODE(0) }, /* SOC_UART1_CTSn */ | |
198 | { 122, MODE(0) }, /* SOC_UART1_RTSn */ | |
199 | ||
200 | /* UART2 */ | |
201 | { 123, MODE(0) }, /* SOC_UART2_RXD */ | |
202 | { 124, MODE(0) }, /* SOC_UART2_TXD */ | |
203 | { 125, MODE(0) }, /* UART0_TXVR_EN */ | |
204 | { 126, MODE(4) }, /* SOC_CPTS_TS_COMP */ | |
205 | ||
206 | /* DCAN */ | |
207 | { 127, MODE(0) }, /* SOC_DCAN0_TX */ | |
208 | { 128, MODE(0) }, /* SOC_DCAN0_RX */ | |
209 | { 137, MODE(1) }, /* SOC_DCAN1_TX */ | |
210 | { 138, MODE(1) }, /* SOC_DCAN1_RX */ | |
211 | ||
212 | /* QSPI */ | |
213 | { 129, MODE(0) }, /* SOC_QSPI_CLK */ | |
214 | { 130, MODE(0) }, /* SOC_QSPI_RTCLK */ | |
215 | { 131, MODE(0) }, /* SOC_QSPI_D0 */ | |
216 | { 132, MODE(0) }, /* SOC_QSPI_D1 */ | |
217 | { 133, MODE(0) }, /* SOC_QSPI_D2 */ | |
218 | { 134, MODE(0) }, /* SOC_QSPI_D3 */ | |
219 | { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ | |
220 | { 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */ | |
221 | ||
222 | /* MCASP2 */ | |
223 | { 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */ | |
224 | { 140, MODE(4) }, /* SOC_MCASP2AXR1 */ | |
225 | { 141, MODE(4) }, /* SOC_MCASP2AXR2 */ | |
226 | { 142, MODE(4) }, /* SOC_MCASP2AXR3 */ | |
227 | { 143, MODE(4) }, /* SOC_MCASP2AXR4 */ | |
228 | { 144, MODE(4) }, /* SOC_MCASP2AXR5 */ | |
229 | { 145, MODE(4) }, /* SOC_McASP2ACLKR */ | |
230 | { 146, MODE(4) }, /* SOC_McASP2FSR */ | |
231 | { 147, MODE(4) }, /* SOC_McASP2AHCLKR */ | |
232 | { 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */ | |
233 | { 149, MODE(4) }, /* SOC_McASP2FSX */ | |
234 | { 150, MODE(4) }, /* SOC_McASP2AHCLKX */ | |
235 | { 151, MODE(4) }, /* SOC_McASP2ACLKX */ | |
236 | ||
237 | /* MCASP1 */ | |
238 | { 152, MODE(4) }, /* SOC_MCASP1ACLKR */ | |
239 | { 153, MODE(4) }, /* SOC_MCASP1FSR */ | |
240 | { 154, MODE(4) }, /* SOC_MCASP1AHCLKR */ | |
241 | { 155, MODE(4) }, /* SOC_MCASP1ACLKX */ | |
242 | { 156, MODE(4) }, /* SOC_MCASP1FSX */ | |
243 | { 157, MODE(4) }, /* SOC_MCASP1AHCLKX */ | |
244 | { 158, MODE(4) }, /* SOC_MCASP1AMUTE */ | |
245 | { 159, MODE(4) }, /* SOC_MCASP1AXR0 */ | |
246 | { 160, MODE(4) }, /* SOC_MCASP1AXR1 */ | |
247 | { 161, MODE(4) }, /* SOC_MCASP1AXR2 */ | |
248 | { 162, MODE(4) }, /* SOC_MCASP1AXR3 */ | |
249 | { 163, MODE(4) }, /* SOC_MCASP1AXR4 */ | |
250 | { 164, MODE(4) }, /* SOC_MCASP1AXR5 */ | |
251 | { 165, MODE(4) }, /* SOC_MCASP1AXR6 */ | |
252 | { 166, MODE(4) }, /* SOC_MCASP1AXR7 */ | |
253 | { 167, MODE(4) }, /* SOC_MCASP1AXR8 */ | |
254 | { 168, MODE(4) }, /* SOC_MCASP1AXR9 */ | |
255 | ||
256 | /* MCASP0 */ | |
257 | { 169, MODE(4) }, /* SOC_MCASP0AMUTE */ | |
258 | { 170, MODE(4) }, /* SOC_MCASP0ACLKR */ | |
259 | { 171, MODE(4) }, /* SOC_MCASP0FSR */ | |
260 | { 172, MODE(4) }, /* SOC_MCASP0AHCLKR */ | |
261 | { 173, MODE(4) }, /* SOC_MCASP0ACLKX */ | |
262 | { 174, MODE(4) }, /* SOC_MCASP0FSX */ | |
263 | { 175, MODE(4) }, /* SOC_MCASP0AHCLKX */ | |
264 | { 176, MODE(4) }, /* SOC_MCASP0AXR0 */ | |
265 | { 177, MODE(4) }, /* SOC_MCASP0AXR1 */ | |
266 | { 178, MODE(4) }, /* SOC_MCASP0AXR2 */ | |
267 | { 179, MODE(4) }, /* SOC_MCASP0AXR3 */ | |
268 | { 180, MODE(4) }, /* SOC_MCASP0AXR4 */ | |
269 | { 181, MODE(4) }, /* SOC_MCASP0AXR5 */ | |
270 | { 182, MODE(4) }, /* SOC_MCASP0AXR6 */ | |
271 | { 183, MODE(4) }, /* SOC_MCASP0AXR7 */ | |
272 | { 184, MODE(4) }, /* SOC_MCASP0AXR8 */ | |
273 | { 185, MODE(4) }, /* SOC_MCASP0AXR9 */ | |
274 | { 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */ | |
275 | { 188, MODE(4) }, /* SOC_MCASP0AXR12 */ | |
276 | { 189, MODE(4) }, /* SOC_MCASP0AXR13 */ | |
277 | { 190, MODE(4) }, /* SOC_MCASP0AXR14 */ | |
278 | { 191, MODE(4) }, /* SOC_MCASP0AXR15 */ | |
279 | ||
280 | /* MMC0 */ | |
281 | { 192, MODE(2) }, /* SOC_MMC0_DAT3 */ | |
282 | { 193, MODE(2) }, /* SOC_MMC0_DAT2 */ | |
283 | { 194, MODE(2) }, /* SOC_MMC0_DAT1 */ | |
284 | { 195, MODE(2) }, /* SOC_MMC0_DAT0 */ | |
285 | { 196, MODE(2) }, /* SOC_MMC0_CLK */ | |
286 | { 197, MODE(2) }, /* SOC_MMC0_CMD */ | |
287 | { 187, MODE(2) }, /* SOC_MMC0_SDCD */ | |
288 | ||
289 | /* McBSP */ | |
290 | { 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */ | |
291 | { 29, MODE(2) }, /* SOC_TIMO1 */ | |
292 | { 210, MODE(2) }, /* SOC_MCBSPDR */ | |
293 | { 211, MODE(2) }, /* SOC_MCBSPDX */ | |
294 | { 212, MODE(2) }, /* SOC_MCBSPFSX */ | |
295 | { 213, MODE(2) }, /* SOC_MCBSPCLKX */ | |
296 | { 214, MODE(2) }, /* SOC_MCBSPFSR */ | |
297 | { 215, MODE(2) }, /* SOC_MCBSPCLKR */ | |
298 | ||
299 | /* I2C */ | |
300 | { 223, MODE(0) }, /* SOC_I2C0_SCL */ | |
301 | { 224, MODE(0) }, /* SOC_I2C0_SDA */ | |
302 | { 225, MODE(0) }, /* SOC_I2C1_SCL */ | |
303 | { 226, MODE(0) }, /* SOC_I2C1_SDA */ | |
304 | { 227, MODE(0) }, /* SOC_I2C2_SCL */ | |
305 | { 228, MODE(0) }, /* SOC_I2C2_SDA */ | |
306 | { 229, MODE(0) }, /* NMIz */ | |
307 | { 230, MODE(0) }, /* LRESETz */ | |
308 | { 231, MODE(0) }, /* LRESETNMIENz */ | |
309 | ||
310 | { 235, MODE(0) }, | |
311 | { 236, MODE(0) }, | |
312 | { 237, MODE(0) }, | |
313 | { 238, MODE(0) }, | |
314 | { 239, MODE(0) }, | |
315 | { 240, MODE(0) }, | |
316 | { 241, MODE(0) }, | |
317 | { 242, MODE(0) }, | |
318 | { 243, MODE(0) }, | |
319 | { 244, MODE(0) }, | |
320 | ||
321 | { 258, MODE(0) }, /* USB0DRVVBUS */ | |
322 | { 259, MODE(0) }, /* USB1DRVVBUS */ | |
323 | { MAX_PIN_N, } | |
324 | }; | |
325 | ||
b9b342ea CJF |
326 | struct pin_cfg k2g_ice_evm_pin_cfg[] = { |
327 | /* MMC 1 */ | |
328 | { 63, MODE(0) | PIN_PTD }, /* MMC1_DAT3.MMC1_DAT3 */ | |
329 | { 64, MODE(0) | PIN_PTU }, /* MMC1_DAT2.MMC1_DAT2 */ | |
330 | { 65, MODE(0) | PIN_PTU }, /* MMC1_DAT1.MMC1_DAT1 */ | |
331 | { 66, MODE(0) | PIN_PTD }, /* MMC1_DAT0.MMC1_DAT0 */ | |
332 | { 67, MODE(0) | PIN_PTD }, /* MMC1_CLK.MMC1_CLK */ | |
333 | { 68, MODE(0) | PIN_PTD }, /* MMC1_CMD.MMC1_CMD */ | |
334 | { 69, MODE(3) | PIN_PTU }, /* MMC1_SDCD.GPIO0_69 */ | |
335 | { 70, MODE(0) | PIN_PTU }, /* MMC1_SDWP.MMC1_SDWP */ | |
336 | { 71, MODE(0) | PIN_PTD }, /* MMC1_POW.MMC1_POW */ | |
337 | ||
338 | /* I2C 0 */ | |
339 | { 223, MODE(0) }, /* SOC_I2C0_SCL */ | |
340 | { 224, MODE(0) }, /* SOC_I2C0_SDA */ | |
a47506ff V |
341 | |
342 | /* QSPI */ | |
343 | { 129, MODE(0) }, /* SOC_QSPI_CLK */ | |
344 | { 130, MODE(0) }, /* SOC_QSPI_RTCLK */ | |
345 | { 131, MODE(0) }, /* SOC_QSPI_D0 */ | |
346 | { 132, MODE(0) }, /* SOC_QSPI_D1 */ | |
347 | { 133, MODE(0) }, /* SOC_QSPI_D2 */ | |
348 | { 134, MODE(0) }, /* SOC_QSPI_D3 */ | |
349 | { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ | |
b9b342ea CJF |
350 | { MAX_PIN_N, } |
351 | }; | |
352 | ||
dd78b8cf VA |
353 | void k2g_mux_config(void) |
354 | { | |
b9b342ea CJF |
355 | if (!board_ti_was_eeprom_read()) { |
356 | configure_pin_mux(k2g_generic_pin_cfg); | |
4849d954 | 357 | } else if (board_is_k2g_gp() || board_is_k2g_g1()) { |
b9b342ea CJF |
358 | configure_pin_mux(k2g_evm_pin_cfg); |
359 | } else if (board_is_k2g_ice()) { | |
360 | configure_pin_mux(k2g_ice_evm_pin_cfg); | |
361 | } else { | |
362 | puts("Unknown board, cannot configure pinmux."); | |
363 | hang(); | |
364 | } | |
dd78b8cf | 365 | } |