[people/ms/u-boot.git] / board / ti / omap1510inn / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 *
 * -- Some bits of code used from rrload's head_OMAP1510.s --
 * Copyright (C) 2002 RidgeRun, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1510)
#include <./configs/omap1510.h>
#endif

#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))


_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE        /* sdram load addr from config.mk */

.globl lowlevel_init
lowlevel_init:

	/*
	 * Configure 1510 pins functions to match our board.
	 */
	ldr     r0, REG_PULL_DWN_CTRL_0
	ldr     r1, VAL_PULL_DWN_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_1
	ldr     r1, VAL_PULL_DWN_CTRL_1
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_2
	ldr     r1, VAL_PULL_DWN_CTRL_2
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_3
	ldr     r1, VAL_PULL_DWN_CTRL_3
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_4
	ldr     r1, VAL_FUNC_MUX_CTRL_4
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_5
	ldr     r1, VAL_FUNC_MUX_CTRL_5
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_6
	ldr     r1, VAL_FUNC_MUX_CTRL_6
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_7
	ldr     r1, VAL_FUNC_MUX_CTRL_7
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_8
	ldr     r1, VAL_FUNC_MUX_CTRL_8
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_9
	ldr     r1, VAL_FUNC_MUX_CTRL_9
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_A
	ldr     r1, VAL_FUNC_MUX_CTRL_A
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_B
	ldr     r1, VAL_FUNC_MUX_CTRL_B
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_C
	ldr     r1, VAL_FUNC_MUX_CTRL_C
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_D
	ldr     r1, VAL_FUNC_MUX_CTRL_D
	str     r1, [r0]
	ldr     r0, REG_VOLTAGE_CTRL_0
	ldr     r1, VAL_VOLTAGE_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_TEST_DBG_CTRL_0
	ldr     r1, VAL_TEST_DBG_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_MOD_CONF_CTRL_0
	ldr     r1, VAL_MOD_CONF_CTRL_0
	str     r1, [r0]

	/* Move to 1510 mode */
	ldr     r0, REG_COMP_MODE_CTRL_0
	ldr     r1, VAL_COMP_MODE_CTRL_0
	str     r1, [r0]

	/* Set up Traffic Ctlr*/
	ldr r0, REG_TC_IMIF_PRIO
	mov r1, #0x0
	str r1, [r0]
	ldr r0, REG_TC_EMIFS_PRIO
	str r1, [r0]
	ldr r0, REG_TC_EMIFF_PRIO
	str r1, [r0]

	ldr r0, REG_TC_EMIFS_CONFIG
	ldr r1, [r0]
	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */

	/* Setup some clock domains */
	ldr r1, =OMAP1510_CLKS
	ldr r0, REG_ARM_IDLECT2
	strh r1, [r0]  /* CLKM, Clock domain control. */

	mov r1, #0x01  /* PER_EN bit */
	ldr r0, REG_ARM_RSTCT2
	strh r1, [r0]  /* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable  */
	/* I supposidly need to enable the dsp clock before switching */
	mov r1, #0x1000
	ldr r0, REG_ARM_SYSST
	strh r1, [r0]
	mov r0, #0x400
1:
	subs r0, r0, #0x1   /* wait for any bubbles to finish */
	bne 1b

	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
	ldr r0, REG_ARM_CKCTL
	strh r1, [r0]

	/* setup DPLL 1 */
	ldr r1, VAL_DPLL1_CTL
	ldr r0, REG_DPLL1_CTL
	strh r1, [r0]
	ands r1, r1, #0x10  /* Check if PLL is enabled. */
	beq lock_end        /* Do not look for lock if BYPASS selected */
2:
	ldrh r1, [r0]
	ands r1, r1, #0x01  /* Check the LOCK bit. */
	beq 2b              /* ...loop until bit goes hi. */
lock_end:

	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	mov r0, #0x10000000                 /* Load physical SDRAM base. */
	mov r1, pc                          /* Get current execution location. */
	/* Zero all but top 6 bits of PC, as they alone detect whether an
	 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
	 * valid range for SDRAM on the OMAP 1510/5910.
	 */
	and r1, r1, #0xfc000000
	cmp r1, r0			/* Compare. */
	beq skip_sdram			/* Skip over EMIF-fast initialization
					 * if running from SDRAM.
					 */

	/*
	 * Delay for SDRAM initialization.
	 */
	mov r3, #0x1800                        /* value should be checked */
3:
	subs r3, r3, #0x1                     /* Decrement count */
	bne 3b

	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */
	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
	str r3, [r2]                        /* Store the passed value with AR disabled. */

	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
	str r1, [r2]                        /* Store the passed value.*/

	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
	str r0, [r2]                        /* Store the passed value. */

	/*
	 * Delay for SDRAM initialization.
	 */
	mov r3, #0x1800
4:
	subs r3, r3, #1                     /* Decrement count. */
	bne 4b

skip_sdram:

	/* slow interface */
	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	str r1, [r0] /* Chip Select 0 */
	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	str r1, [r0] /* Chip Select 1 */
	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
	ldr r0, REG_TC_EMIFS_CS2_CONFIG
	str r1, [r0] /* Chip Select 2 */
	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	str r1, [r0] /* Chip Select 3 */

 /* Next, Enable the RS232 Line Drivers in the FPGA. */
 /* Also, power on the audio CODEC's amplifier here, */
 /* which will make a noise on the audio output. */
 /* This is done here instead of in the kernel so there */
 /* isn't a loud popping noise at the start of each */
 /* song. */
 /* Also, disable the CODEC's clocks. */
 /* omap1510-HelenP1 [specific] */

	ldr r0, REG_FPGA_POWER
	mov r1, #0
	ldr r2, REG_FPGA_DIP_SWITCH
	ldrb r3, [r2]
	cmp r3, #0x8
	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
	strb r1, [r0]
	ldr r0, REG_FPGA_AUDIO
	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
	strb r1, [r0]

	/* back to arch calling code */
	mov	pc, lr

/* the literal pools origin */
	.ltorg

/* OMAP configuration registers */
REG_FUNC_MUX_CTRL_0:		/* 32 bits */
	.word 0xfffe1000
REG_FUNC_MUX_CTRL_1:		/* 32 bits */
	.word 0xfffe1004
REG_FUNC_MUX_CTRL_2:		/* 32 bits */
	.word 0xfffe1008
REG_COMP_MODE_CTRL_0:		/* 32 bits */
	.word 0xfffe100c
REG_FUNC_MUX_CTRL_3:		/* 32 bits */
	.word 0xfffe1010
REG_FUNC_MUX_CTRL_4:		/* 32 bits */
	.word 0xfffe1014
REG_FUNC_MUX_CTRL_5:		/* 32 bits */
	.word 0xfffe1018
REG_FUNC_MUX_CTRL_6:		/* 32 bits */
	.word 0xfffe101c
REG_FUNC_MUX_CTRL_7:		/* 32 bits */
	.word 0xfffe1020
REG_FUNC_MUX_CTRL_8:		/* 32 bits */
	.word 0xfffe1024
REG_FUNC_MUX_CTRL_9:		/* 32 bits */
	.word 0xfffe1028
REG_FUNC_MUX_CTRL_A:		/* 32 bits */
	.word 0xfffe102C
REG_FUNC_MUX_CTRL_B:		/* 32 bits */
	.word 0xfffe1030
REG_FUNC_MUX_CTRL_C:		/* 32 bits */
	.word 0xfffe1034
REG_FUNC_MUX_CTRL_D:		/* 32 bits */
	.word 0xfffe1038
REG_PULL_DWN_CTRL_0:		/* 32 bits */
	.word 0xfffe1040
REG_PULL_DWN_CTRL_1:		/* 32 bits */
	.word 0xfffe1044
REG_PULL_DWN_CTRL_2:		/* 32 bits */
	.word 0xfffe1048
REG_PULL_DWN_CTRL_3:		/* 32 bits */
	.word 0xfffe104c
REG_VOLTAGE_CTRL_0:		/* 32 bits */
	.word 0xfffe1060
REG_TEST_DBG_CTRL_0:		/* 32 bits */
	.word 0xfffe1070
REG_MOD_CONF_CTRL_0:		/* 32 bits */
	.word 0xfffe1080
REG_TC_IMIF_PRIO:		/* 32 bits */
	.word 0xfffecc00
REG_TC_EMIFS_PRIO:		/* 32 bits */
	.word 0xfffecc04
REG_TC_EMIFF_PRIO:		/* 32 bits */
	.word 0xfffecc08
REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c
REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
	.word 0xfffecc20
REG_TC_EMIFF_MRS:		/* 32 bits */
	.word 0xfffecc24
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00
/* identification code register */
REG_IDCODE:			/* 32 bits */
	.word 0xfffed404

/* Innovator specific */
REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
	.word 0x08000003
REG_FPGA_POWER:			/* 8 bits */
	.word 0x08000005
REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
	.word 0x0800000c
REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
	.word 0x0800000e

VAL_COMP_MODE_CTRL_0:
	.word 0x0000eaef
VAL_FUNC_MUX_CTRL_4:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_5:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_6:
	.word 0x00000001
VAL_FUNC_MUX_CTRL_7:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_8:
	.word 0x10001200
VAL_FUNC_MUX_CTRL_9:
	.word 0x01201012
VAL_FUNC_MUX_CTRL_A:
	.word 0x00000248
VAL_FUNC_MUX_CTRL_B:
	.word 0x00000248
VAL_FUNC_MUX_CTRL_C:
	.word 0x09000000
VAL_FUNC_MUX_CTRL_D:
	.word 0x00000000
VAL_PULL_DWN_CTRL_0:
	.word 0x11a10000
VAL_PULL_DWN_CTRL_1:
	.word 0x2e047fff
VAL_PULL_DWN_CTRL_2:
	.word 0xffd603a6
VAL_PULL_DWN_CTRL_3:
	.word 0x00003e03
VAL_VOLTAGE_CTRL_0:
	.word 0x00000007
VAL_TEST_DBG_CTRL_0:
	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
	 *   This slows down internal SRAM accesses.
	 */
	.word 0x00000007
VAL_MOD_CONF_CTRL_0:
	.word 0x0b000008
VAL_ARM_CKCTL:
	.word 0x010f
VAL_DPLL1_CTL:
	.word 0x2710
VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
	.word 0x00001149
VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
	.word 0x00004158
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x0000f559
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x00003331
VAL_TC_EMIFF_SDRAM_CONFIG:
	.word 0x010290fc
VAL_TC_EMIFF_MRS:
	.word 0x00000027
Commit	Line	Data
2e5983d2 WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* -- Some bits of code used from rrload's head_OMAP1510.s --
	8	* Copyright (C) 2002 RidgeRun, Inc.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
2e5983d2 WD	11	*/
	12
	13	#include <config.h>
	14	#include <version.h>
	15
	16	#if defined(CONFIG_OMAP1510)
	17	#include <./configs/omap1510.h>
	18	#endif
	19
	20	#define OMAP1510_CLKS ((1<<EN_XORPCK)\|(1<<EN_PERCK)\|(1<<EN_TIMCK)\|(1<<EN_GPIOCK))
	21
	22
	23	_TEXT_BASE:
14d0a02a	24	.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
2e5983d2	25
87cb6862 WD	26	.globl lowlevel_init
87cb6862 WD	27	lowlevel_init:
2e5983d2	28
945af8d7 WD	29	/*
	30	* Configure 1510 pins functions to match our board.
	31	*/
	32	ldr r0, REG_PULL_DWN_CTRL_0
	33	ldr r1, VAL_PULL_DWN_CTRL_0
	34	str r1, [r0]
	35	ldr r0, REG_PULL_DWN_CTRL_1
	36	ldr r1, VAL_PULL_DWN_CTRL_1
	37	str r1, [r0]
	38	ldr r0, REG_PULL_DWN_CTRL_2
	39	ldr r1, VAL_PULL_DWN_CTRL_2
	40	str r1, [r0]
	41	ldr r0, REG_PULL_DWN_CTRL_3
	42	ldr r1, VAL_PULL_DWN_CTRL_3
	43	str r1, [r0]
	44	ldr r0, REG_FUNC_MUX_CTRL_4
	45	ldr r1, VAL_FUNC_MUX_CTRL_4
	46	str r1, [r0]
	47	ldr r0, REG_FUNC_MUX_CTRL_5
	48	ldr r1, VAL_FUNC_MUX_CTRL_5
	49	str r1, [r0]
	50	ldr r0, REG_FUNC_MUX_CTRL_6
	51	ldr r1, VAL_FUNC_MUX_CTRL_6
	52	str r1, [r0]
	53	ldr r0, REG_FUNC_MUX_CTRL_7
	54	ldr r1, VAL_FUNC_MUX_CTRL_7
	55	str r1, [r0]
	56	ldr r0, REG_FUNC_MUX_CTRL_8
	57	ldr r1, VAL_FUNC_MUX_CTRL_8
	58	str r1, [r0]
	59	ldr r0, REG_FUNC_MUX_CTRL_9
	60	ldr r1, VAL_FUNC_MUX_CTRL_9
	61	str r1, [r0]
	62	ldr r0, REG_FUNC_MUX_CTRL_A
	63	ldr r1, VAL_FUNC_MUX_CTRL_A
	64	str r1, [r0]
	65	ldr r0, REG_FUNC_MUX_CTRL_B
	66	ldr r1, VAL_FUNC_MUX_CTRL_B
	67	str r1, [r0]
	68	ldr r0, REG_FUNC_MUX_CTRL_C
	69	ldr r1, VAL_FUNC_MUX_CTRL_C
	70	str r1, [r0]
6f21347d WD	71	ldr r0, REG_FUNC_MUX_CTRL_D
	72	ldr r1, VAL_FUNC_MUX_CTRL_D
	73	str r1, [r0]
945af8d7 WD	74	ldr r0, REG_VOLTAGE_CTRL_0
	75	ldr r1, VAL_VOLTAGE_CTRL_0
	76	str r1, [r0]
	77	ldr r0, REG_TEST_DBG_CTRL_0
	78	ldr r1, VAL_TEST_DBG_CTRL_0
	79	str r1, [r0]
	80	ldr r0, REG_MOD_CONF_CTRL_0
	81	ldr r1, VAL_MOD_CONF_CTRL_0
	82	str r1, [r0]
2e5983d2	83
945af8d7 WD	84	/* Move to 1510 mode */
	85	ldr r0, REG_COMP_MODE_CTRL_0
	86	ldr r1, VAL_COMP_MODE_CTRL_0
	87	str r1, [r0]
2e5983d2	88
945af8d7 WD	89	/* Set up Traffic Ctlr*/
	90	ldr r0, REG_TC_IMIF_PRIO
	91	mov r1, #0x0
	92	str r1, [r0]
	93	ldr r0, REG_TC_EMIFS_PRIO
	94	str r1, [r0]
	95	ldr r0, REG_TC_EMIFF_PRIO
	96	str r1, [r0]
2e5983d2	97
945af8d7 WD	98	ldr r0, REG_TC_EMIFS_CONFIG
	99	ldr r1, [r0]
	100	bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
	101	bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
	102	str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
2e5983d2	103
945af8d7 WD	104	/* Setup some clock domains */
	105	ldr r1, =OMAP1510_CLKS
	106	ldr r0, REG_ARM_IDLECT2
	107	strh r1, [r0] /* CLKM, Clock domain control. */
2e5983d2	108
945af8d7 WD	109	mov r1, #0x01 /* PER_EN bit */
	110	ldr r0, REG_ARM_RSTCT2
	111	strh r1, [r0] /* CLKM; Peripheral reset. */
2e5983d2	112
945af8d7 WD	113	/* Set CLKM to Sync-Scalable */
	114	/* I supposidly need to enable the dsp clock before switching */
	115	mov r1, #0x1000
	116	ldr r0, REG_ARM_SYSST
	117	strh r1, [r0]
	118	mov r0, #0x400
2e5983d2	119	1:
945af8d7 WD	120	subs r0, r0, #0x1 /* wait for any bubbles to finish */
945af8d7 WD	121	bne 1b
2e5983d2	122
945af8d7 WD	123	ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
	124	ldr r0, REG_ARM_CKCTL
	125	strh r1, [r0]
2e5983d2	126
945af8d7 WD	127	/* setup DPLL 1 */
	128	ldr r1, VAL_DPLL1_CTL
	129	ldr r0, REG_DPLL1_CTL
	130	strh r1, [r0]
	131	ands r1, r1, #0x10 /* Check if PLL is enabled. */
	132	beq lock_end /* Do not look for lock if BYPASS selected */
2e5983d2	133	2:
945af8d7 WD	134	ldrh r1, [r0]
	135	ands r1, r1, #0x01 /* Check the LOCK bit. */
	136	beq 2b /* ...loop until bit goes hi. */
2e5983d2 WD	137	lock_end:
2e5983d2 WD	138
945af8d7	139	/* Set memory timings corresponding to the new clock speed */
2e5983d2	140
945af8d7 WD	141	/* Check execution location to determine current execution location
	142	* and branch to appropriate initialization code.
	143	*/
	144	mov r0, #0x10000000 /* Load physical SDRAM base. */
	145	mov r1, pc /* Get current execution location. */
8b74bf31	146	/* Zero all but top 6 bits of PC, as they alone detect whether an
c15f3120 WD	147	* address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
	148	* valid range for SDRAM on the OMAP 1510/5910.
	149	*/
	150	and r1, r1, #0xfc000000
	151	cmp r1, r0 /* Compare. */
	152	beq skip_sdram /* Skip over EMIF-fast initialization
	153	* if running from SDRAM.
	154	*/
2e5983d2	155
945af8d7 WD	156	/*
	157	* Delay for SDRAM initialization.
	158	*/
	159	mov r3, #0x1800 /* value should be checked */
2e5983d2	160	3:
945af8d7 WD	161	subs r3, r3, #0x1 /* Decrement count */
945af8d7 WD	162	bne 3b
2e5983d2	163
945af8d7 WD	164	/*
	165	* Set SDRAM control values. Disable refresh before MRS command.
	166	*/
	167	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
	168	bic r3, r0, #0xC /* (BIT3\|BIT2) ulConfig with auto-refresh disabled. */
	169	orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
	170	orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
	171	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
	172	str r3, [r2] /* Store the passed value with AR disabled. */
2e5983d2	173
945af8d7 WD	174	ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
	175	ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
	176	str r1, [r2] /* Store the passed value.*/
2e5983d2	177
945af8d7 WD	178	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
945af8d7 WD	179	str r0, [r2] /* Store the passed value. */
2e5983d2	180
945af8d7 WD	181	/*
	182	* Delay for SDRAM initialization.
	183	*/
	184	mov r3, #0x1800
2e5983d2	185	4:
945af8d7 WD	186	subs r3, r3, #1 /* Decrement count. */
945af8d7 WD	187	bne 4b
2e5983d2 WD	188
	189	skip_sdram:
	190
945af8d7 WD	191	/* slow interface */
	192	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	193	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	194	str r1, [r0] /* Chip Select 0 */
	195	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	196	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	197	str r1, [r0] /* Chip Select 1 */
	198	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
	199	ldr r0, REG_TC_EMIFS_CS2_CONFIG
	200	str r1, [r0] /* Chip Select 2 */
	201	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	202	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	203	str r1, [r0] /* Chip Select 3 */
2e5983d2 WD	204
	205	/* Next, Enable the RS232 Line Drivers in the FPGA. */
	206	/* Also, power on the audio CODEC's amplifier here, */
	207	/* which will make a noise on the audio output. */
	208	/* This is done here instead of in the kernel so there */
	209	/* isn't a loud popping noise at the start of each */
	210	/* song. */
	211	/* Also, disable the CODEC's clocks. */
	212	/* omap1510-HelenP1 [specific] */
	213
945af8d7 WD	214	ldr r0, REG_FPGA_POWER
	215	mov r1, #0
	216	ldr r2, REG_FPGA_DIP_SWITCH
	217	ldrb r3, [r2]
	218	cmp r3, #0x8
	219	movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */
	220	strb r1, [r0]
	221	ldr r0, REG_FPGA_AUDIO
	222	mov r1, #0x0 /* Disable sound driver (CODEC clocks) */
	223	strb r1, [r0]
2e5983d2	224
945af8d7	225	/* back to arch calling code */
2e5983d2 WD	226	mov pc, lr
	227
	228	/* the literal pools origin */
945af8d7	229	.ltorg
2e5983d2 WD	230
	231	/* OMAP configuration registers */
	232	REG_FUNC_MUX_CTRL_0: /* 32 bits */
	233	.word 0xfffe1000
	234	REG_FUNC_MUX_CTRL_1: /* 32 bits */
	235	.word 0xfffe1004
	236	REG_FUNC_MUX_CTRL_2: /* 32 bits */
	237	.word 0xfffe1008
	238	REG_COMP_MODE_CTRL_0: /* 32 bits */
	239	.word 0xfffe100c
	240	REG_FUNC_MUX_CTRL_3: /* 32 bits */
	241	.word 0xfffe1010
	242	REG_FUNC_MUX_CTRL_4: /* 32 bits */
	243	.word 0xfffe1014
	244	REG_FUNC_MUX_CTRL_5: /* 32 bits */
	245	.word 0xfffe1018
	246	REG_FUNC_MUX_CTRL_6: /* 32 bits */
	247	.word 0xfffe101c
	248	REG_FUNC_MUX_CTRL_7: /* 32 bits */
	249	.word 0xfffe1020
	250	REG_FUNC_MUX_CTRL_8: /* 32 bits */
	251	.word 0xfffe1024
	252	REG_FUNC_MUX_CTRL_9: /* 32 bits */
	253	.word 0xfffe1028
	254	REG_FUNC_MUX_CTRL_A: /* 32 bits */
	255	.word 0xfffe102C
	256	REG_FUNC_MUX_CTRL_B: /* 32 bits */
	257	.word 0xfffe1030
	258	REG_FUNC_MUX_CTRL_C: /* 32 bits */
	259	.word 0xfffe1034
	260	REG_FUNC_MUX_CTRL_D: /* 32 bits */
	261	.word 0xfffe1038
	262	REG_PULL_DWN_CTRL_0: /* 32 bits */
	263	.word 0xfffe1040
	264	REG_PULL_DWN_CTRL_1: /* 32 bits */
	265	.word 0xfffe1044
	266	REG_PULL_DWN_CTRL_2: /* 32 bits */
	267	.word 0xfffe1048
	268	REG_PULL_DWN_CTRL_3: /* 32 bits */
	269	.word 0xfffe104c
	270	REG_VOLTAGE_CTRL_0: /* 32 bits */
	271	.word 0xfffe1060
	272	REG_TEST_DBG_CTRL_0: /* 32 bits */
	273	.word 0xfffe1070
	274	REG_MOD_CONF_CTRL_0: /* 32 bits */
	275	.word 0xfffe1080
	276	REG_TC_IMIF_PRIO: /* 32 bits */
	277	.word 0xfffecc00
	278	REG_TC_EMIFS_PRIO: /* 32 bits */
	279	.word 0xfffecc04
	280	REG_TC_EMIFF_PRIO: /* 32 bits */
	281	.word 0xfffecc08
	282	REG_TC_EMIFS_CONFIG: /* 32 bits */
	283	.word 0xfffecc0c
	284	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
945af8d7	285	.word 0xfffecc10
2e5983d2	286	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
945af8d7	287	.word 0xfffecc14
2e5983d2	288	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
945af8d7	289	.word 0xfffecc18
2e5983d2	290	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
945af8d7	291	.word 0xfffecc1c
2e5983d2 WD	292	REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
	293	.word 0xfffecc20
	294	REG_TC_EMIFF_MRS: /* 32 bits */
	295	.word 0xfffecc24
	296	/* MPU clock/reset/power mode control registers */
	297	REG_ARM_CKCTL: /* 16 bits */
	298	.word 0xfffece00
	299	REG_ARM_IDLECT2: /* 16 bits */
945af8d7	300	.word 0xfffece08
2e5983d2	301	REG_ARM_RSTCT2: /* 16 bits */
945af8d7	302	.word 0xfffece14
2e5983d2	303	REG_ARM_SYSST: /* 16 bits */
945af8d7	304	.word 0xfffece18
2e5983d2 WD	305	/* DPLL control registers */
	306	REG_DPLL1_CTL: /* 16 bits */
	307	.word 0xfffecf00
	308	/* identification code register */
	309	REG_IDCODE: /* 32 bits */
945af8d7	310	.word 0xfffed404
2e5983d2 WD	311
	312	/* Innovator specific */
	313	REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
945af8d7	314	.word 0x08000003
2e5983d2	315	REG_FPGA_POWER: /* 8 bits */
945af8d7	316	.word 0x08000005
2e5983d2 WD	317	REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
	318	.word 0x0800000c
	319	REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
945af8d7	320	.word 0x0800000e
2e5983d2 WD	321
	322	VAL_COMP_MODE_CTRL_0:
	323	.word 0x0000eaef
	324	VAL_FUNC_MUX_CTRL_4:
	325	.word 0x00000000
	326	VAL_FUNC_MUX_CTRL_5:
	327	.word 0x00000000
	328	VAL_FUNC_MUX_CTRL_6:
	329	.word 0x00000001
	330	VAL_FUNC_MUX_CTRL_7:
	331	.word 0x00000000
	332	VAL_FUNC_MUX_CTRL_8:
	333	.word 0x10001200
	334	VAL_FUNC_MUX_CTRL_9:
	335	.word 0x01201012
	336	VAL_FUNC_MUX_CTRL_A:
	337	.word 0x00000248
	338	VAL_FUNC_MUX_CTRL_B:
	339	.word 0x00000248
	340	VAL_FUNC_MUX_CTRL_C:
	341	.word 0x09000000
	342	VAL_FUNC_MUX_CTRL_D:
	343	.word 0x00000000
	344	VAL_PULL_DWN_CTRL_0:
	345	.word 0x11a10000
	346	VAL_PULL_DWN_CTRL_1:
	347	.word 0x2e047fff
	348	VAL_PULL_DWN_CTRL_2:
6f21347d	349	.word 0xffd603a6
2e5983d2	350	VAL_PULL_DWN_CTRL_3:
6f21347d	351	.word 0x00003e03
2e5983d2 WD	352	VAL_VOLTAGE_CTRL_0:
	353	.word 0x00000007
	354	VAL_TEST_DBG_CTRL_0:
	355	/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
945af8d7 WD	356	* This slows down internal SRAM accesses.
945af8d7 WD	357	*/
2e5983d2 WD	358	.word 0x00000007
	359	VAL_MOD_CONF_CTRL_0:
	360	.word 0x0b000008
	361	VAL_ARM_CKCTL:
	362	.word 0x010f
	363	VAL_DPLL1_CTL:
	364	.word 0x2710
	365	VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
	366	.word 0x00001149
	367	VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
	368	.word 0x00004158
	369	VAL_TC_EMIFS_CS0_CONFIG:
	370	.word 0x002130b0
	371	VAL_TC_EMIFS_CS1_CONFIG:
	372	.word 0x0000f559
	373	VAL_TC_EMIFS_CS2_CONFIG:
	374	.word 0x000055f0
	375	VAL_TC_EMIFS_CS3_CONFIG:
	376	.word 0x00003331
	377	VAL_TC_EMIFF_SDRAM_CONFIG:
	378	.word 0x010290fc
	379	VAL_TC_EMIFF_MRS:
	380	.word 0x00000027