[people/ms/u-boot.git] / board / ti / omap2420h4 / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>

_TEXT_BASE:
	.word	TEXT_BASE	/* sdram load addr from config.mk */

/**************************************************************************
 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
 * R1 = SRAM destination address.
 *************************************************************************/
.global cpy_clk_code
 cpy_clk_code:
	/* Copy DPLL code into SRAM */
	adr	r0, go_to_speed		/* get addr of clock setting code */
	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
	mov	r1, r1			/* r1 <- dest address (passed in) */
	add	r2, r2, r0		/* r2 <- source end address */
next2:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	bne	next2
	mov	pc, lr			/* back to caller */

/* ****************************************************************************
 *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
 *		 -executed from SRAM.
 *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
 *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
 *  R2 = dpll value
 *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
 ******************************************************************************/
.global go_to_speed
 go_to_speed:
	sub	sp, sp, #0x4 /* get some stack space */
	str	r4, [sp]     /* save r4's value */

	/* move into fast relock bypass */
	ldr	r8, pll_ctl_add
	mov	r4, #0x2
	str	r4, [r8]
	ldr	r4, pll_stat
block:
	ldr	r8, [r4]	/* wait for bypass to take effect */
	and	r8, r8, #0x3
	cmp	r8, #0x1
	bne	block

	/* set new dpll dividers _after_ in bypass */
	ldr	r4, pll_div_add
	ldr	r8, pll_div_val
	str	r8, [r4]

	/* now prepare GPMC (flash) for new dpll speed */
	/* flash needs to be stable when we jump back to it */
	ldr	r4, cfg3_0_addr
	ldr	r8, cfg3_0_val
	str	r8, [r4]
	ldr	r4, cfg4_0_addr
	ldr	r8, cfg4_0_val
	str	r8, [r4]
	ldr	r4, cfg1_0_addr
	ldr	r8, [r4]
	orr	r8, r8, #0x3	 /* up gpmc divider */
	str	r8, [r4]

	/* setup to 2x loop though code.  The first loop pre-loads the
	 * icache, the 2nd commits the prcm config, and locks the dpll
	 */
	mov	r4, #0x1000	 /* spin spin spin */
	mov	r8, #0x4	 /* first pass condition & set registers */
	cmp	r8, #0x4
2:
	ldrne	r8, [r3]	 /* DPLL lock check */
	and	r8, r8, #0x7
	cmp	r8, #0x2
	beq	4f
3:
	subeq	r8, r8, #0x1
	streq	r8, [r0]	 /* commit dividers (2nd time) */
	nop
lloop1:
	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
	nop
	cmp	r4, #0x0
	bne	lloop1
	mov	r4, #0x40000
	cmp	r8, #0x1
	nop
	streq	r2, [r1]	/* lock dpll (2nd time) */
	nop
lloop2:
	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
	nop
	cmp	r4, #0x0
	bne	lloop2
	mov	r4, #0x40000
	cmp	r8, #0x1
	nop
	ldreq	r8, [r3]	 /* get lock condition for dpll */
	cmp	r8, #0x4	 /* first time though? */
	bne	2b
	moveq	r8, #0x2	 /* set to dpll check condition. */
	beq	3b		 /* if condition not true branch */
4:
	ldr	r4, [sp]
	add	sp, sp, #0x4	 /* return stack space */
	mov	pc, lr		 /* back to caller, locked */

_go_to_speed: .word go_to_speed

/* these constants need to be close for PIC code */
cfg3_0_addr:
    .word  GPMC_CONFIG3_0
cfg3_0_val:
    .word  H4_24XX_GPMC_CONFIG3_0
cfg4_0_addr:
    .word  GPMC_CONFIG4_0
cfg4_0_val:
    .word  H4_24XX_GPMC_CONFIG4_0
cfg1_0_addr:
    .word  GPMC_CONFIG1_0
pll_ctl_add:
    .word CM_CLKEN_PLL
pll_stat:
    .word CM_IDLEST_CKGEN
pll_div_add:
    .word CM_CLKSEL1_PLL
pll_div_val:
    .word DPLL_VAL	/* DPLL setting (300MHz default) */

.globl lowlevel_init
lowlevel_init:
	ldr	sp,	SRAM_STACK
	str	ip,	[sp]	/* stash old link register */
	mov	ip,	lr	/* save link reg across call */
	bl	s_init		/* go setup pll,mux,memory */
	ldr	ip,	[sp]	/* restore save ip */
	mov	lr,	ip	/* restore link reg */

	/* map interrupt controller */
	ldr	r0,	VAL_INTH_SETUP
	mcr	p15, 0, r0, c15, c2, 4

	/* back to arch calling code */
	mov	pc,	lr

	/* the literal pools origin */
	.ltorg

REG_CONTROL_STATUS:
	.word CONTROL_STATUS
VAL_INTH_SETUP:
	.word PERIFERAL_PORT_BASE
SRAM_STACK:
	.word LOW_LEVEL_SRAM_STACK
Commit	Line	Data
8ed96046 WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2004
	5	* Texas Instruments, <www.ti.com>
	6	* Richard Woodruff <r-woodruff2@ti.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
082acfd4	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8ed96046 WD	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <config.h>
	28	#include <version.h>
	29	#include <asm/arch/omap2420.h>
	30	#include <asm/arch/mem.h>
	31	#include <asm/arch/clocks.h>
	32
	33	_TEXT_BASE:
	34	.word TEXT_BASE /* sdram load addr from config.mk */
	35
8ed96046 WD	36	/**************************************************************************
	37	* cpy_clk_code: relocates clock code into SRAM where its safer to execute
	38	* R1 = SRAM destination address.
	39	*************************************************************************/
	40	.global cpy_clk_code
	41	cpy_clk_code:
082acfd4 WD	42	/* Copy DPLL code into SRAM */
	43	adr r0, go_to_speed /* get addr of clock setting code */
	44	mov r2, #384 /* r2 size to copy (div by 32 bytes) */
	45	mov r1, r1 /* r1 <- dest address (passed in) */
	46	add r2, r2, r0 /* r2 <- source end address */
8ed96046	47	next2:
082acfd4 WD	48	ldmia r0!, {r3-r10} /* copy from source address [r0] */
	49	stmia r1!, {r3-r10} /* copy to target address [r1] */
	50	cmp r0, r2 /* until source end address [r2] */
	51	bne next2
	52	mov pc, lr /* back to caller */
8ed96046	53
082acfd4	54	/* ****************************************************************************
8ed96046	55	* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
082acfd4	56	* -executed from SRAM.
8ed96046 WD	57	* R0 = PRCM_CLKCFG_CTRL - addr of valid reg
	58	* R1 = CM_CLKEN_PLL - addr dpll ctlr reg
	59	* R2 = dpll value
	60	* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
082acfd4	61	******************************************************************************/
8ed96046 WD	62	.global go_to_speed
8ed96046 WD	63	go_to_speed:
082acfd4 WD	64	sub sp, sp, #0x4 /* get some stack space */
	65	str r4, [sp] /* save r4's value */
	66
	67	/* move into fast relock bypass */
	68	ldr r8, pll_ctl_add
	69	mov r4, #0x2
	70	str r4, [r8]
	71	ldr r4, pll_stat
8ed96046	72	block:
082acfd4 WD	73	ldr r8, [r4] /* wait for bypass to take effect */
	74	and r8, r8, #0x3
	75	cmp r8, #0x1
	76	bne block
8ed96046 WD	77
8ed96046 WD	78	/* set new dpll dividers _after_ in bypass */
082acfd4 WD	79	ldr r4, pll_div_add
	80	ldr r8, pll_div_val
	81	str r8, [r4]
	82
	83	/* now prepare GPMC (flash) for new dpll speed */
8ed96046	84	/* flash needs to be stable when we jump back to it */
082acfd4 WD	85	ldr r4, cfg3_0_addr
	86	ldr r8, cfg3_0_val
	87	str r8, [r4]
	88	ldr r4, cfg4_0_addr
	89	ldr r8, cfg4_0_val
	90	str r8, [r4]
	91	ldr r4, cfg1_0_addr
	92	ldr r8, [r4]
	93	orr r8, r8, #0x3 /* up gpmc divider */
	94	str r8, [r4]
	95
	96	/* setup to 2x loop though code. The first loop pre-loads the
	97	* icache, the 2nd commits the prcm config, and locks the dpll
	98	*/
	99	mov r4, #0x1000 /* spin spin spin */
	100	mov r8, #0x4 /* first pass condition & set registers */
	101	cmp r8, #0x4
8ed96046	102	2:
082acfd4 WD	103	ldrne r8, [r3] /* DPLL lock check */
	104	and r8, r8, #0x7
	105	cmp r8, #0x2
	106	beq 4f
8ed96046	107	3:
082acfd4 WD	108	subeq r8, r8, #0x1
	109	streq r8, [r0] /* commit dividers (2nd time) */
	110	nop
8ed96046	111	lloop1:
082acfd4 WD	112	sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
	113	nop
	114	cmp r4, #0x0
	115	bne lloop1
	116	mov r4, #0x40000
	117	cmp r8, #0x1
	118	nop
	119	streq r2, [r1] /* lock dpll (2nd time) */
	120	nop
8ed96046	121	lloop2:
082acfd4 WD	122	sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
	123	nop
	124	cmp r4, #0x0
	125	bne lloop2
	126	mov r4, #0x40000
	127	cmp r8, #0x1
	128	nop
	129	ldreq r8, [r3] /* get lock condition for dpll */
	130	cmp r8, #0x4 /* first time though? */
	131	bne 2b
	132	moveq r8, #0x2 /* set to dpll check condition. */
	133	beq 3b /* if condition not true branch */
	134	4:
	135	ldr r4, [sp]
	136	add sp, sp, #0x4 /* return stack space */
	137	mov pc, lr /* back to caller, locked */
8ed96046 WD	138
	139	_go_to_speed: .word go_to_speed
	140
	141	/* these constants need to be close for PIC code */
	142	cfg3_0_addr:
	143	.word GPMC_CONFIG3_0
082acfd4	144	cfg3_0_val:
8ed96046 WD	145	.word H4_24XX_GPMC_CONFIG3_0
	146	cfg4_0_addr:
	147	.word GPMC_CONFIG4_0
	148	cfg4_0_val:
	149	.word H4_24XX_GPMC_CONFIG4_0
	150	cfg1_0_addr:
	151	.word GPMC_CONFIG1_0
	152	pll_ctl_add:
	153	.word CM_CLKEN_PLL
	154	pll_stat:
	155	.word CM_IDLEST_CKGEN
	156	pll_div_add:
082acfd4	157	.word CM_CLKSEL1_PLL
8ed96046 WD	158	pll_div_val:
8ed96046 WD	159	.word DPLL_VAL /* DPLL setting (300MHz default) */
8ed96046	160
87cb6862 WD	161	.globl lowlevel_init
87cb6862 WD	162	lowlevel_init:
8ed96046	163	ldr sp, SRAM_STACK
082acfd4	164	str ip, [sp] /* stash old link register */
8ed96046	165	mov ip, lr /* save link reg across call */
082acfd4 WD	166	bl s_init /* go setup pll,mux,memory */
082acfd4 WD	167	ldr ip, [sp] /* restore save ip */
8ed96046	168	mov lr, ip /* restore link reg */
289f932c	169
8ed96046 WD	170	/* map interrupt controller */
	171	ldr r0, VAL_INTH_SETUP
	172	mcr p15, 0, r0, c15, c2, 4
	173
	174	/* back to arch calling code */
	175	mov pc, lr
	176
	177	/* the literal pools origin */
	178	.ltorg
	179
	180	REG_CONTROL_STATUS:
	181	.word CONTROL_STATUS
	182	VAL_INTH_SETUP:
	183	.word PERIFERAL_PORT_BASE
	184	SRAM_STACK:
	185	.word LOW_LEVEL_SRAM_STACK