projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e63e5904 TR |
1 | /* |
| 2 | * (C) Copyright 2004-2009 | |
| 3 | * Texas Instruments Incorporated | |
| 4 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| e63e5904 TR |
7 | */ |
| 8 | #ifndef _BOARD_SDP_H_ | |
| 9 | #define _BOARD_SDP_H_ | |
| 10 | ||
| 11 | #define OFF_IN_PD 0 | |
| 12 | #define OFF_OUT_PD 0 | |
| 13 | ||
| 14 | /* | |
| 15 | * IEN - Input Enable | |
| 16 | * IDIS - Input Disable | |
| 17 | * PTD - Pull type Down | |
| 18 | * PTU - Pull type Up | |
| 19 | * DIS - Pull type selection is inactive | |
| 20 | * EN - Pull type selection is active | |
| 21 | * M0 - Mode 0 | |
| 22 | * The commented string gives the final mux configuration for that pin | |
| 23 | */ | |
| 24 | #define MUX_SDP3430()\ | |
| 25 | /*SDRC*/\ | |
| 26 | MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ | |
| 27 | MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ | |
| 28 | MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ | |
| 29 | MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ | |
| 30 | MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ | |
| 31 | MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ | |
| 32 | MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ | |
| 33 | MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ | |
| 34 | MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ | |
| 35 | MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ | |
| 36 | MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ | |
| 37 | MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ | |
| 38 | MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ | |
| 39 | MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ | |
| 40 | MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ | |
| 41 | MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ | |
| 42 | MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ | |
| 43 | MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ | |
| 44 | MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ | |
| 45 | MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ | |
| 46 | MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ | |
| 47 | MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ | |
| 48 | MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ | |
| 49 | MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ | |
| 50 | MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ | |
| 51 | MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ | |
| 52 | MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ | |
| 53 | MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ | |
| 54 | MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ | |
| 55 | MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ | |
| 56 | MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ | |
| 57 | MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ | |
| 58 | MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ | |
| 59 | MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ | |
| 60 | MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ | |
| 61 | MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ | |
| 62 | MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ | |
| 63 | /*GPMC*/\ | |
| 64 | MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 65 | MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 66 | MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 67 | MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 68 | MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 69 | MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 70 | MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 71 | MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 72 | MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 73 | MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 74 | MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 75 | MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 76 | MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 77 | MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 78 | MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 79 | MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 80 | MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 81 | MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 82 | MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 83 | MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 84 | MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 85 | MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 86 | MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 87 | MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 88 | MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 89 | MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 90 | MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 91 | MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 92 | MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 93 | MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 94 | MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\ | |
| 95 | MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\ | |
| 96 | MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\ | |
| 97 | MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\ | |
| 98 | MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 99 | MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 100 | MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 101 | MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 102 | MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 103 | MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\ | |
| 104 | MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 105 | MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 106 | MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 107 | MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ | |
| 108 | MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ | |
| 109 | /*DSS*/\ | |
| 110 | MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 111 | MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 112 | MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 113 | MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 114 | MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 115 | MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 116 | MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 117 | MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 118 | MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 119 | MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 120 | MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 121 | MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 122 | MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 123 | MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 124 | MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 125 | MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 126 | MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 127 | MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 128 | MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 129 | MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 130 | MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 131 | MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 132 | MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 133 | MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 134 | MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 135 | MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 136 | MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 137 | MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 138 | /*CAMERA*/\ | |
| 139 | MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 140 | MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 141 | MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 142 | MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 143 | MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\ | |
| 144 | MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ | |
| 145 | MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ | |
| 146 | MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 147 | MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 148 | MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 149 | MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 150 | MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 151 | MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 152 | MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 153 | MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 154 | MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 155 | MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 156 | MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 157 | MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ | |
| 158 | MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 159 | MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 160 | MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 161 | MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 162 | MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 163 | /*Audio InterfACe */\ | |
| 164 | MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 165 | MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 166 | MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 167 | MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 168 | /*Expansion Card */\ | |
| 169 | MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 170 | MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 171 | MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 172 | MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 173 | MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 174 | MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 175 | MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 176 | MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 177 | MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 178 | MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 179 | /*Wireless LAN */\ | |
| 180 | MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 181 | MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 182 | MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 183 | MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 184 | MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 185 | MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 186 | MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\ | |
| 187 | MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\ | |
| 188 | MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\ | |
| 189 | MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\ | |
| 190 | /*Bluetooth*/\ | |
| 191 | MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 192 | MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 193 | MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 194 | MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 195 | MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 196 | MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 197 | MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 198 | MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 199 | /*Modem Interface */\ | |
| 200 | MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 201 | MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 202 | MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ | |
| 203 | MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 204 | MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\ | |
| 205 | MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\ | |
| 206 | MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\ | |
| 207 | MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\ | |
| 208 | MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 209 | MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\ | |
| 210 | MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 211 | MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 212 | MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ | |
| 213 | MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 214 | MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 215 | /*Serial Interface*/\ | |
| 216 | MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 217 | MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 218 | MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 219 | MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 220 | MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 221 | MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 222 | MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 223 | MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 224 | MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 225 | MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 226 | MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 227 | MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 228 | MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 229 | MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 230 | MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 231 | MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 232 | /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\ | |
| 233 | MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ | |
| 234 | MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ | |
| 235 | MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ | |
| 236 | MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ | |
| 237 | MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ | |
| 238 | MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ | |
| 239 | MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\ | |
| 240 | MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\ | |
| 241 | MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 242 | MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 243 | MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 244 | MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 245 | MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 246 | MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\ | |
| 247 | MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\ | |
| 248 | MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 249 | MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 250 | MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 251 | MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 252 | MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 253 | MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 254 | /*Control and debug */\ | |
| 255 | MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ | |
| 256 | MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\ | |
| 257 | MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 258 | MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\ | |
| 259 | MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\ | |
| 260 | MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\ | |
| 261 | MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\ | |
| 262 | MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\ | |
| 263 | MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\ | |
| 264 | MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\ | |
| 265 | MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ | |
| 266 | MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ | |
| 267 | MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ | |
| 268 | MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ | |
| 269 | MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ | |
| 270 | MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ | |
| 271 | MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ | |
| 272 | MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 273 | MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 274 | MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ | |
| 275 | MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ | |
| 276 | MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\ | |
| 277 | MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\ | |
| 278 | MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\ | |
| 279 | MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\ | |
| 280 | MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 281 | MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 282 | MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 283 | MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 284 | MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 285 | MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 286 | MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 287 | MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 288 | MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 289 | MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 290 | MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 291 | MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 292 | /*Die to Die */\ | |
| 293 | MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 294 | MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 295 | MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 296 | MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 297 | MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 298 | MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 299 | MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 300 | MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 301 | MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 302 | MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 303 | MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 304 | MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 305 | MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 306 | MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 307 | MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 308 | MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 309 | MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 310 | MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 311 | MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 312 | MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 313 | MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 314 | MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 315 | MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 316 | MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 317 | MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 318 | MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 319 | MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 320 | MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 321 | MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 322 | MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 323 | MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 324 | MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 325 | MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 326 | MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 327 | MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 328 | MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 329 | MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 330 | MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 331 | MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\ | |
| 332 | MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 333 | MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 334 | MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 335 | MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 336 | MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ | |
| 337 | MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 338 | MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 339 | MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 340 | MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 341 | MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 342 | MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 343 | MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 344 | MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 345 | MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 346 | MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 347 | MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 348 | MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ | |
| 349 | MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 350 | MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\ | |
| 351 | MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 352 | MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 353 | MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 354 | MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 355 | MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\ | |
| 356 | MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ | |
| 357 | MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\ | |
| 358 | MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/ | |
| 359 | ||
| 360 | /* | |
| 361 | * GPMC Timing definitions for SDP3430 | |
| 362 | * at L3 = 166Mhz | |
| 363 | */ | |
| 364 | ||
| 365 | /* Timing definitions for GPMC controller for Sibley NOR */ | |
| 366 | #define SDP3430_NOR_GPMC_CONF1 0x00001200 | |
| 367 | #define SDP3430_NOR_GPMC_CONF2 0x001F1F00 | |
| 368 | #define SDP3430_NOR_GPMC_CONF3 0x00080802 | |
| 369 | #define SDP3430_NOR_GPMC_CONF4 0x1C091C09 | |
| 370 | #define SDP3430_NOR_GPMC_CONF5 0x01131F1F | |
| 371 | #define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2 | |
| 372 | ||
| 373 | /* | |
| 374 | * Timing definitions for GPMC controller for Debug Board | |
| 375 | * Debug board contains access to ethernet and DIP Switch setting | |
| 376 | * information etc. | |
| 377 | */ | |
| 378 | #define SDP3430_DEBUG_GPMC_CONF1 0x00611200 | |
| 379 | #define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01 | |
| 380 | #define SDP3430_DEBUG_GPMC_CONF3 0x00080803 | |
| 381 | #define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09 | |
| 382 | #define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F | |
| 383 | #define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4 | |
| 384 | ||
| 385 | /* Timing defintions for GPMC OneNAND */ | |
| 386 | #define SDP3430_ONENAND_GPMC_CONF1 0x00001200 | |
| 387 | #define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01 | |
| 388 | #define SDP3430_ONENAND_GPMC_CONF3 0x00030301 | |
| 389 | #define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04 | |
| 390 | #define SDP3430_ONENAND_GPMC_CONF5 0x010F1010 | |
| 391 | #define SDP3430_ONENAND_GPMC_CONF6 0x1F060000 | |
| 392 | ||
| 393 | /* GPMC definitions for GPMC NAND */ | |
| 394 | #define SDP3430_NAND_GPMC_CONF1 0x00000800 | |
| 395 | #define SDP3430_NAND_GPMC_CONF2 0x00141400 | |
| 396 | #define SDP3430_NAND_GPMC_CONF3 0x00141400 | |
| 397 | #define SDP3430_NAND_GPMC_CONF4 0x0F010F01 | |
| 398 | #define SDP3430_NAND_GPMC_CONF5 0x010C1414 | |
| 399 | #define SDP3430_NAND_GPMC_CONF6 0x1F040A80 | |
| 400 | ||
| 401 | #endif /* _BOARD_SDP_H_ */ |