[people/ms/u-boot.git] / board / toradex / colibri_t20 / colibri_t20.c

/*
 *  Copyright (C) 2012 Lucas Stach
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/tegra.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <i2c.h>
#include <nand.h>
#include "../common/tdx-common.h"

DECLARE_GLOBAL_DATA_PTR;

#define PMU_I2C_ADDRESS		0x34
#define MAX_I2C_RETRY		3
#define PMU_SUPPLYENE		0x14
#define PMU_SUPPLYENE_SYSINEN	(1<<5)
#define PMU_SUPPLYENE_EXITSLREQ	(1<<1)

int arch_misc_init(void)
{
	/* Disable PMIC sleep mode on low supply voltage */
	struct udevice *dev;
	u8 addr, data[1];
	int err;

	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
	if (err) {
		debug("%s: Cannot find PMIC I2C chip\n", __func__);
		return err;
	}

	addr = PMU_SUPPLYENE;

	err = dm_i2c_read(dev, addr, data, 1);
	if (err) {
		debug("failed to get PMU_SUPPLYENE\n");
		return err;
	}

	data[0] &= ~PMU_SUPPLYENE_SYSINEN;
	data[0] |= PMU_SUPPLYENE_EXITSLREQ;

	err = dm_i2c_write(dev, addr, data, 1);
	if (err) {
		debug("failed to set PMU_SUPPLYENE\n");
		return err;
	}

	/* make sure SODIMM pin 87 nRESET_OUT is released properly */
	pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);

	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
	    NVBOOTTYPE_RECOVERY)
		printf("USB recovery mode\n");

	return 0;
}

int checkboard(void)
{
	printf("Model: Toradex Colibri T20 %dMB V%s\n",
	       (gd->ram_size == 0x10000000) ? 256 : 512,
	       (nand_info[0]->erasesize >> 10 == 512) ?
	       ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	return ft_common_board_setup(blob, bd);
}
#endif

#ifdef CONFIG_TEGRA_MMC
/*
 * Routine: pin_mux_mmc
 * Description: setup the pin muxes/tristate values for the SDMMC(s)
 */
void pin_mux_mmc(void)
{
	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
	pinmux_tristate_disable(PMUX_PINGRP_GMB);
}
#endif

#ifdef CONFIG_TEGRA_NAND
void pin_mux_nand(void)
{
	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);

	/*
	 * configure pingroup ATC to something unrelated to
	 * avoid ATC overriding KBC
	 */
	pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
}
#endif

#ifdef CONFIG_USB_EHCI_TEGRA
void pin_mux_usb(void)
{
	/* module internal USB bus to connect ethernet chipset */
	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);

	/* ULPI reference clock output */
	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);

	/* PHY reset GPIO */
	pinmux_tristate_disable(PMUX_PINGRP_UAC);

	/* VBus GPIO */
	pinmux_tristate_disable(PMUX_PINGRP_DTE);

	/* Reset ASIX using LAN_RESET */
	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
	pinmux_tristate_disable(PMUX_PINGRP_GPV);
	udelay(5);
	gpio_set_value(TEGRA_GPIO(V, 4), 1);

	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif

#ifdef CONFIG_VIDEO_TEGRA20
/*
 * Routine: pin_mux_display
 * Description: setup the pin muxes/tristate values for the LCD interface)
 */
void pin_mux_display(void)
{
	/*
	 * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
	 * device-tree
	 */
	pinmux_tristate_disable(PMUX_PINGRP_DTA);

	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
	pinmux_tristate_disable(PMUX_PINGRP_SDC);
}
#endif
Commit	Line	Data
6bbda883 LS	1	/*
	2	* Copyright (C) 2012 Lucas Stach
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
6bbda883 LS	5	*/
	6
	7	#include <common.h>
6bbda883 LS	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/funcmux.h>
	10	#include <asm/arch/pinmux.h>
a5825625	11	#include <asm/arch-tegra/ap.h>
6bbda883	12	#include <asm/arch-tegra/board.h>
a5825625	13	#include <asm/arch-tegra/tegra.h>
d1db97aa	14	#include <asm/gpio.h>
a5825625	15	#include <asm/io.h>
10ef82d3	16	#include <i2c.h>
b891d010	17	#include <nand.h>
37fa4125	18	#include "../common/tdx-common.h"
b891d010 MZ	19
b891d010 MZ	20	DECLARE_GLOBAL_DATA_PTR;
10ef82d3 MZ	21
	22	#define PMU_I2C_ADDRESS 0x34
	23	#define MAX_I2C_RETRY 3
	24	#define PMU_SUPPLYENE 0x14
	25	#define PMU_SUPPLYENE_SYSINEN (1<<5)
	26	#define PMU_SUPPLYENE_EXITSLREQ (1<<1)
a5825625 MZ	27
	28	int arch_misc_init(void)
	29	{
10ef82d3 MZ	30	/* Disable PMIC sleep mode on low supply voltage */
	31	struct udevice *dev;
	32	u8 addr, data[1];
	33	int err;
	34
	35	err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
	36	if (err) {
	37	debug("%s: Cannot find PMIC I2C chip\n", __func__);
	38	return err;
	39	}
	40
	41	addr = PMU_SUPPLYENE;
	42
	43	err = dm_i2c_read(dev, addr, data, 1);
	44	if (err) {
	45	debug("failed to get PMU_SUPPLYENE\n");
	46	return err;
	47	}
	48
	49	data[0] &= ~PMU_SUPPLYENE_SYSINEN;
	50	data[0] \|= PMU_SUPPLYENE_EXITSLREQ;
	51
	52	err = dm_i2c_write(dev, addr, data, 1);
	53	if (err) {
	54	debug("failed to set PMU_SUPPLYENE\n");
	55	return err;
	56	}
	57
b7b20670 MZ	58	/* make sure SODIMM pin 87 nRESET_OUT is released properly */
	59	pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
	60
a5825625 MZ	61	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
	62	NVBOOTTYPE_RECOVERY)
	63	printf("USB recovery mode\n");
	64
	65	return 0;
	66	}
6bbda883	67
b891d010 MZ	68	int checkboard(void)
	69	{
	70	printf("Model: Toradex Colibri T20 %dMB V%s\n",
	71	(gd->ram_size == 0x10000000) ? 256 : 512,
	72	(nand_info[0]->erasesize >> 10 == 512) ?
	73	((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
	74
	75	return 0;
	76	}
	77
37fa4125 SA	78	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	79	int ft_board_setup(void blob, bd_t bd)
	80	{
	81	return ft_common_board_setup(blob, bd);
	82	}
	83	#endif
	84
6bbda883	85	#ifdef CONFIG_TEGRA_MMC
c9aa831e TW	86	/*
	87	* Routine: pin_mux_mmc
	88	* Description: setup the pin muxes/tristate values for the SDMMC(s)
	89	*/
	90	void pin_mux_mmc(void)
6bbda883 LS	91	{
6bbda883 LS	92	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
70ad375e	93	pinmux_tristate_disable(PMUX_PINGRP_GMB);
6bbda883 LS	94	}
6bbda883 LS	95	#endif
d1db97aa MZ	96
	97	#ifdef CONFIG_TEGRA_NAND
	98	void pin_mux_nand(void)
	99	{
	100	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
76a30fed MZ	101
	102	/*
	103	* configure pingroup ATC to something unrelated to
	104	* avoid ATC overriding KBC
	105	*/
	106	pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
d1db97aa MZ	107	}
	108	#endif
	109
	110	#ifdef CONFIG_USB_EHCI_TEGRA
	111	void pin_mux_usb(void)
	112	{
	113	/* module internal USB bus to connect ethernet chipset */
	114	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
	115
	116	/* ULPI reference clock output */
	117	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
	118	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
	119
	120	/* PHY reset GPIO */
	121	pinmux_tristate_disable(PMUX_PINGRP_UAC);
	122
	123	/* VBus GPIO */
	124	pinmux_tristate_disable(PMUX_PINGRP_DTE);
	125
00a5270b	126	/* Reset ASIX using LAN_RESET */
01a97a11 SW	127	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
01a97a11 SW	128	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
00a5270b MZ	129	pinmux_tristate_disable(PMUX_PINGRP_GPV);
00a5270b MZ	130	udelay(5);
01a97a11	131	gpio_set_value(TEGRA_GPIO(V, 4), 1);
00a5270b MZ	132
00a5270b MZ	133	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
d1db97aa MZ	134	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
	135	}
	136	#endif
b2ea19b5	137
d2f90650	138	#ifdef CONFIG_VIDEO_TEGRA20
b2ea19b5 MZ	139	/*
	140	* Routine: pin_mux_display
	141	* Description: setup the pin muxes/tristate values for the LCD interface)
	142	*/
	143	void pin_mux_display(void)
	144	{
	145	/*
	146	* Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
	147	* device-tree
	148	*/
	149	pinmux_tristate_disable(PMUX_PINGRP_DTA);
	150
	151	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
	152	pinmux_tristate_disable(PMUX_PINGRP_SDC);
	153	}
	154	#endif