projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fa230445 HS |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 9c0f42ec | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| fa230445 HS |
16 | * GNU General Public License for more details. |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <common.h> | |
| 25 | #include <ioports.h> | |
| 26 | #include <mpc8260.h> | |
| 27 | ||
| 28 | #include <command.h> | |
| 29 | #ifdef CONFIG_PCI | |
| 30 | #include <pci.h> | |
| 31 | #include <asm/m8260_pci.h> | |
| 32 | #endif | |
| fa230445 HS |
33 | |
| 34 | #if 0 | |
| 35 | #define deb_printf(fmt,arg...) \ | |
| 36 | printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) | |
| 37 | #else | |
| 38 | #define deb_printf(fmt,arg...) \ | |
| 9c0f42ec | 39 | do { } while (0) |
| fa230445 HS |
40 | #endif |
| 41 | ||
| 42 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
| 43 | unsigned long board_get_cpu_clk_f (void); | |
| 44 | #endif | |
| 45 | ||
| 46 | /* | |
| 47 | * I/O Port configuration table | |
| 48 | * | |
| 49 | * if conf is 1, then that port pin will be configured at boot time | |
| 50 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
| 51 | */ | |
| 52 | ||
| 53 | const iop_conf_t iop_conf_tab[4][32] = { | |
| 54 | ||
| 55 | /* Port A configuration */ | |
| 56 | { /* conf ppar psor pdir podr pdat */ | |
| 9c0f42ec WD |
57 | /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ |
| 58 | /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ | |
| 59 | /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ | |
| 60 | /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ | |
| 61 | /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ | |
| 62 | /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ | |
| 63 | /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ | |
| 64 | /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ | |
| 65 | /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ | |
| 66 | /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ | |
| 67 | /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ | |
| 68 | /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ | |
| 69 | /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ | |
| 70 | /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ | |
| 71 | /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ | |
| 72 | /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ | |
| 73 | /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ | |
| 74 | /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ | |
| 75 | /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ | |
| 76 | /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ | |
| 77 | /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ | |
| 78 | /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ | |
| 79 | /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ | |
| 80 | /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ | |
| 81 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ | |
| 82 | /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ | |
| 83 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ | |
| 84 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ | |
| 85 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ | |
| 86 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ | |
| 87 | /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ | |
| 88 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ | |
| fa230445 HS |
89 | }, |
| 90 | ||
| 91 | /* Port B configuration */ | |
| 9c0f42ec WD |
92 | { /* conf ppar psor pdir podr pdat */ |
| 93 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
| 94 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
| 95 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
| 96 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
| 97 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
| 98 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
| 99 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
| 100 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
| 101 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
| 102 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
| 103 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
| 104 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
| 105 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
| 106 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
| 107 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ | |
| 108 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ | |
| 109 | /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ | |
| 110 | /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ | |
| 111 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ | |
| 112 | /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ | |
| 113 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ | |
| 114 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ | |
| 115 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ | |
| 116 | /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ | |
| 117 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ | |
| 118 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ | |
| 119 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ | |
| 120 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ | |
| 121 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 122 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 123 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 124 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
| fa230445 HS |
125 | }, |
| 126 | ||
| 127 | /* Port C */ | |
| 9c0f42ec WD |
128 | { /* conf ppar psor pdir podr pdat */ |
| 129 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ | |
| 130 | /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ | |
| 131 | /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ | |
| 132 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ | |
| 133 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ | |
| 134 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ | |
| 135 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ | |
| 136 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ | |
| 137 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ | |
| 138 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ | |
| 139 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ | |
| 140 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ | |
| 141 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ | |
| 142 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ | |
| 143 | /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ | |
| 144 | /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ | |
| 145 | /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ | |
| 146 | /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ | |
| 147 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ | |
| 148 | /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ | |
| 149 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ | |
| 150 | /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ | |
| 151 | /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ | |
| 152 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ | |
| 153 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ | |
| 154 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ | |
| 155 | /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ | |
| 156 | /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ | |
| 157 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ | |
| 158 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ | |
| 159 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ | |
| 160 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ | |
| fa230445 HS |
161 | }, |
| 162 | ||
| 163 | /* Port D */ | |
| 9c0f42ec WD |
164 | { /* conf ppar psor pdir podr pdat */ |
| 165 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
| 166 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
| 167 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ | |
| 168 | /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ | |
| 169 | /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ | |
| 170 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ | |
| 171 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ | |
| 172 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ | |
| 173 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ | |
| 174 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ | |
| 175 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ | |
| 176 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ | |
| 177 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
| 178 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
| 179 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ | |
| 180 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ | |
| fa230445 | 181 | #if defined(CONFIG_SOFT_I2C) |
| 9c0f42ec WD |
182 | /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ |
| 183 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ | |
| fa230445 HS |
184 | #else |
| 185 | #if defined(CONFIG_HARD_I2C) | |
| 9c0f42ec WD |
186 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
| 187 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
| fa230445 | 188 | #else /* normal I/O port pins */ |
| 9c0f42ec WD |
189 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
| 190 | /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
| fa230445 HS |
191 | #endif |
| 192 | #endif | |
| 9c0f42ec WD |
193 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
| 194 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
| 195 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
| 196 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
| 197 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
| 198 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
| 199 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ | |
| 200 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ | |
| 201 | /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ | |
| 202 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ | |
| 203 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 204 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 205 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
| 206 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
| fa230445 HS |
207 | } |
| 208 | }; | |
| 209 | ||
| 9c0f42ec | 210 | #define _NOT_USED_ 0xFFFFFFFF |
| fa230445 HS |
211 | |
| 212 | /* UPM pattern for bus clock = 66.7 MHz */ | |
| 213 | static const uint upmTable67[] = | |
| 214 | { | |
| 9c0f42ec WD |
215 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ |
| 216 | /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, | |
| 217 | /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
| 218 | ||
| 219 | /* UPM Read Burst RAM array entry -> unused */ | |
| 220 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 221 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 222 | ||
| 223 | /* UPM Read Burst RAM array entry -> unused */ | |
| 224 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 225 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 226 | ||
| 227 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
| 228 | /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, | |
| 229 | /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
| 230 | ||
| 231 | /* UPM Write Burst RAM array entry -> unused */ | |
| 232 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 233 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 234 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 235 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 236 | ||
| 237 | /* UPM Refresh Timer RAM array entry -> unused */ | |
| 238 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 239 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 240 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 241 | ||
| 242 | /* UPM Exception RAM array entry -> unsused */ | |
| 243 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| fa230445 HS |
244 | }; |
| 245 | ||
| 246 | /* UPM pattern for bus clock = 100 MHz */ | |
| 247 | static const uint upmTable100[] = | |
| 248 | { | |
| 9c0f42ec WD |
249 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ |
| 250 | /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, | |
| 251 | /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
| 252 | ||
| 253 | /* UPM Read Burst RAM array entry -> unused */ | |
| 254 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 255 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 256 | ||
| 257 | /* UPM Read Burst RAM array entry -> unused */ | |
| 258 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 259 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 260 | ||
| 261 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
| 262 | /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, | |
| 263 | /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
| 264 | ||
| 265 | /* UPM Write Burst RAM array entry -> unused */ | |
| 266 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 267 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 268 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 269 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 270 | ||
| 271 | /* UPM Refresh Timer RAM array entry -> unused */ | |
| 272 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 273 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 274 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 275 | ||
| 276 | /* UPM Exception RAM array entry -> unsused */ | |
| 277 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| fa230445 HS |
278 | }; |
| 279 | ||
| 280 | /* UPM pattern for bus clock = 133.3 MHz */ | |
| 281 | static const uint upmTable133[] = | |
| 282 | { | |
| 9c0f42ec WD |
283 | /* Offset UPM Read Single RAM array entry -> NAND Read Data */ |
| 284 | /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, | |
| 285 | /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, | |
| 286 | ||
| 287 | /* UPM Read Burst RAM array entry -> unused */ | |
| 288 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 289 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 290 | ||
| 291 | /* UPM Read Burst RAM array entry -> unused */ | |
| 292 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 293 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 294 | ||
| 295 | /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ | |
| 296 | /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, | |
| 297 | /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, | |
| 298 | ||
| 299 | /* UPM Write Burst RAM array entry -> unused */ | |
| 300 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 301 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 302 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 303 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 304 | ||
| 305 | /* UPM Refresh Timer RAM array entry -> unused */ | |
| 306 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 307 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 308 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 309 | ||
| 310 | /* UPM Exception RAM array entry -> unsused */ | |
| 311 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| fa230445 HS |
312 | }; |
| 313 | ||
| 314 | static int chipsel = 0; | |
| 315 | ||
| 316 | /* UPM pattern for slow init */ | |
| 317 | static const uint upmTableSlow[] = | |
| 318 | { | |
| 9c0f42ec WD |
319 | /* Offset UPM Read Single RAM array entry */ |
| 320 | /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, | |
| 321 | /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, | |
| 322 | ||
| 323 | /* UPM Read Burst RAM array entry -> unused */ | |
| 324 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 325 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 326 | ||
| 327 | /* UPM Read Burst RAM array entry -> unused */ | |
| 328 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 329 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 330 | ||
| 331 | /* UPM Write Single RAM array entry */ | |
| 332 | /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, | |
| 333 | /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, | |
| 334 | ||
| 335 | /* UPM Write Burst RAM array entry -> unused */ | |
| 336 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 337 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 338 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 339 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 340 | ||
| 341 | /* UPM Refresh Timer RAM array entry -> unused */ | |
| 342 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 343 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 344 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 345 | ||
| 346 | /* UPM Exception RAM array entry -> unused */ | |
| 347 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| fa230445 HS |
348 | }; |
| 349 | ||
| 350 | /* UPM pattern for fast init */ | |
| 351 | static const uint upmTableFast[] = | |
| 352 | { | |
| 9c0f42ec WD |
353 | /* Offset UPM Read Single RAM array entry */ |
| 354 | /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, | |
| 355 | /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, | |
| 356 | ||
| 357 | /* UPM Read Burst RAM array entry -> unused */ | |
| 358 | /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 359 | /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 360 | ||
| 361 | /* UPM Read Burst RAM array entry -> unused */ | |
| 362 | /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 363 | /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 364 | ||
| 365 | /* UPM Write Single RAM array entry */ | |
| 366 | /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, | |
| 367 | /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, | |
| 368 | ||
| 369 | /* UPM Write Burst RAM array entry -> unused */ | |
| 370 | /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 371 | /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 372 | /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 373 | /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 374 | ||
| 375 | /* UPM Refresh Timer RAM array entry -> unused */ | |
| 376 | /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 377 | /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | |
| 378 | /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| 379 | ||
| 380 | /* UPM Exception RAM array entry -> unused */ | |
| 381 | /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | |
| fa230445 HS |
382 | }; |
| 383 | ||
| 384 | ||
| 385 | /* ------------------------------------------------------------------------- */ | |
| 386 | ||
| 387 | /* Check Board Identity: | |
| 388 | */ | |
| 389 | int checkboard (void) | |
| 390 | { | |
| 391 | char *p = (char *) HWIB_INFO_START_ADDR; | |
| 392 | ||
| 393 | puts ("Board: "); | |
| 394 | if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { | |
| 395 | puts (p); | |
| 396 | } else { | |
| 397 | puts ("No HWIB assuming TQM8272"); | |
| 398 | } | |
| 399 | putc ('\n'); | |
| 400 | ||
| 401 | return 0; | |
| 402 | } | |
| 403 | ||
| 404 | /* ------------------------------------------------------------------------- */ | |
| 405 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
| 406 | static int get_cas_latency (void) | |
| 407 | { | |
| 408 | /* get it from the option -ts in CIB */ | |
| 409 | /* default is 3 */ | |
| 410 | int ret = 3; | |
| 411 | int pos = 0; | |
| 412 | char *p = (char *) CIB_INFO_START_ADDR; | |
| 413 | ||
| 414 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
| 415 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
| 416 | return ret; | |
| 417 | } | |
| 418 | if (*p == '-') { | |
| 419 | if ((p[1] == 't') && (p[2] == 's')) { | |
| 420 | return (p[4] - '0'); | |
| 421 | } | |
| 422 | } | |
| 423 | p++; | |
| 424 | pos++; | |
| 425 | } | |
| 426 | return ret; | |
| 427 | } | |
| 428 | #endif | |
| 429 | ||
| 430 | static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) | |
| 431 | { | |
| 432 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
| 433 | int clk = board_get_cpu_clk_f (); | |
| 434 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
| 435 | int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); | |
| 436 | int cas; | |
| 437 | ||
| 438 | sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ | |
| 439 | PSDMR_BUFCMD); | |
| 440 | if (busmode) { | |
| 441 | switch (clk) { | |
| 442 | case 66666666: | |
| 443 | sdmr |= (PSDMR_RFRC_66MHZ_60X | \ | |
| 444 | PSDMR_PRETOACT_66MHZ_60X | \ | |
| 445 | PSDMR_WRC_66MHZ_60X | \ | |
| 446 | PSDMR_BUFCMD_66MHZ_60X); | |
| 447 | break; | |
| 448 | case 100000000: | |
| 449 | sdmr |= (PSDMR_RFRC_100MHZ_60X | \ | |
| 450 | PSDMR_PRETOACT_100MHZ_60X | \ | |
| 451 | PSDMR_WRC_100MHZ_60X | \ | |
| 452 | PSDMR_BUFCMD_100MHZ_60X); | |
| 453 | break; | |
| 454 | ||
| 455 | } | |
| 456 | } else { | |
| 457 | switch (clk) { | |
| 458 | case 66666666: | |
| 459 | sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ | |
| 460 | PSDMR_PRETOACT_66MHZ_SINGLE | \ | |
| 461 | PSDMR_WRC_66MHZ_SINGLE | \ | |
| 462 | PSDMR_BUFCMD_66MHZ_SINGLE); | |
| 463 | break; | |
| 464 | case 100000000: | |
| 465 | sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ | |
| 466 | PSDMR_PRETOACT_100MHZ_SINGLE | \ | |
| 467 | PSDMR_WRC_100MHZ_SINGLE | \ | |
| 468 | PSDMR_BUFCMD_100MHZ_SINGLE); | |
| 469 | break; | |
| 470 | case 133333333: | |
| 471 | sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ | |
| 472 | PSDMR_PRETOACT_133MHZ_SINGLE | \ | |
| 473 | PSDMR_WRC_133MHZ_SINGLE | \ | |
| 474 | PSDMR_BUFCMD_133MHZ_SINGLE); | |
| 475 | break; | |
| 476 | } | |
| 477 | } | |
| 478 | cas = get_cas_latency(); | |
| 479 | sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); | |
| 480 | sdmr |= cas; | |
| 481 | sdmr |= ((cas - 1) << 6); | |
| 482 | return sdmr; | |
| 483 | #else | |
| 484 | return sdmr; | |
| 485 | #endif | |
| 486 | } | |
| 487 | ||
| 488 | /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
| 489 | * | |
| 490 | * This routine performs standard 8260 initialization sequence | |
| 491 | * and calculates the available memory size. It may be called | |
| 492 | * several times to try different SDRAM configurations on both | |
| 493 | * 60x and local buses. | |
| 494 | */ | |
| 495 | static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, | |
| 496 | ulong orx, volatile uchar * base, int col) | |
| 497 | { | |
| 498 | volatile uchar c = 0xff; | |
| 499 | volatile uint *sdmr_ptr; | |
| 500 | volatile uint *orx_ptr; | |
| 501 | ulong maxsize, size; | |
| 502 | int i; | |
| 503 | ||
| 504 | /* We must be able to test a location outsize the maximum legal size | |
| 505 | * to find out THAT we are outside; but this address still has to be | |
| 506 | * mapped by the controller. That means, that the initial mapping has | |
| 507 | * to be (at least) twice as large as the maximum expected size. | |
| 508 | */ | |
| 509 | maxsize = (1 + (~orx | 0x7fff)) / 2; | |
| 510 | ||
| 511 | /* Since CFG_SDRAM_BASE is always 0 (??), we assume that | |
| 512 | * we are configuring CS1 if base != 0 | |
| 513 | */ | |
| 514 | sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; | |
| 515 | orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; | |
| 516 | ||
| 517 | *orx_ptr = orx; | |
| 518 | sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); | |
| 519 | /* | |
| 520 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
| 521 | * | |
| 522 | * "At system reset, initialization software must set up the | |
| 523 | * programmable parameters in the memory controller banks registers | |
| 524 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
| 525 | * system software should execute the following initialization sequence | |
| 526 | * for each SDRAM device. | |
| 527 | * | |
| 528 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
| 529 | * 2. Issue eight CBR REFRESH commands | |
| 530 | * 3. Issue a MODE-SET command to initialize the mode register | |
| 531 | * | |
| 532 | * The initial commands are executed by setting P/LSDMR[OP] and | |
| 533 | * accessing the SDRAM with a single-byte transaction." | |
| 534 | * | |
| 535 | * The appropriate BRx/ORx registers have already been set when we | |
| 536 | * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. | |
| 537 | */ | |
| 538 | ||
| 539 | *sdmr_ptr = sdmr | PSDMR_OP_PREA; | |
| 540 | *base = c; | |
| 541 | ||
| 542 | *sdmr_ptr = sdmr | PSDMR_OP_CBRR; | |
| 543 | for (i = 0; i < 8; i++) | |
| 544 | *base = c; | |
| 545 | ||
| 546 | *sdmr_ptr = sdmr | PSDMR_OP_MRW; | |
| 547 | *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ | |
| 548 | ||
| 549 | *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
| 550 | *base = c; | |
| 551 | ||
| 552 | size = get_ram_size((long *)base, maxsize); | |
| 553 | *orx_ptr = orx | ~(size - 1); | |
| 554 | ||
| 555 | return (size); | |
| 556 | } | |
| 557 | ||
| 9973e3c6 | 558 | phys_size_t initdram (int board_type) |
| fa230445 HS |
559 | { |
| 560 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
| 561 | volatile memctl8260_t *memctl = &immap->im_memctl; | |
| 562 | ||
| 563 | #ifndef CFG_RAMBOOT | |
| 564 | long size8, size9; | |
| 565 | #endif | |
| 566 | long psize, lsize; | |
| 567 | ||
| 568 | psize = 16 * 1024 * 1024; | |
| 569 | lsize = 0; | |
| 570 | ||
| 571 | memctl->memc_psrt = CFG_PSRT; | |
| 572 | memctl->memc_mptpr = CFG_MPTPR; | |
| 573 | ||
| 574 | #ifndef CFG_RAMBOOT | |
| 575 | /* 60x SDRAM setup: | |
| 576 | */ | |
| 577 | size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, | |
| 578 | (uchar *) CFG_SDRAM_BASE, 8); | |
| 579 | size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, | |
| 580 | (uchar *) CFG_SDRAM_BASE, 9); | |
| 581 | ||
| 582 | if (size8 < size9) { | |
| 583 | psize = size9; | |
| 584 | printf ("(60x:9COL - %ld MB, ", psize >> 20); | |
| 585 | } else { | |
| 586 | psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, | |
| 587 | (uchar *) CFG_SDRAM_BASE, 8); | |
| 588 | printf ("(60x:8COL - %ld MB, ", psize >> 20); | |
| 589 | } | |
| 590 | ||
| 591 | #endif /* CFG_RAMBOOT */ | |
| 592 | ||
| 593 | icache_enable (); | |
| 594 | ||
| 595 | return (psize); | |
| 596 | } | |
| 597 | ||
| 598 | ||
| 599 | static inline int scanChar (char *p, int len, unsigned long *number) | |
| 600 | { | |
| 601 | int akt = 0; | |
| 602 | ||
| 603 | *number = 0; | |
| 9c0f42ec | 604 | while (akt < len) { |
| fa230445 HS |
605 | if ((*p >= '0') && (*p <= '9')) { |
| 606 | *number *= 10; | |
| 607 | *number += *p - '0'; | |
| 608 | p += 1; | |
| 609 | } else { | |
| 610 | if (*p == '-') return akt; | |
| 611 | return -1; | |
| 612 | } | |
| 613 | akt ++; | |
| 614 | } | |
| 615 | return akt; | |
| 616 | } | |
| 617 | ||
| 618 | typedef struct{ | |
| 619 | int Bus; | |
| 620 | int flash; | |
| 621 | int flash_nr; | |
| 622 | int ram; | |
| 623 | int ram_cs; | |
| 624 | int nand; | |
| 625 | int nand_cs; | |
| 626 | int eeprom; | |
| 627 | int can; | |
| 628 | unsigned long cpunr; | |
| 629 | unsigned long option; | |
| 630 | int SecEng; | |
| 631 | int cpucl; | |
| 632 | int cpmcl; | |
| 633 | int buscl; | |
| 634 | int busclk_real_ok; | |
| 635 | int busclk_real; | |
| 636 | unsigned char OK; | |
| 637 | unsigned char ethaddr[20]; | |
| 638 | } HWIB_INFO; | |
| 639 | ||
| 640 | HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, | |
| 641 | 0, 0, 0, 0, 0, 0}; | |
| 642 | ||
| 643 | static int dump_hwib(void) | |
| 644 | { | |
| 645 | HWIB_INFO *hw = &hwinf; | |
| 646 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
| 647 | char *s = getenv("serial#"); | |
| 648 | ||
| 649 | if (hw->OK) { | |
| 650 | printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); | |
| 651 | printf ("serial : %s\n", s); | |
| 652 | printf ("ethaddr: %s\n", hw->ethaddr); | |
| 9c0f42ec WD |
653 | printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); |
| 654 | printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); | |
| 9b55a253 | 655 | printf ("CPU : %lu\n", hw->cpunr); |
| 9c0f42ec | 656 | printf ("CAN : %d\n", hw->can); |
| fa230445 HS |
657 | if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); |
| 658 | else printf ("No EEprom\n"); | |
| 659 | if (hw->nand) { | |
| 9c0f42ec | 660 | printf ("NAND : %x\n", hw->nand); |
| fa230445 HS |
661 | printf ("NAND CS: %d\n", hw->nand_cs); |
| 662 | } else { printf ("No NAND\n");} | |
| 663 | printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); | |
| 664 | printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ | |
| 665 | "60x" : "Single PQII")); | |
| 9b55a253 | 666 | printf ("Option : %lx\n", hw->option); |
| fa230445 HS |
667 | printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); |
| 668 | printf ("CPM Clk: %d\n", hw->cpmcl); | |
| 669 | printf ("CPU Clk: %d\n", hw->cpucl); | |
| 670 | printf ("Bus Clk: %d\n", hw->buscl); | |
| 671 | if (hw->busclk_real_ok) { | |
| 672 | printf (" real Clk: %d\n", hw->busclk_real); | |
| 673 | } | |
| 9c0f42ec | 674 | printf ("CAS : %d\n", get_cas_latency()); |
| fa230445 HS |
675 | } else { |
| 676 | printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); | |
| 677 | } | |
| 678 | return 0; | |
| 679 | } | |
| 680 | ||
| 681 | static inline int search_real_busclk (int *clk) | |
| 682 | { | |
| 683 | int part = 0, pos = 0; | |
| 684 | char *p = (char *) CIB_INFO_START_ADDR; | |
| 685 | int ok = 0; | |
| 686 | ||
| 687 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
| 688 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
| 689 | return 0; | |
| 690 | } | |
| 691 | switch (part) { | |
| 692 | default: | |
| 693 | if (*p == '-') { | |
| 694 | ++part; | |
| 695 | } | |
| 696 | break; | |
| 697 | case 3: | |
| 698 | if (*p == '-') { | |
| 699 | ++part; | |
| 700 | break; | |
| 701 | } | |
| 702 | if (*p == 'b') { | |
| 703 | ok = 1; | |
| 704 | p++; | |
| 705 | break; | |
| 706 | } | |
| 707 | if (ok) { | |
| 708 | switch (*p) { | |
| 709 | case '6': | |
| 710 | *clk = 66666666; | |
| 711 | return 1; | |
| 712 | break; | |
| 713 | case '1': | |
| 714 | if (p[1] == '3') { | |
| 715 | *clk = 133333333; | |
| 716 | } else { | |
| 717 | *clk = 100000000; | |
| 718 | } | |
| 719 | return 1; | |
| 720 | break; | |
| 721 | } | |
| 722 | } | |
| 723 | break; | |
| 724 | } | |
| 725 | p++; | |
| 726 | } | |
| 727 | return 0; | |
| 728 | } | |
| 729 | ||
| 730 | int analyse_hwib (void) | |
| 731 | { | |
| 732 | char *p = (char *) HWIB_INFO_START_ADDR; | |
| 733 | int anz; | |
| 734 | int part = 1, i = 0, pos = 0; | |
| 735 | HWIB_INFO *hw = &hwinf; | |
| 736 | ||
| 737 | deb_printf(" %s pointer: %p\n", __FUNCTION__, p); | |
| 738 | /* Head = TQM */ | |
| 739 | if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) { | |
| 740 | deb_printf("No HWIB\n"); | |
| 741 | return -1; | |
| 742 | } | |
| 743 | p += 3; | |
| 744 | if (scanChar (p, 4, &hw->cpunr) < 0) { | |
| 745 | deb_printf("No CPU\n"); | |
| 746 | return -2; | |
| 747 | } | |
| 748 | p +=4; | |
| 749 | ||
| 750 | hw->flash = 0x200000 << (*p - 'A'); | |
| 751 | p++; | |
| 752 | hw->flash_nr = *p - '0'; | |
| 753 | p++; | |
| 754 | ||
| 755 | hw->ram = 0x2000000 << (*p - 'A'); | |
| 756 | p++; | |
| 757 | if (*p == '2') { | |
| 758 | hw->ram_cs = 2; | |
| 759 | p++; | |
| 760 | } | |
| 761 | ||
| 9c0f42ec WD |
762 | if (*p == 'A') hw->can = 1; |
| 763 | if (*p == 'B') hw->can = 2; | |
| fa230445 HS |
764 | p +=1; |
| 765 | p +=1; /* connector */ | |
| 766 | if (*p != '0') { | |
| 07e82cb2 | 767 | hw->eeprom = 0x1000 << (*p - 'A'); |
| fa230445 HS |
768 | } |
| 769 | p++; | |
| 9c0f42ec WD |
770 | |
| 771 | if ((*p < '0') || (*p > '9')) { | |
| fa230445 HS |
772 | /* NAND before z-option */ |
| 773 | hw->nand = 0x8000000 << (*p - 'A'); | |
| 774 | p++; | |
| 775 | hw->nand_cs = *p - '0'; | |
| 776 | p += 2; | |
| 777 | } | |
| 778 | /* z-option */ | |
| 779 | anz = scanChar (p, 4, &hw->option); | |
| 780 | if (anz < 0) { | |
| 781 | deb_printf("No option\n"); | |
| 782 | return -3; | |
| 783 | } | |
| 784 | if (hw->option & 0x8) hw->Bus = 1; | |
| 785 | p += anz; | |
| 786 | if (*p != '-') { | |
| 787 | deb_printf("No -\n"); | |
| 788 | return -4; | |
| 789 | } | |
| 790 | p++; | |
| 791 | /* C option */ | |
| 792 | if (*p == 'E') { | |
| 793 | hw->SecEng = 1; | |
| 794 | p++; | |
| 795 | } | |
| 796 | switch (*p) { | |
| 797 | case 'M': hw->cpucl = 266666666; | |
| 798 | break; | |
| 799 | case 'P': hw->cpucl = 300000000; | |
| 800 | break; | |
| 801 | case 'T': hw->cpucl = 400000000; | |
| 802 | break; | |
| 803 | default: | |
| 804 | deb_printf("No CPU Clk: %c\n", *p); | |
| 805 | return -5; | |
| 806 | break; | |
| 807 | } | |
| 808 | p++; | |
| 809 | switch (*p) { | |
| 810 | case 'I': hw->cpmcl = 200000000; | |
| 811 | break; | |
| 812 | case 'M': hw->cpmcl = 300000000; | |
| 813 | break; | |
| 814 | default: | |
| 815 | deb_printf("No CPM Clk\n"); | |
| 816 | return -6; | |
| 817 | break; | |
| 818 | } | |
| 819 | p++; | |
| 820 | switch (*p) { | |
| 821 | case 'B': hw->buscl = 66666666; | |
| 822 | break; | |
| 823 | case 'E': hw->buscl = 100000000; | |
| 824 | break; | |
| 825 | case 'F': hw->buscl = 133333333; | |
| 826 | break; | |
| 827 | default: | |
| 828 | deb_printf("No BUS Clk\n"); | |
| 829 | return -7; | |
| 830 | break; | |
| 831 | } | |
| 832 | p++; | |
| 833 | ||
| 834 | hw->OK = 1; | |
| 835 | /* search MAC Address */ | |
| 836 | while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) { | |
| 837 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
| 838 | return 0; | |
| 839 | } | |
| 840 | switch (part) { | |
| 841 | default: | |
| 842 | if (*p == ' ') { | |
| 843 | ++part; | |
| 844 | i = 0; | |
| 845 | } | |
| 846 | break; | |
| 847 | case 3: /* Copy MAC address */ | |
| 848 | if (*p == ' ') { | |
| 849 | ++part; | |
| 850 | i = 0; | |
| 851 | break; | |
| 852 | } | |
| 853 | hw->ethaddr[i++] = *p; | |
| 854 | if ((i % 3) == 2) | |
| 855 | hw->ethaddr[i++] = ':'; | |
| 856 | break; | |
| 857 | ||
| 858 | } | |
| 859 | p++; | |
| 860 | } | |
| 861 | ||
| 862 | hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); | |
| 863 | return 0; | |
| 864 | } | |
| 865 | ||
| 866 | #if defined(CONFIG_GET_CPU_STR_F) | |
| 867 | /* !! This routine runs from Flash */ | |
| 868 | char get_cpu_str_f (char *buf) | |
| 869 | { | |
| 870 | char *p = (char *) HWIB_INFO_START_ADDR; | |
| 871 | int i = 0; | |
| 872 | ||
| 873 | buf[i++] = 'M'; | |
| 874 | buf[i++] = 'P'; | |
| 875 | buf[i++] = 'C'; | |
| 876 | if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { | |
| 877 | buf[i++] = *&p[3]; | |
| 878 | buf[i++] = *&p[4]; | |
| 879 | buf[i++] = *&p[5]; | |
| 880 | buf[i++] = *&p[6]; | |
| 881 | } else { | |
| 882 | buf[i++] = '8'; | |
| 883 | buf[i++] = '2'; | |
| 884 | buf[i++] = '7'; | |
| 885 | buf[i++] = 'x'; | |
| 886 | } | |
| 887 | buf[i++] = 0; | |
| 888 | return 0; | |
| 889 | } | |
| 890 | #endif | |
| 891 | ||
| 892 | #if defined(CONFIG_BOARD_GET_CPU_CLK_F) | |
| 893 | /* !! This routine runs from Flash */ | |
| 894 | unsigned long board_get_cpu_clk_f (void) | |
| 895 | { | |
| 896 | char *p = (char *) HWIB_INFO_START_ADDR; | |
| 897 | int i = 0; | |
| 898 | ||
| 899 | if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { | |
| 900 | if (search_real_busclk (&i)) | |
| 901 | return i; | |
| 902 | } | |
| 903 | return CONFIG_8260_CLKIN; | |
| 904 | } | |
| 905 | #endif | |
| 906 | ||
| 907 | #if CONFIG_BOARD_EARLY_INIT_R | |
| 908 | ||
| 909 | static int can_test (unsigned long off) | |
| 910 | { | |
| 9c0f42ec | 911 | volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off); |
| fa230445 HS |
912 | |
| 913 | *(base + 0x17) = 'T'; | |
| 914 | *(base + 0x18) = 'Q'; | |
| 915 | *(base + 0x19) = 'M'; | |
| 916 | if ((*(base + 0x17) != 'T') || | |
| 917 | (*(base + 0x18) != 'Q') || | |
| 918 | (*(base + 0x19) != 'M')) { | |
| 919 | return 0; | |
| 920 | } | |
| 921 | return 1; | |
| 922 | } | |
| 923 | ||
| 924 | static int can_config_one (unsigned long off) | |
| 925 | { | |
| 9c0f42ec WD |
926 | volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off); |
| 927 | volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02); | |
| 928 | volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f); | |
| fa230445 HS |
929 | unsigned char temp; |
| 930 | ||
| 9c0f42ec | 931 | *cpu_if = 0x45; |
| fa230445 HS |
932 | temp = *ctrl; |
| 933 | temp |= 0x40; | |
| 934 | *ctrl = temp; | |
| 9c0f42ec | 935 | *clkout = 0x20; |
| fa230445 HS |
936 | temp = *ctrl; |
| 937 | temp &= ~0x40; | |
| 938 | *ctrl = temp; | |
| 939 | return 0; | |
| 940 | } | |
| 941 | ||
| 942 | static int can_config (void) | |
| 943 | { | |
| 944 | int ret = 0; | |
| 945 | can_config_one (0); | |
| 946 | if (hwinf.can == 2) { | |
| 947 | can_config_one (0x100); | |
| 948 | } | |
| 949 | /* make Test if they really there */ | |
| 950 | ret += can_test (0); | |
| 951 | ret += can_test (0x100); | |
| 952 | return ret; | |
| 953 | } | |
| 954 | ||
| 955 | static int init_can (void) | |
| 956 | { | |
| 9c0f42ec | 957 | volatile immap_t * immr = (immap_t *)CFG_IMMR; |
| fa230445 HS |
958 | volatile memctl8260_t *memctl = &immr->im_memctl; |
| 959 | int count = 0; | |
| 960 | ||
| 961 | if ((hwinf.OK) && (hwinf.can)) { | |
| 962 | memctl->memc_or4 = CFG_CAN_OR; | |
| 963 | memctl->memc_br4 = CFG_CAN_BR; | |
| 964 | /* upm Init */ | |
| 965 | upmconfig (UPMC, (uint *) upmTableFast, | |
| 966 | sizeof (upmTableFast) / sizeof (uint)); | |
| 967 | memctl->memc_mcmr = (MxMR_DSx_3_CYCL | | |
| 968 | MxMR_GPL_x4DIS | | |
| 969 | MxMR_RLFx_2X | | |
| 970 | MxMR_WLFx_2X | | |
| 971 | MxMR_OP_NORM); | |
| 972 | /* can configure */ | |
| 973 | count = can_config (); | |
| 9c0f42ec | 974 | printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE); |
| fa230445 HS |
975 | if (hwinf.can != count) printf("!!! difference to HWIB\n"); |
| 976 | } else { | |
| 9c0f42ec | 977 | printf ("CAN: No\n"); |
| fa230445 HS |
978 | } |
| 979 | return 0; | |
| 980 | } | |
| 981 | ||
| 982 | int board_early_init_r(void) | |
| 983 | { | |
| 984 | analyse_hwib (); | |
| 985 | init_can (); | |
| 986 | return 0; | |
| 987 | } | |
| 988 | #endif | |
| 989 | ||
| 990 | int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
| 991 | { | |
| 992 | dump_hwib (); | |
| 993 | return 0; | |
| 994 | } | |
| 995 | ||
| 996 | U_BOOT_CMD( | |
| 9c0f42ec WD |
997 | hwib, 1, 1, do_hwib_dump, |
| 998 | "hwib - dump HWIB'\n", | |
| fa230445 HS |
999 | "\n" |
| 1000 | ); | |
| 1001 | ||
| 1002 | #ifdef CFG_UPDATE_FLASH_SIZE | |
| 1003 | static int get_flash_timing (void) | |
| 1004 | { | |
| 1005 | /* get it from the option -tf in CIB */ | |
| 1006 | /* default is 0x00000c84 */ | |
| 1007 | int ret = 0x00000c84; | |
| 1008 | int pos = 0; | |
| 1009 | int nr = 0; | |
| 1010 | char *p = (char *) CIB_INFO_START_ADDR; | |
| 1011 | ||
| 1012 | while ((*p != '\0') && (pos < CIB_INFO_LEN)) { | |
| 1013 | if (*p < ' ' || *p > '~') { /* ASCII strings! */ | |
| 1014 | return ret; | |
| 1015 | } | |
| 1016 | if (*p == '-') { | |
| 1017 | if ((p[1] == 't') && (p[2] == 'f')) { | |
| 1018 | p += 6; | |
| 1019 | ret = 0; | |
| 1020 | while (nr < 8) { | |
| 1021 | if ((*p >= '0') && (*p <= '9')) { | |
| 1022 | ret *= 0x10; | |
| 1023 | ret += *p - '0'; | |
| 1024 | p += 1; | |
| 1025 | nr ++; | |
| 1026 | } else if ((*p >= 'A') && (*p <= 'F')) { | |
| 1027 | ret *= 10; | |
| 1028 | ret += *p - '7'; | |
| 1029 | p += 1; | |
| 1030 | nr ++; | |
| 1031 | } else { | |
| 1032 | if (nr < 8) return 0x00000c84; | |
| 1033 | return ret; | |
| 1034 | } | |
| 1035 | } | |
| 1036 | } | |
| 1037 | } | |
| 1038 | p++; | |
| 1039 | pos++; | |
| 1040 | } | |
| 1041 | return ret; | |
| 1042 | } | |
| 1043 | ||
| 1044 | /* Update the Flash_Size and the Flash Timing */ | |
| 1045 | int update_flash_size (int flash_size) | |
| 1046 | { | |
| 9c0f42ec | 1047 | volatile immap_t * immr = (immap_t *)CFG_IMMR; |
| fa230445 HS |
1048 | volatile memctl8260_t *memctl = &immr->im_memctl; |
| 1049 | unsigned long reg; | |
| 1050 | unsigned long tim; | |
| 1051 | ||
| 1052 | /* I must use reg, otherwise the board hang */ | |
| 1053 | reg = memctl->memc_or0; | |
| 1054 | reg &= ~ORxU_AM_MSK; | |
| 1055 | reg |= MEG_TO_AM(flash_size >> 20); | |
| 1056 | tim = get_flash_timing (); | |
| 1057 | reg &= ~0xfff; | |
| 1058 | reg |= (tim & 0xfff); | |
| 1059 | memctl->memc_or0 = reg; | |
| 1060 | return 0; | |
| 1061 | } | |
| 1062 | #endif | |
| 1063 | ||
| ab3abcba | 1064 | #if defined(CONFIG_CMD_NAND) |
| fa230445 HS |
1065 | |
| 1066 | #include <nand.h> | |
| 1067 | #include <linux/mtd/mtd.h> | |
| 1068 | ||
| 1069 | static u8 hwctl = 0; | |
| 1070 | ||
| cfa460ad | 1071 | static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| fa230445 | 1072 | { |
| cfa460ad WJ |
1073 | struct nand_chip *this = mtd->priv; |
| 1074 | ||
| 1075 | if (ctrl & NAND_CTRL_CHANGE) { | |
| 1076 | if ( ctrl & NAND_CLE ) | |
| 1077 | hwctl |= 0x1; | |
| 1078 | else | |
| 1079 | hwctl &= ~0x1; | |
| 1080 | if ( ctrl & NAND_ALE ) | |
| 1081 | hwctl |= 0x2; | |
| 1082 | else | |
| 1083 | hwctl &= ~0x2; | |
| fa230445 | 1084 | } |
| cfa460ad WJ |
1085 | if (cmd != NAND_CMD_NONE) |
| 1086 | writeb(cmd, this->IO_ADDR_W); | |
| fa230445 HS |
1087 | } |
| 1088 | ||
| 1089 | static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) | |
| 1090 | { | |
| 1091 | struct nand_chip *this = mtdinfo->priv; | |
| 1092 | ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); | |
| 1093 | ||
| 1094 | if (hwctl & 0x1) { | |
| 1095 | WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); | |
| 1096 | } else if (hwctl & 0x2) { | |
| 1097 | WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); | |
| 1098 | } else { | |
| 1099 | WRITE_NAND(byte, base); | |
| 1100 | } | |
| 1101 | } | |
| 1102 | ||
| 1103 | static u_char upmnand_read_byte(struct mtd_info *mtdinfo) | |
| 1104 | { | |
| 1105 | struct nand_chip *this = mtdinfo->priv; | |
| 1106 | ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); | |
| 1107 | ||
| 1108 | return READ_NAND(base); | |
| 1109 | } | |
| 1110 | ||
| 1111 | static int tqm8272_dev_ready(struct mtd_info *mtdinfo) | |
| 1112 | { | |
| 1113 | /* constant delay (see also tR in the datasheet) */ | |
| 1114 | udelay(12); \ | |
| 1115 | return 1; | |
| 1116 | } | |
| 1117 | ||
| 1118 | #ifndef CONFIG_NAND_SPL | |
| 1119 | static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) | |
| 1120 | { | |
| 1121 | struct nand_chip *this = mtdinfo->priv; | |
| 1122 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); | |
| 1123 | int i; | |
| 1124 | ||
| 1125 | for (i = 0; i< len; i++) | |
| 1126 | buf[i] = *base; | |
| 1127 | } | |
| 1128 | ||
| 1129 | static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) | |
| 1130 | { | |
| 1131 | struct nand_chip *this = mtdinfo->priv; | |
| 1132 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); | |
| 1133 | int i; | |
| 1134 | ||
| 1135 | for (i = 0; i< len; i++) | |
| 1136 | *base = buf[i]; | |
| 1137 | } | |
| 1138 | ||
| 1139 | static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) | |
| 1140 | { | |
| 1141 | struct nand_chip *this = mtdinfo->priv; | |
| 1142 | unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); | |
| 1143 | int i; | |
| 1144 | ||
| 1145 | for (i = 0; i < len; i++) | |
| 1146 | if (buf[i] != *base) | |
| 1147 | return -1; | |
| 1148 | return 0; | |
| 1149 | } | |
| 1150 | #endif /* #ifndef CONFIG_NAND_SPL */ | |
| 1151 | ||
| 1152 | void board_nand_select_device(struct nand_chip *nand, int chip) | |
| 1153 | { | |
| 1154 | chipsel = chip; | |
| 1155 | } | |
| 1156 | ||
| 1157 | int board_nand_init(struct nand_chip *nand) | |
| 1158 | { | |
| 1159 | static int UpmInit = 0; | |
| 9c0f42ec | 1160 | volatile immap_t * immr = (immap_t *)CFG_IMMR; |
| fa230445 HS |
1161 | volatile memctl8260_t *memctl = &immr->im_memctl; |
| 1162 | ||
| 1163 | if (hwinf.nand == 0) return -1; | |
| 9c0f42ec | 1164 | |
| fa230445 HS |
1165 | /* Setup the UPM */ |
| 1166 | if (UpmInit == 0) { | |
| 1167 | switch (hwinf.busclk_real) { | |
| 1168 | case 100000000: | |
| 1169 | upmconfig (UPMB, (uint *) upmTable100, | |
| 1170 | sizeof (upmTable100) / sizeof (uint)); | |
| 1171 | break; | |
| 1172 | case 133333333: | |
| 1173 | upmconfig (UPMB, (uint *) upmTable133, | |
| 1174 | sizeof (upmTable133) / sizeof (uint)); | |
| 1175 | break; | |
| 1176 | default: | |
| 1177 | upmconfig (UPMB, (uint *) upmTable67, | |
| 1178 | sizeof (upmTable67) / sizeof (uint)); | |
| 1179 | break; | |
| 1180 | } | |
| 1181 | UpmInit = 1; | |
| 1182 | } | |
| 1183 | ||
| 1184 | /* Setup the memctrl */ | |
| 1185 | memctl->memc_or3 = CFG_NAND_OR; | |
| 1186 | memctl->memc_br3 = CFG_NAND_BR; | |
| 1187 | memctl->memc_mbmr = (MxMR_OP_NORM); | |
| 1188 | ||
| cfa460ad | 1189 | nand->ecc.mode = NAND_ECC_SOFT; |
| fa230445 | 1190 | |
| cfa460ad | 1191 | nand->cmd_ctrl = upmnand_hwcontrol; |
| 9c0f42ec | 1192 | nand->read_byte = upmnand_read_byte; |
| fa230445 | 1193 | nand->write_byte = upmnand_write_byte; |
| 9c0f42ec WD |
1194 | nand->dev_ready = tqm8272_dev_ready; |
| 1195 | ||
| fa230445 | 1196 | #ifndef CONFIG_NAND_SPL |
| 9c0f42ec WD |
1197 | nand->write_buf = tqm8272_write_buf; |
| 1198 | nand->read_buf = tqm8272_read_buf; | |
| fa230445 HS |
1199 | nand->verify_buf = tqm8272_verify_buf; |
| 1200 | #endif | |
| 1201 | ||
| 1202 | /* | |
| 1203 | * Select required NAND chip | |
| 1204 | */ | |
| 1205 | board_nand_select_device(nand, 0); | |
| 1206 | return 0; | |
| 1207 | } | |
| 1208 | ||
| d39b5741 | 1209 | #endif |
| fa230445 HS |
1210 | |
| 1211 | #ifdef CONFIG_PCI | |
| 1212 | struct pci_controller hose; | |
| 1213 | ||
| 1214 | int board_early_init_f (void) | |
| 1215 | { | |
| 1216 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
| 1217 | ||
| 1218 | immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; | |
| 1219 | return 0; | |
| 1220 | } | |
| 1221 | ||
| 1222 | extern void pci_mpc8250_init(struct pci_controller *); | |
| 1223 | ||
| 1224 | void pci_init_board(void) | |
| 1225 | { | |
| 1226 | pci_mpc8250_init(&hose); | |
| 1227 | } | |
| 1228 | #endif |