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fsl: Clean up printing of PCI boot info
[people/ms/u-boot.git] / board / tqc / tqm85xx / tqm85xx.c
CommitLineData
f5c5ef4a 1/*
1287e0c5
WG		 2 * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
3 *
4 * (C) Copyright 2006
5 * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
6 *
d96f41e0
SR		 7 * (C) Copyright 2005
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
f5c5ef4a
WD		 10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2002,2003, Motorola Inc.
12 * Xianghua Xiao, (X.Xiao@motorola.com)
13 *
14 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
3cbd8231 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
f5c5ef4a
WD		 27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
f5c5ef4a
WD		 35#include <common.h>
36#include <pci.h>
37#include <asm/processor.h>
38#include <asm/immap_85xx.h>
c8514622 39#include <asm/fsl_pci.h>
d9ee843d 40#include <asm/io.h>
06412756 41#include <linux/compiler.h>
f5c5ef4a 42#include <ioports.h>
d96f41e0 43#include <flash.h>
25991353
WG		 44#include <libfdt.h>
45#include <fdt_support.h>
10efa024 46#include <netdev.h>
f5c5ef4a 47
d87080b7
WD		 48DECLARE_GLOBAL_DATA_PTR;
49
d96f41e0 50extern flash_info_t flash_info[]; /* FLASH chips info */
f5c5ef4a
WD		 51
52void local_bus_init (void);
f18e874a 53ulong flash_get_size (ulong base, int banknum);
966083e9 54
bd3143f0 55#ifdef CONFIG_PS2MULT
b99ba167 56void ps2mult_early_init (void);
bd3143f0 57#endif
f5c5ef4a 58
d96f41e0 59#ifdef CONFIG_CPM2
f5c5ef4a
WD		 60/*
61 * I/O Port configuration table
62 *
63 * if conf is 1, then that port pin will be configured at boot time
64 * according to the five values podr/pdir/ppar/psor/pdat for that entry
65 */
66
67const iop_conf_t iop_conf_tab[4][32] = {
68
b99ba167
WG		 69 /* Port A: conf, ppar, psor, pdir, podr, pdat */
70 {
71 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
72 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
73 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
74 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
75 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
76 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
77 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
78 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
79 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
80 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
81 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
82 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
83 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
84 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
85 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
86 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
87 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
88 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
89 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
90 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
91 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
92 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
93 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
94 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
95 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
96 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
97 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
98 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
99 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
100 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
101 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
102 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
103 },
104
105 /* Port B: conf, ppar, psor, pdir, podr, pdat */
106 {
107 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
108 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
109 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
110 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
111 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
112 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
113 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
114 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
115 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
116 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
117 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
118 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
119 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
120 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
121 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
122 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
123 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
124 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
125 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
126 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
127 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
128 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
129 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
130 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
131 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
132 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
133 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
134 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
135 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
136 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
137 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
138 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
139 },
140
141 /* Port C: conf, ppar, psor, pdir, podr, pdat */
142 {
143 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
144 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
145 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
146 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
147 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
148 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
149 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
150 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
151 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
152 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
153 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
154 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
155 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
156 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
157 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
158 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
159 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
160 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
161 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
162 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
163 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
164 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
165 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
166 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
167 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
168 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
169 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
170 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
171 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
172 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
173 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
174 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
175 },
176
177 /* Port D: conf, ppar, psor, pdir, podr, pdat */
178 {
5d5bd838 179#ifdef CONFIG_TQM8560
b99ba167
WG		 180 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
181 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
182 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
5d5bd838
WG		 183#else /* !CONFIG_TQM8560 */
184 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
185 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
186 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
187#endif /* CONFIG_TQM8560 */
b99ba167
WG		 188 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
189 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
190 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
191 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
192 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
193 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
194 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
195 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
196 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
197 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
198 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
199 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
200 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
201 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
202 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
203 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
204 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
205 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
206 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
207 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
208 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
209 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
210 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
211 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
212 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
213 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
214 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
215 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
216 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
217 }
f5c5ef4a 218};
d96f41e0
SR		 219#endif /* CONFIG_CPM2 */
220
221#define CASL_STRING1 "casl=xx"
222#define CASL_STRING2 "casl="
f5c5ef4a 223
d96f41e0
SR		 224static const int casl_table[] = { 20, 25, 30 };
225#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
f5c5ef4a 226
b99ba167 227int cas_latency (void)
f5c5ef4a 228{
b99ba167 229 char *s = getenv ("serial#");
d96f41e0
SR		 230 int casl;
231 int val;
232 int i;
233
234 casl = CONFIG_DDR_DEFAULT_CL;
235
236 if (s != NULL) {
b99ba167
WG		 237 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
238 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
239 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
d96f41e0 240
b99ba167 241 for (i = 0; i < N_CASL; ++i) {
d96f41e0
SR		 242 if (val == casl_table[i]) {
243 return val;
244 }
245 }
246 }
247 }
248
249 return casl;
f5c5ef4a
WD		 250}
251
252int checkboard (void)
253{
b99ba167 254 char *s = getenv ("serial#");
d96f41e0 255
b99ba167 256 printf ("Board: %s", CONFIG_BOARDNAME);
d96f41e0 257 if (s != NULL) {
b99ba167
WG		 258 puts (", serial# ");
259 puts (s);
d96f41e0 260 }
b99ba167 261 putc ('\n');
f5c5ef4a 262
f5c5ef4a
WD		 263 /*
264 * Initialize local bus.
265 */
266 local_bus_init ();
267
268 return 0;
269}
270
d96f41e0 271int misc_init_r (void)
f5c5ef4a 272{
d96f41e0
SR		 273 /*
274 * Adjust flash start and offset to detected values
275 */
276 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
277 gd->bd->bi_flashoffset = 0;
9d2a873b 278
d96f41e0 279 /*
45dee2e6 280 * Recalculate CS configuration if second FLASH bank is available
d96f41e0 281 */
45dee2e6 282 if (flash_info[0].size > 0) {
f51cdaf1
BB		 283 set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
284 (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
285 set_lbc_br(1, gd->bd->bi_flashstart |
286 (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
f5c5ef4a 287 /*
45dee2e6 288 * Re-check to get correct base address for bank 1
f5c5ef4a 289 */
45dee2e6
WG		 290 flash_get_size (gd->bd->bi_flashstart, 0);
291 } else {
f51cdaf1
BB		 292 set_lbc_or(1, 0);
293 set_lbc_br(1, 0);
f5c5ef4a 294 }
f5c5ef4a 295
f5c5ef4a 296 /*
45dee2e6 297 * If bank 1 is equipped, bank 0 is mapped after bank 1
f5c5ef4a 298 */
f51cdaf1
BB		 299 set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
300 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
b1b76464 301 set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
f51cdaf1
BB		 302 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
303
45dee2e6
WG		 304 /*
305 * Re-check to get correct base address for bank 0
306 */
307 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
f5c5ef4a 308
45dee2e6
WG		 309 /*
310 * Re-do flash protection upon new addresses
311 */
312 flash_protect (FLAG_PROTECT_CLEAR,
313 gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf 314 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 315
316 /* Monitor protection ON by default */
317 flash_protect (FLAG_PROTECT_SET,
31ca9119 318 CONFIG_SYS_MONITOR_BASE, 0xffffffff,
6d0f6bcf 319 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6
WG		 320
321 /* Environment protection ON by default */
322 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 323 CONFIG_ENV_ADDR,
324 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf 325 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 326
0e8d1586 327#ifdef CONFIG_ENV_ADDR_REDUND
45dee2e6
WG		 328 /* Redundant environment protection ON by default */
329 flash_protect (FLAG_PROTECT_SET,
0e8d1586 330 CONFIG_ENV_ADDR_REDUND,
dfcd7f21 331 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf 332 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
45dee2e6 333#endif
f5c5ef4a 334
d96f41e0
SR		 335 return 0;
336}
f5c5ef4a 337
d9ee843d
WG		 338#ifdef CONFIG_CAN_DRIVER
339/*
340 * Initialize UPMC RAM
341 */
342static void upmc_write (u_char addr, uint val)
343{
f51cdaf1 344 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
d9ee843d
WG		 345
346 out_be32 (&lbc->mdr, val);
347
348 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
349 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
350
351 /* dummy access to perform write */
6d0f6bcf 352 out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
d9ee843d
WG		 353
354 /* normal operation */
355 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
356}
357#endif /* CONFIG_CAN_DRIVER */
358
1287e0c5
WG		 359uint get_lbc_clock (void)
360{
f51cdaf1 361 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
1287e0c5 362 sys_info_t sys_info;
a5d212a2 363 ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
1287e0c5
WG		 364
365 get_sys_info (&sys_info);
366
367 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
368#ifdef CONFIG_MPC8548
369 /*
370 * Yes, the entire PQ38 family use the same
371 * bit-representation for twice the clock divider value.
372 */
373 clkdiv *= 2;
374#endif
375 return sys_info.freqSystemBus / clkdiv;
376 }
377
6d0f6bcf 378 puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
1287e0c5
WG		 379
380 return 0;
381}
382
f5c5ef4a
WD		 383/*
384 * Initialize Local Bus
385 */
f5c5ef4a
WD		 386void local_bus_init (void)
387{
6d0f6bcf 388 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1 389 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
1287e0c5
WG		 390 uint lbc_mhz = get_lbc_clock () / 1000000;
391
392#ifdef CONFIG_MPC8548
393 uint svr = get_svr ();
394 uint lcrr;
395
396 /*
397 * MPC revision < 2.0
398 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
399 * Modify engineering use only register at address 0xE_0F20.
400 * "1. Read register at offset 0xE_0F20
401 * 2. And value with 0x0000_FFFF
402 * 3. OR result with 0x0000_0004
403 * 4. Write result back to offset 0xE_0F20."
404 *
405 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
406 * Modify engineering use only register at address 0xE_0F20.
407 * "1. Read register at offset 0xE_0F20
408 * 2. And value with 0xFFFF_FFDF
409 * 3. Write result back to offset 0xE_0F20."
410 *
411 * Since it is the same register, we do the modification in one step.
412 */
413 if (SVR_MAJ (svr) < 2) {
414 uint dummy = gur->lbiuiplldcr1;
415 dummy &= 0x0000FFDF;
416 dummy |= 0x00000004;
417 gur->lbiuiplldcr1 = dummy;
418 }
f5c5ef4a 419
6d0f6bcf 420 lcrr = CONFIG_SYS_LBC_LCRR;
1287e0c5
WG		 421
422 /*
423 * Local Bus Clock > 83.3 MHz. According to timing
424 * specifications set LCRR[EADC] to 2 delay cycles.
425 */
426 if (lbc_mhz > 83) {
427 lcrr &= ~LCRR_EADC;
428 lcrr |= LCRR_EADC_2;
429 }
430
431 /*
432 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
433 * disable PLL bypass for Local Bus Clock > 83 MHz.
434 */
435 if (lbc_mhz >= 66)
436 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
437
438 else
439 lcrr |= LCRR_DBYP; /* DLL Bypass */
440
441 lbc->lcrr = lcrr;
442 asm ("sync;isync;msync");
443
444 /*
445 * According to MPC8548ERMAD Rev.1.3 read back LCRR
446 * and terminate with isync
447 */
448 lcrr = lbc->lcrr;
449 asm ("isync;");
450
451 /* let DLL stabilize */
452 udelay (500);
453
454#else /* !CONFIG_MPC8548 */
f5c5ef4a
WD		 455
456 /*
457 * Errata LBC11.
458 * Fix Local Bus clock glitch when DLL is enabled.
459 *
8ed44d91
WD		 460 * If localbus freq is < 66MHz, DLL bypass mode must be used.
461 * If localbus freq is > 133MHz, DLL can be safely enabled.
f5c5ef4a
WD		 462 * Between 66 and 133, the DLL is enabled with an override workaround.
463 */
464
1287e0c5 465 if (lbc_mhz < 66) {
6d0f6bcf 466 lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
f2302d44
SR		 467 lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
468 LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
f5c5ef4a 469
1287e0c5 470 } else if (lbc_mhz >= 133) {
6d0f6bcf 471 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 472
473 } else {
474 /*
475 * On REV1 boards, need to change CLKDIV before enable DLL.
476 * Default CLKDIV is 8, change it to 4 temporarily.
477 */
478 uint pvr = get_pvr ();
479 uint temp_lbcdll = 0;
480
481 if (pvr == PVR_85xx_REV1) {
482 /* FIXME: Justify the high bit here. */
483 lbc->lcrr = 0x10000004;
484 }
485
6d0f6bcf 486 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
f5c5ef4a
WD		 487 udelay (200);
488
489 /*
490 * Sample LBC DLL ctrl reg, upshift it to set the
491 * override bits.
492 */
493 temp_lbcdll = gur->lbcdllcr;
494 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
495 asm ("sync;isync;msync");
496 }
1287e0c5 497#endif /* !CONFIG_MPC8548 */
d9ee843d
WG		 498
499#ifdef CONFIG_CAN_DRIVER
500 /*
501 * According to timing specifications EAD must be
502 * set if Local Bus Clock is > 83 MHz.
503 */
1287e0c5 504 if (lbc_mhz > 83)
f51cdaf1 505 set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
d9ee843d 506 else
f51cdaf1
BB		 507 set_lbc_or(2, CONFIG_SYS_OR2_CAN);
508 set_lbc_br(2, CONFIG_SYS_BR2_CAN);
d9ee843d
WG		 509
510 /* LGPL4 is UPWAIT */
511 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
512
513 /* Initialize UPMC for CAN: single read */
514 upmc_write (0x00, 0xFFFFED00);
515 upmc_write (0x01, 0xCCFFCC00);
516 upmc_write (0x02, 0x00FFCF00);
517 upmc_write (0x03, 0x00FFCF00);
518 upmc_write (0x04, 0x00FFDC00);
519 upmc_write (0x05, 0x00FFCF00);
520 upmc_write (0x06, 0x00FFED00);
521 upmc_write (0x07, 0x3FFFCC07);
522
523 /* Initialize UPMC for CAN: single write */
524 upmc_write (0x18, 0xFFFFED00);
525 upmc_write (0x19, 0xCCFFEC00);
526 upmc_write (0x1A, 0x00FFED80);
527 upmc_write (0x1B, 0x00FFED80);
528 upmc_write (0x1C, 0x00FFFC00);
529 upmc_write (0x1D, 0x0FFFEC00);
530 upmc_write (0x1E, 0x0FFFEF00);
531 upmc_write (0x1F, 0x3FFFEC05);
532#endif /* CONFIG_CAN_DRIVER */
f5c5ef4a
WD		 533}
534
f5c5ef4a
WD		 535/*
536 * Initialize PCI Devices, report devices found.
537 */
538
a3182348 539#ifdef CONFIG_PCI1
b9e8078b 540static struct pci_controller pci1_hose;
a3182348 541#endif /* CONFIG_PCI1 */
f5c5ef4a 542
b9e8078b
WG		 543#ifdef CONFIG_PCIE1
544static struct pci_controller pcie1_hose;
545#endif /* CONFIG_PCIE1 */
546
06412756 547void pci_init_board (void)
b9e8078b 548{
06412756
PT		 549 struct fsl_pci_info pci_info[2];
550 int first_free_busno = 0;
551 int num = 0;
552 int pcie_ep;
553 __maybe_unused int pcie_configured;
b9e8078b 554
06412756
PT		 555 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
556 u32 devdisr = in_be32(&gur->devdisr);
557 u32 pordevsr = in_be32(&gur->pordevsr);
558 __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
559 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
b9e8078b 560
06412756
PT		 561#ifdef CONFIG_PCI1
562 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
563 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
b9e8078b 564 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
06412756 565 uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
b9e8078b 566
06412756
PT		 567 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
568 SET_STD_PCI_INFO(pci_info[num], 1);
569 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
8ca78f2c 570 printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
b9e8078b
WG		 571 (pci_32) ? 32 : 64,
572 (pci_speed == 33333333) ? "33" :
573 (pci_speed == 66666666) ? "66" : "unknown",
574 pci_clk_sel ? "sync" : "async",
06412756 575 pcie_ep ? "agent" : "host",
b9e8078b 576 pci_arb ? "arbiter" : "external-arbiter");
06412756
PT		 577 first_free_busno = fsl_pci_init_port(&pci_info[num++],
578 &pci1_hose, first_free_busno);
b9e8078b 579#ifdef CONFIG_PCIX_CHECK
06412756 580 if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
b9e8078b
WG		 581 ushort reg16 =
582 PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
583 PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
06412756 584 uint dev = PCI_BDF(0, 0, 0);
b9e8078b
WG		 585
586 /* PCI-X init */
587 if (CONFIG_SYS_CLK_FREQ < 66000000)
588 puts ("PCI-X will only work at 66 MHz\n");
589
06412756 590 pci_write_config_word(dev, PCIX_COMMAND, reg16);
b9e8078b 591 }
f5c5ef4a 592#endif
b9e8078b 593 } else {
8ca78f2c 594 printf("PCI1: disabled\n");
b9e8078b 595 }
06412756
PT		 596#else
597 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
598#endif
b9e8078b 599
b9e8078b 600#ifdef CONFIG_PCIE1
06412756
PT		 601 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
602
603 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
604 SET_STD_PCIE_INFO(pci_info[num], 1);
605 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
8ca78f2c 606 printf("PCIE1: connected as %s\n",
06412756
PT		 607 pcie_ep ? "Endpoint" : "Root Complex");
608 first_free_busno = fsl_pci_init_port(&pci_info[num++],
609 &pcie1_hose, first_free_busno);
b9e8078b 610 } else {
8ca78f2c 611 printf("PCIE1: disabled\n");
b9e8078b 612 }
06412756
PT		 613#else
614 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
b9e8078b
WG		 615#endif /* CONFIG_PCIE1 */
616}
f5c5ef4a 617
b9e8078b 618#ifdef CONFIG_OF_BOARD_SETUP
25991353
WG		 619void ft_board_setup (void *blob, bd_t *bd)
620{
25991353
WG		 621 ft_cpu_setup (blob, bd);
622
6525d51f 623 FT_FSL_PCI_SETUP;
25991353 624}
b9e8078b 625#endif /* CONFIG_OF_BOARD_SETUP */
25991353 626
bc8bb6d4
WD		 627#ifdef CONFIG_BOARD_EARLY_INIT_R
628int board_early_init_r (void)
629{
630#ifdef CONFIG_PS2MULT
b99ba167 631 ps2mult_early_init ();
bc8bb6d4
WD		 632#endif /* CONFIG_PS2MULT */
633 return (0);
634}
635#endif /* CONFIG_BOARD_EARLY_INIT_R */
10efa024
BW		 636
637int board_eth_init(bd_t *bis)
638{
639 cpu_eth_init(bis); /* Intialize TSECs first */
640 return pci_eth_init(bis);
641}
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