[people/ms/u-boot.git] / board / tqc / tqma6 / tqma6.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
 * Author: Markus Niebel <markus.niebel@tq-group.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
#include <i2c.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>

#include "tqma6_bb.h"

DECLARE_GLOBAL_DATA_PTR;

#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define GPIO_OUT_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

#define GPIO_IN_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)

#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

static const uint16_t tqma6_emmc_dsr = 0x0100;

/* eMMC on USDHCI3 always present */
static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
	NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK,		USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD,		USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6,	USDHC_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7,	USDHC_PAD_CTRL),
	/* eMMC reset */
	NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET,	GPIO_OUT_PAD_CTRL),
};

/*
 * According to board_mmc_init() the following map is done:
 * (U-boot device node)    (Physical Port)
 * mmc0                    eMMC (SD3) on TQMa6
 * mmc1 .. n               optional slots used on baseboard
 */
struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
	.esdhc_base = USDHC3_BASE_ADDR,
	.max_bus_width = 8,
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
		/* eMMC/uSDHC3 is always present */
		ret = 1;
	else
		ret = tqma6_bb_board_mmc_getcd(mmc);

	return ret;
}

int board_mmc_getwp(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
		/* eMMC/uSDHC3 is always present */
		ret = 0;
	else
		ret = tqma6_bb_board_mmc_getwp(mmc);

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
					 ARRAY_SIZE(tqma6_usdhc3_pads));
	tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
		puts("Warning: failed to initialize eMMC dev\n");
	} else {
		struct mmc *mmc = find_mmc_device(0);
		if (mmc)
			mmc_set_dsr(mmc, tqma6_emmc_dsr);
	}

	tqma6_bb_board_mmc_init(bis);

	return 0;
}

static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
	/* SS1 */
	NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
	NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
};

static unsigned const tqma6_ecspi1_cs[] = {
	IMX_GPIO_NR(3, 19),
};

static void tqma6_iomuxc_spi(void)
{
	unsigned i;

	for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
		gpio_direction_output(tqma6_ecspi1_cs[i], 1);
	imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
					 ARRAY_SIZE(tqma6_ecspi1_pads));
}

static struct i2c_pads_info tqma6_i2c3_pads = {
	/* I2C3: on board LM75, M24C64,  */
	.scl = {
		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
					 I2C_PAD_CTRL),
		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
					  I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(1, 5)
	},
	.sda = {
		.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
					 I2C_PAD_CTRL),
		.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
					  I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(1, 6)
	}
};

static void tqma6_setup_i2c(void)
{
	/* use logical index for bus, e.g. I2C1 -> 0 */
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
}

int board_early_init_f(void)
{
	return tqma6_bb_board_early_init_f();
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	tqma6_iomuxc_spi();
	tqma6_setup_i2c();

	tqma6_bb_board_init();

	return 0;
}

static const char *tqma6_get_boardname(void)
{
	u32 cpurev = get_cpu_rev();

	switch ((cpurev & 0xFF000) >> 12) {
	case MXC_CPU_MX6SOLO:
		return "TQMa6S";
		break;
	case MXC_CPU_MX6DL:
		return "TQMa6DL";
		break;
	case MXC_CPU_MX6D:
		return "TQMa6D";
		break;
	case MXC_CPU_MX6Q:
		return "TQMa6Q";
		break;
	default:
		return "??";
	};
}

int board_late_init(void)
{
	struct pmic *p;
	u32 reg;

	setenv("board_name", tqma6_get_boardname());

	/*
	 * configure PFUZE100 PMIC:
	 * TODO: should go to power_init_board if bus switching is
	 * fixed in generic power code
	 */
	power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
	p = pmic_get("PFUZE100");
	if (p && !pmic_probe(p)) {
		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
		printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
	}

	tqma6_bb_board_late_init();

	return 0;
}

int checkboard(void)
{
	printf("Board: %s on a %s\n", tqma6_get_boardname(),
	       tqma6_bb_get_boardname());
	return 0;
}

/*
 * Device Tree Support
 */
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
	/* bring in eMMC dsr settings */
	do_fixup_by_path_u32(blob,
			     "/soc/aips-bus@02100000/usdhc@02198000",
			     "dsr", tqma6_emmc_dsr, 2);
	tqma6_bb_ft_board_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
Commit	Line	Data
cb07d74e MN	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	4	*
	5	* Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
	6	* Author: Markus Niebel <markus.niebel@tq-group.com>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/mx6-pins.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/iomux.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/errno.h>
	17	#include <asm/gpio.h>
	18	#include <asm/io.h>
	19	#include <asm/imx-common/mxc_i2c.h>
	20	#include <common.h>
	21	#include <fsl_esdhc.h>
	22	#include <libfdt.h>
	23	#include <i2c.h>
	24	#include <mmc.h>
	25	#include <power/pfuze100_pmic.h>
	26	#include <power/pmic.h>
	27
	28	#include "tqma6_bb.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	33	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	34
	35	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	36	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	37
	38	#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_LOW \| \
	39	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	40
	41	#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_LOW \| \
	42	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	43
	44	#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	45	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	46
	47	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	48	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	49	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	50
	51	int dram_init(void)
	52	{
	53	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	54
	55	return 0;
	56	}
	57
	58	static const uint16_t tqma6_emmc_dsr = 0x0100;
	59
	60	/* eMMC on USDHCI3 always present */
	61	static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
	62	NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
	63	NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
	64	NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
65	NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
66	NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
67	NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
68	NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
69	NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
70	NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
71	NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
72	/* eMMC reset */
73	NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
74	};
75
76	/*
77	* According to board_mmc_init() the following map is done:
78	* (U-boot device node) (Physical Port)
79	* mmc0 eMMC (SD3) on TQMa6
80	* mmc1 .. n optional slots used on baseboard
81	*/
82	struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
83	.esdhc_base = USDHC3_BASE_ADDR,
84	.max_bus_width = 8,
85	};
86
87	int board_mmc_getcd(struct mmc *mmc)
88	{
89	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
90	int ret = 0;
91
92	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
93	/* eMMC/uSDHC3 is always present */
94	ret = 1;
95	else
96	ret = tqma6_bb_board_mmc_getcd(mmc);
97
98	return ret;
99	}
100
101	int board_mmc_getwp(struct mmc *mmc)
102	{
103	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
104	int ret = 0;
105
106	if (cfg->esdhc_base == USDHC3_BASE_ADDR)
107	/* eMMC/uSDHC3 is always present */
108	ret = 0;
109	else
110	ret = tqma6_bb_board_mmc_getwp(mmc);
111
112	return ret;
113	}
114
115	int board_mmc_init(bd_t *bis)
116	{
117	imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
118	ARRAY_SIZE(tqma6_usdhc3_pads));
119	tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
120	if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
121	puts("Warning: failed to initialize eMMC dev\n");
122	} else {
123	struct mmc *mmc = find_mmc_device(0);
124	if (mmc)
125	mmc_set_dsr(mmc, tqma6_emmc_dsr);
126	}
127
128	tqma6_bb_board_mmc_init(bis);
129
130	return 0;
131	}
132
133	static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
134	/* SS1 */
135	NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
136	NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
137	NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
138	NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
139	};
140
141	static unsigned const tqma6_ecspi1_cs[] = {
142	IMX_GPIO_NR(3, 19),
143	};
144
145	static void tqma6_iomuxc_spi(void)
146	{
147	unsigned i;
148
149	for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
150	gpio_direction_output(tqma6_ecspi1_cs[i], 1);
151	imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
152	ARRAY_SIZE(tqma6_ecspi1_pads));
153	}
154
155	static struct i2c_pads_info tqma6_i2c3_pads = {
156	/* I2C3: on board LM75, M24C64, */
157	.scl = {
158	.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
159	I2C_PAD_CTRL),
160	.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
161	I2C_PAD_CTRL),
162	.gp = IMX_GPIO_NR(1, 5)
163	},
164	.sda = {
165	.i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
166	I2C_PAD_CTRL),
167	.gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
168	I2C_PAD_CTRL),
169	.gp = IMX_GPIO_NR(1, 6)
170	}
171	};
172
173	static void tqma6_setup_i2c(void)
174	{
175	/* use logical index for bus, e.g. I2C1 -> 0 */
176	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
177	}
178
179	int board_early_init_f(void)
180	{
181	return tqma6_bb_board_early_init_f();
182	}
183
184	int board_init(void)
185	{
186	/* address of boot parameters */
187	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
188
189	tqma6_iomuxc_spi();
190	tqma6_setup_i2c();
191
192	tqma6_bb_board_init();
193
194	return 0;
195	}
196
197	static const char *tqma6_get_boardname(void)
198	{
199	u32 cpurev = get_cpu_rev();
200
201	switch ((cpurev & 0xFF000) >> 12) {
202	case MXC_CPU_MX6SOLO:
203	return "TQMa6S";
204	break;
205	case MXC_CPU_MX6DL:
206	return "TQMa6DL";
207	break;
208	case MXC_CPU_MX6D:
209	return "TQMa6D";
210	break;
211	case MXC_CPU_MX6Q:
212	return "TQMa6Q";
213	break;
214	default:
215	return "??";
216	};
217	}
218
219	int board_late_init(void)
220	{
221	struct pmic *p;
222	u32 reg;
223
224	setenv("board_name", tqma6_get_boardname());
225
226	/*
227	* configure PFUZE100 PMIC:
228	* TODO: should go to power_init_board if bus switching is
229	* fixed in generic power code
230	*/
231	power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
676ac24e	232	p = pmic_get("PFUZE100");
cb07d74e MN	233	if (p && !pmic_probe(p)) {
cb07d74e MN	234	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
676ac24e	235	printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
cb07d74e MN	236	}
	237
	238	tqma6_bb_board_late_init();
	239
	240	return 0;
	241	}
	242
	243	int checkboard(void)
	244	{
	245	printf("Board: %s on a %s\n", tqma6_get_boardname(),
	246	tqma6_bb_get_boardname());
	247	return 0;
	248	}
	249
	250	/*
	251	* Device Tree Support
	252	*/
	253	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
	254	void ft_board_setup(void blob, bd_t bd)
	255	{
	256	/* bring in eMMC dsr settings */
	257	do_fixup_by_path_u32(blob,
	258	"/soc/aips-bus@02100000/usdhc@02198000",
	259	"dsr", tqma6_emmc_dsr, 2);
	260	tqma6_bb_ft_board_setup(blob, bd);
	261	}
	262	#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */