[people/ms/u-boot.git] / board / tqm8xx / tqm8xx.c

/*
 * (C) Copyright 2000, 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 * Test TQ ID string (TQM8xx...)
 * If present, check for "L" type (no second DRAM bank),
 * otherwise "L" type is assumed as default.
 *
 * Set board_type to 'L' for "L" type, 0 else.
 */

int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	unsigned char *s = getenv ("serial#");

	puts ("Board: ");

	if (!s || strncmp (s, "TQM8", 4)) {
		puts ("### No HW ID - assuming TQM8xxL\n");
		return (0);
	}

	if ((*(s + 6) == 'L')) {	/* a TQM8xxL type */
		gd->board_type = 'L';
	}

	for (; *s; ++s) {
		if (*s == ' ')
			break;
		putc (*s);
	}
	putc ('\n');

	return (0);
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	long int size_b1 = 0;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;

	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or2 = CFG_OR2_PRELIM;
	memctl->memc_br2 = CFG_BR2_PRELIM;

#ifndef	CONFIG_CAN_DRIVER
	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
		memctl->memc_or3 = CFG_OR3_PRELIM;
		memctl->memc_br3 = CFG_BR3_PRELIM;
	}
#endif							/* CONFIG_CAN_DRIVER */

	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
	udelay (1);

#ifndef	CONFIG_CAN_DRIVER
	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
		udelay (1);
		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
		udelay (1);
	}
#endif							/* CONFIG_CAN_DRIVER */

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
	} else {					/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CFG_MAMR_8COL;
		udelay (500);
/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
	}

#ifndef	CONFIG_CAN_DRIVER
	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
		/*
		 * Check Bank 1 Memory Size
		 * use current column settings
		 * [9 column SDRAM may also be used in 8 column mode,
		 *  but then only half the real size will be used.]
		 */
		size_b1 =
				dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
						   SDRAM_MAX_SIZE);
/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
	} else {
		size_b1 = 0;
	}
#endif							/* CONFIG_CAN_DRIVER */

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping: map bigger bank first
	 */
	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */

		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
		memctl->memc_br3 =
				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

		if (size_b0 > 0) {
			/*
			 * Position Bank 0 immediately above Bank 1
			 */
			memctl->memc_or2 =
					((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
			memctl->memc_br2 =
					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
					+ size_b1;
		} else {
			unsigned long reg;

			/*
			 * No bank 0
			 *
			 * invalidate bank
			 */
			memctl->memc_br2 = 0;

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}

	} else {					/* SDRAM Bank 0 is bigger - map first   */

		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
		memctl->memc_br2 =
				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

		if (size_b1 > 0) {
			/*
			 * Position Bank 1 immediately above Bank 0
			 */
			memctl->memc_or3 =
					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
			memctl->memc_br3 =
					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
					+ size_b0;
		} else {
			unsigned long reg;

#ifndef	CONFIG_CAN_DRIVER
			/*
			 * No bank 1
			 *
			 * invalidate bank
			 */
			memctl->memc_br3 = 0;
#endif							/* CONFIG_CAN_DRIVER */

			/* adjust refresh rate depending on SDRAM type, one bank */
			reg = memctl->memc_mptpr;
			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
			memctl->memc_mptpr = reg;
		}
	}

	udelay (10000);

#ifdef	CONFIG_CAN_DRIVER
	/* Initialize OR3 / BR3 */
	memctl->memc_or3 = CFG_OR3_CAN;
	memctl->memc_br3 = CFG_BR3_CAN;

	/* Initialize MBMR */
	memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */

	/* Initialize UPMB for CAN: single read */
	memctl->memc_mdr = 0xFFFFC004;
	memctl->memc_mcr = 0x0100 | UPMB;

	memctl->memc_mdr = 0x0FFFD004;
	memctl->memc_mcr = 0x0101 | UPMB;

	memctl->memc_mdr = 0x0FFFC000;
	memctl->memc_mcr = 0x0102 | UPMB;

	memctl->memc_mdr = 0x3FFFC004;
	memctl->memc_mcr = 0x0103 | UPMB;

	memctl->memc_mdr = 0xFFFFDC05;
	memctl->memc_mcr = 0x0104 | UPMB;

	/* Initialize UPMB for CAN: single write */
	memctl->memc_mdr = 0xFFFCC004;
	memctl->memc_mcr = 0x0118 | UPMB;

	memctl->memc_mdr = 0xCFFCD004;
	memctl->memc_mcr = 0x0119 | UPMB;

	memctl->memc_mdr = 0x0FFCC000;
	memctl->memc_mcr = 0x011A | UPMB;

	memctl->memc_mdr = 0x7FFCC004;
	memctl->memc_mcr = 0x011B | UPMB;

	memctl->memc_mdr = 0xFFFDCC05;
	memctl->memc_mcr = 0x011C | UPMB;
#endif							/* CONFIG_CAN_DRIVER */

#ifdef	CONFIG_ISP1362_USB
	/* Initialize OR5 / BR5 */
	memctl->memc_or5 = CFG_OR5_ISP1362;
	memctl->memc_br5 = CFG_BR5_ISP1362;
#endif							/* CONFIG_ISP1362_USB */


	return (size_b0 + size_b1);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base,
						   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile long int *addr;
	ulong cnt, val;
	ulong save[32];				/* to make test non-destructive */
	unsigned char i = 0;

	memctl->memc_mamr = mamr_value;

	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
		addr = base + cnt;		/* pointer arith! */

		save[i++] = *addr;
		*addr = ~cnt;
	}

	/* write 0 to base address */
	addr = base;
	save[i] = *addr;
	*addr = 0;

	/* check at base address */
	if ((val = *addr) != 0) {
		*addr = save[i];
		return (0);
	}

	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
		addr = base + cnt;		/* pointer arith! */

		val = *addr;
		*addr = save[--i];

		if (val != (~cnt)) {
			return (cnt * sizeof (long));
		}
	}
	return (maxsize);
}

/* ------------------------------------------------------------------------- */
Commit	Line	Data
f8cac651 WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8xx.h>
	26
	27	/* ------------------------------------------------------------------------- */
	28
	29	static long int dram_size (long int, long int *, long int);
	30
	31	/* ------------------------------------------------------------------------- */
	32
	33	#define _NOT_USED_ 0xFFFFFFFF
	34
	35	const uint sdram_table[] =
	36	{
	37	/*
	38	* Single Read. (Offset 0 in UPMA RAM)
	39	*/
	40	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	41	0x1FF5FC47, /* last */
	42	/*
	43	* SDRAM Initialization (offset 5 in UPMA RAM)
	44	*
	45	* This is no UPM entry point. The following definition uses
	46	* the remaining space to establish an initialization
	47	* sequence, which is executed by a RUN command.
	48	*
	49	*/
	50	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	51	/*
	52	* Burst Read. (Offset 8 in UPMA RAM)
	53	*/
	54	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	55	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	56	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	57	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	58	/*
	59	* Single Write. (Offset 18 in UPMA RAM)
	60	*/
	61	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	62	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	63	/*
	64	* Burst Write. (Offset 20 in UPMA RAM)
65	*/
66	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
67	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
68	_NOT_USED_,
69	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71	/*
72	* Refresh (Offset 30 in UPMA RAM)
73	*/
74	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
75	0xFFFFFC84, 0xFFFFFC07, /* last */
76	_NOT_USED_, _NOT_USED_,
77	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78	/*
79	* Exception. (Offset 3c in UPMA RAM)
80	*/
81	0x7FFFFC07, /* last */
82	_NOT_USED_, _NOT_USED_, _NOT_USED_,
83	};
84
85	/* ------------------------------------------------------------------------- */
86
87
88	/*
89	* Check Board Identity:
90	*
91	* Test TQ ID string (TQM8xx...)
92	* If present, check for "L" type (no second DRAM bank),
93	* otherwise "L" type is assumed as default.
94	*
95	* Set board_type to 'L' for "L" type, 0 else.
96	*/
97
98	int checkboard (void)
99	{
100	DECLARE_GLOBAL_DATA_PTR;
101
102	unsigned char *s = getenv ("serial#");
103
104	puts ("Board: ");
105
106	if (!s \|\| strncmp (s, "TQM8", 4)) {
107	puts ("### No HW ID - assuming TQM8xxL\n");
108	return (0);
109	}
110
111	if (((s + 6) == 'L')) { / a TQM8xxL type */
112	gd->board_type = 'L';
113	}
114
115	for (; *s; ++s) {
116	if (*s == ' ')
117	break;
118	putc (*s);
119	}
120	putc ('\n');
121
122	return (0);
123	}
124
125	/* ------------------------------------------------------------------------- */
126
127	long int initdram (int board_type)
128	{
129	volatile immap_t immap = (immap_t ) CFG_IMMR;
130	volatile memctl8xx_t *memctl = &immap->im_memctl;
131	long int size8, size9;
132	long int size_b0 = 0;
133	long int size_b1 = 0;
134
135	upmconfig (UPMA, (uint *) sdram_table,
136	sizeof (sdram_table) / sizeof (uint));
137
138	/*
139	* Preliminary prescaler for refresh (depends on number of
140	* banks): This value is selected for four cycles every 62.4 us
141	* with two SDRAM banks or four cycles every 31.2 us with one
142	* bank. It will be adjusted after memory sizing.
143	*/
144	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
145
146	/*
147	* The following value is used as an address (i.e. opcode) for
148	* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
149	* the port size is 32bit the SDRAM does NOT "see" the lower two
150	* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
151	* MICRON SDRAMs:
152	* -> 0 00 010 0 010
153	* \| \| \| \| +- Burst Length = 4
154	* \| \| \| +----- Burst Type = Sequential
155	* \| \| +------- CAS Latency = 2
156	* \| +----------- Operating Mode = Standard
157	* +-------------- Write Burst Mode = Programmed Burst Length
158	*/
159	memctl->memc_mar = 0x00000088;
160
161	/*
162	* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
163	* preliminary addresses - these have to be modified after the
164	* SDRAM size has been determined.
165	*/
166	memctl->memc_or2 = CFG_OR2_PRELIM;
167	memctl->memc_br2 = CFG_BR2_PRELIM;
168
169	#ifndef CONFIG_CAN_DRIVER
170	if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
171	memctl->memc_or3 = CFG_OR3_PRELIM;
172	memctl->memc_br3 = CFG_BR3_PRELIM;
173	}
174	#endif /* CONFIG_CAN_DRIVER */
175
176	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
177
178	udelay (200);
179
180	/* perform SDRAM initializsation sequence */
181
182	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
183	udelay (1);
184	memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
185	udelay (1);
186
187	#ifndef CONFIG_CAN_DRIVER
188	if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
189	memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
190	udelay (1);
191	memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
192	udelay (1);
193	}
194	#endif /* CONFIG_CAN_DRIVER */
195
196	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
197
198	udelay (1000);
199
200	/*
201	* Check Bank 0 Memory Size for re-configuration
202	*
203	* try 8 column mode
204	*/
205	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
206	SDRAM_MAX_SIZE);
207
208	udelay (1000);
209
210	/*
211	* try 9 column mode
212	*/
213	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
214	SDRAM_MAX_SIZE);
215
216	if (size8 < size9) { /* leave configuration at 9 columns */
217	size_b0 = size9;
218	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
219	} else { /* back to 8 columns */
220	size_b0 = size8;
221	memctl->memc_mamr = CFG_MAMR_8COL;
222	udelay (500);
223	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
224	}
225
226	#ifndef CONFIG_CAN_DRIVER
227	if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
228	/*
229	* Check Bank 1 Memory Size
230	* use current column settings
231	* [9 column SDRAM may also be used in 8 column mode,
232	* but then only half the real size will be used.]
233	*/
234	size_b1 =
235	dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
236	SDRAM_MAX_SIZE);
237	/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
238	} else {
239	size_b1 = 0;
240	}
241	#endif /* CONFIG_CAN_DRIVER */
242
243	udelay (1000);
244
245	/*
246	* Adjust refresh rate depending on SDRAM type, both banks
247	* For types > 128 MBit leave it at the current (fast) rate
248	*/
249	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
250	/* reduce to 15.6 us (62.4 us / quad) */
251	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
252	udelay (1000);
253	}
254
255	/*
256	* Final mapping: map bigger bank first
257	*/
258	if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
259
260	memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
261	memctl->memc_br3 =
262	(CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
263
264	if (size_b0 > 0) {
265	/*
266	* Position Bank 0 immediately above Bank 1
267	*/
268	memctl->memc_or2 =
269	((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
270	memctl->memc_br2 =
271	((CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V)
272	+ size_b1;
273	} else {
274	unsigned long reg;
275
276	/*
277	* No bank 0
278	*
279	* invalidate bank
280	*/
281	memctl->memc_br2 = 0;
282
283	/* adjust refresh rate depending on SDRAM type, one bank */
284	reg = memctl->memc_mptpr;
285	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
286	memctl->memc_mptpr = reg;
287	}
288
289	} else { /* SDRAM Bank 0 is bigger - map first */
290
291	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
292	memctl->memc_br2 =
293	(CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
294
295	if (size_b1 > 0) {
296	/*
297	* Position Bank 1 immediately above Bank 0
298	*/
299	memctl->memc_or3 =
300	((-size_b1) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
301	memctl->memc_br3 =
302	((CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V)
303	+ size_b0;
304	} else {
305	unsigned long reg;
306
307	#ifndef CONFIG_CAN_DRIVER
308	/*
309	* No bank 1
310	*
311	* invalidate bank
312	*/
313	memctl->memc_br3 = 0;
314	#endif /* CONFIG_CAN_DRIVER */
315
316	/* adjust refresh rate depending on SDRAM type, one bank */
317	reg = memctl->memc_mptpr;
318	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
319	memctl->memc_mptpr = reg;
320	}
321	}
322
323	udelay (10000);
324
325	#ifdef CONFIG_CAN_DRIVER
326	/* Initialize OR3 / BR3 */
327	memctl->memc_or3 = CFG_OR3_CAN;
328	memctl->memc_br3 = CFG_BR3_CAN;
329
330	/* Initialize MBMR */
331	memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
332
333	/* Initialize UPMB for CAN: single read */
334	memctl->memc_mdr = 0xFFFFC004;
335	memctl->memc_mcr = 0x0100 \| UPMB;
336
337	memctl->memc_mdr = 0x0FFFD004;
338	memctl->memc_mcr = 0x0101 \| UPMB;
339
340	memctl->memc_mdr = 0x0FFFC000;
341	memctl->memc_mcr = 0x0102 \| UPMB;
342
343	memctl->memc_mdr = 0x3FFFC004;
344	memctl->memc_mcr = 0x0103 \| UPMB;
345
346	memctl->memc_mdr = 0xFFFFDC05;
347	memctl->memc_mcr = 0x0104 \| UPMB;
348
349	/* Initialize UPMB for CAN: single write */
350	memctl->memc_mdr = 0xFFFCC004;
351	memctl->memc_mcr = 0x0118 \| UPMB;
352
353	memctl->memc_mdr = 0xCFFCD004;
354	memctl->memc_mcr = 0x0119 \| UPMB;
355
356	memctl->memc_mdr = 0x0FFCC000;
357	memctl->memc_mcr = 0x011A \| UPMB;
358
359	memctl->memc_mdr = 0x7FFCC004;
360	memctl->memc_mcr = 0x011B \| UPMB;
361
362	memctl->memc_mdr = 0xFFFDCC05;
363	memctl->memc_mcr = 0x011C \| UPMB;
364	#endif /* CONFIG_CAN_DRIVER */
365
bdccc4fe WD	366	#ifdef CONFIG_ISP1362_USB
	367	/* Initialize OR5 / BR5 */
	368	memctl->memc_or5 = CFG_OR5_ISP1362;
	369	memctl->memc_br5 = CFG_BR5_ISP1362;
	370	#endif /* CONFIG_ISP1362_USB */
42d1f039 WD	371
42d1f039 WD	372
f8cac651 WD	373	return (size_b0 + size_b1);
	374	}
	375
	376	/* ------------------------------------------------------------------------- */
	377
	378	/*
	379	* Check memory range for valid RAM. A simple memory test determines
	380	* the actually available RAM size between addresses `base' and
	381	* `base + maxsize'. Some (not all) hardware errors are detected:
	382	* - short between address lines
	383	* - short between data lines
	384	*/
	385
	386	static long int dram_size (long int mamr_value, long int *base,
	387	long int maxsize)
	388	{
	389	volatile immap_t immap = (immap_t ) CFG_IMMR;
	390	volatile memctl8xx_t *memctl = &immap->im_memctl;
	391	volatile long int *addr;
	392	ulong cnt, val;
	393	ulong save[32]; /* to make test non-destructive */
	394	unsigned char i = 0;
	395
	396	memctl->memc_mamr = mamr_value;
	397
	398	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
	399	addr = base + cnt; /* pointer arith! */
	400
	401	save[i++] = *addr;
	402	*addr = ~cnt;
	403	}
	404
	405	/* write 0 to base address */
	406	addr = base;
	407	save[i] = *addr;
	408	*addr = 0;
	409
	410	/* check at base address */
	411	if ((val = *addr) != 0) {
	412	*addr = save[i];
	413	return (0);
	414	}
	415
	416	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
	417	addr = base + cnt; /* pointer arith! */
	418
	419	val = *addr;
	420	*addr = save[--i];
	421
	422	if (val != (~cnt)) {
	423	return (cnt * sizeof (long));
	424	}
	425	}
	426	return (maxsize);
	427	}
	428
	429	/* ------------------------------------------------------------------------- */