[people/ms/u-boot.git] / board / udoo / udoo.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/sata.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define WDT_EN		IMX_GPIO_NR(5, 4)
#define WDT_TRG		IMX_GPIO_NR(3, 19)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart2_pads[] = {
	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

static iomux_v3_cfg_t const wdog_pads[] = {
	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
};

int mx6_rgmii_rework(struct phy_device *phydev)
{
	/*
	 * Bug: Apparently uDoo does not works with Gigabit switches...
	 * Limiting speed to 10/100Mbps, and setting master mode, seems to
	 * be the only way to have a successfull PHY auto negotiation.
	 * How to fix: Understand why Linux kernel do not have this issue.
	 */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);

	/* control data pad skew - devaddr = 0x02, register = 0x04 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
	return 0;
}

static iomux_v3_cfg_t const enet_pads1[] = {
	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	/* RGMII reset */
	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* Ethernet power supply */
	IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* pin 32 - 1 - (MODE0) all */
	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* pin 31 - 1 - (MODE1) all */
	IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* pin 28 - 1 - (MODE2) all */
	IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* pin 27 - 1 - (MODE3) all */
	IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
	IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const enet_pads2[] = {
	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
};

static void setup_iomux_enet(void)
{
	SETUP_IOMUX_PADS(enet_pads1);
	udelay(20);
	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */

	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */

	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
	udelay(1000);

	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */

	/* Need 100ms delay to exit from reset. */
	udelay(1000 * 100);

	gpio_free(IMX_GPIO_NR(6, 24));
	gpio_free(IMX_GPIO_NR(6, 25));
	gpio_free(IMX_GPIO_NR(6, 27));
	gpio_free(IMX_GPIO_NR(6, 28));
	gpio_free(IMX_GPIO_NR(6, 29));

	SETUP_IOMUX_PADS(enet_pads2);
}

static void setup_iomux_uart(void)
{
	SETUP_IOMUX_PADS(uart2_pads);
}

static void setup_iomux_wdog(void)
{
	SETUP_IOMUX_PADS(wdog_pads);
	gpio_direction_output(WDT_TRG, 0);
	gpio_direction_output(WDT_EN, 1);
	gpio_direction_input(WDT_TRG);
}

static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };

int board_mmc_getcd(struct mmc *mmc)
{
	return 1; /* Always present */
}

int board_eth_init(bd_t *bis)
{
	uint32_t base = IMX_FEC_BASE;
	struct mii_dev *bus = NULL;
	struct phy_device *phydev = NULL;
	int ret;

	setup_iomux_enet();

#ifdef CONFIG_FEC_MXC
	bus = fec_get_miibus(base, -1);
	if (!bus)
		return -EINVAL;
	/* scan phy 4,5,6,7 */
	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);

	if (!phydev) {
		ret = -EINVAL;
		goto free_bus;
	}
	printf("using phy at %d\n", phydev->addr);
	ret  = fec_probe(bis, -1, base, bus, phydev);
	if (ret)
		goto free_phydev;
#endif
	return 0;

free_phydev:
	free(phydev);
free_bus:
	free(bus);
	return ret;
}

int board_mmc_init(bd_t *bis)
{
	SETUP_IOMUX_PADS(usdhc3_pads);
	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	usdhc_cfg.max_bus_width = 4;

	return fsl_esdhc_initialize(bis, &usdhc_cfg);
}

int board_early_init_f(void)
{
	setup_iomux_wdog();
	setup_iomux_uart();

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);
	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_SATA
	if (is_cpu_type(MXC_CPU_MX6Q))
		setup_sata();
#endif
	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (is_cpu_type(MXC_CPU_MX6Q))
		setenv("board_rev", "MX6Q");
	else
		setenv("board_rev", "MX6DL");
#endif
	return 0;
}

int checkboard(void)
{
	if (is_cpu_type(MXC_CPU_MX6Q))
		puts("Board: Udoo Quad\n");
	else
		puts("Board: Udoo DualLite\n");

	return 0;
}
Commit	Line	Data
0c5e2667 FE	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/iomux.h>
078813d2	12	#include <malloc.h>
0c5e2667	13	#include <asm/arch/mx6-pins.h>
1221ce45	14	#include <linux/errno.h>
0c5e2667 FE	15	#include <asm/gpio.h>
0c5e2667 FE	16	#include <asm/imx-common/iomux-v3.h>
98d01229	17	#include <asm/imx-common/sata.h>
0c5e2667 FE	18	#include <mmc.h>
	19	#include <fsl_esdhc.h>
	20	#include <asm/arch/crm_regs.h>
	21	#include <asm/io.h>
	22	#include <asm/arch/sys_proto.h>
078813d2 GP	23	#include <micrel.h>
	24	#include <miiphy.h>
	25	#include <netdev.h>
0c5e2667 FE	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	30	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	31	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	32
078813d2 GP	33	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	34	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	35
0c5e2667 FE	36	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	37	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	38	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	39
	40	#define WDT_EN IMX_GPIO_NR(5, 4)
	41	#define WDT_TRG IMX_GPIO_NR(3, 19)
	42
	43	int dram_init(void)
	44	{
78506c2f	45	gd->ram_size = imx_ddr_size();
0c5e2667 FE	46
	47	return 0;
	48	}
	49
	50	static iomux_v3_cfg_t const uart2_pads[] = {
78506c2f	51	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
78506c2f	52	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
0c5e2667 FE	53	};
	54
	55	static iomux_v3_cfg_t const usdhc3_pads[] = {
78506c2f	56	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	57	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	58	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	59	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	60	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	61	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
0c5e2667 FE	62	};
	63
	64	static iomux_v3_cfg_t const wdog_pads[] = {
78506c2f	65	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
78506c2f	66	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
0c5e2667 FE	67	};
0c5e2667 FE	68
078813d2 GP	69	int mx6_rgmii_rework(struct phy_device *phydev)
	70	{
	71	/*
	72	* Bug: Apparently uDoo does not works with Gigabit switches...
	73	* Limiting speed to 10/100Mbps, and setting master mode, seems to
	74	* be the only way to have a successfull PHY auto negotiation.
	75	* How to fix: Understand why Linux kernel do not have this issue.
	76	*/
	77	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
	78
	79	/* control data pad skew - devaddr = 0x02, register = 0x04 */
	80	ksz9031_phy_extended_write(phydev, 0x02,
	81	MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
	82	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	83	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
	84	ksz9031_phy_extended_write(phydev, 0x02,
	85	MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
	86	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	87	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
	88	ksz9031_phy_extended_write(phydev, 0x02,
	89	MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
	90	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	91	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
	92	ksz9031_phy_extended_write(phydev, 0x02,
	93	MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
	94	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
	95	return 0;
	96	}
	97
	98	static iomux_v3_cfg_t const enet_pads1[] = {
78506c2f	99	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	100	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	101	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	102	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	103	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	104	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	105	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	106	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	107	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	108	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
078813d2	109	/* RGMII reset */
78506c2f	110	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	111	/* Ethernet power supply */
78506c2f	112	IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	113	/* pin 32 - 1 - (MODE0) all */
78506c2f	114	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	115	/* pin 31 - 1 - (MODE1) all */
78506c2f	116	IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	117	/* pin 28 - 1 - (MODE2) all */
78506c2f	118	IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	119	/* pin 27 - 1 - (MODE3) all */
78506c2f	120	IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2	121	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
78506c2f	122	IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
078813d2 GP	123	};
	124
	125	static iomux_v3_cfg_t const enet_pads2[] = {
78506c2f	126	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	127	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	128	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	129	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	130	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
078813d2 GP	131	};
	132
	133	static void setup_iomux_enet(void)
	134	{
78506c2f	135	SETUP_IOMUX_PADS(enet_pads1);
078813d2 GP	136	udelay(20);
	137	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
	138
	139	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
	140
	141	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
	142	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
	143	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
	144	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
	145	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
	146	udelay(1000);
	147
	148	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
	149
	150	/* Need 100ms delay to exit from reset. */
	151	udelay(1000 * 100);
	152
	153	gpio_free(IMX_GPIO_NR(6, 24));
	154	gpio_free(IMX_GPIO_NR(6, 25));
	155	gpio_free(IMX_GPIO_NR(6, 27));
	156	gpio_free(IMX_GPIO_NR(6, 28));
	157	gpio_free(IMX_GPIO_NR(6, 29));
	158
78506c2f	159	SETUP_IOMUX_PADS(enet_pads2);
078813d2 GP	160	}
078813d2 GP	161
0c5e2667 FE	162	static void setup_iomux_uart(void)
0c5e2667 FE	163	{
78506c2f	164	SETUP_IOMUX_PADS(uart2_pads);
0c5e2667 FE	165	}
	166
	167	static void setup_iomux_wdog(void)
	168	{
78506c2f	169	SETUP_IOMUX_PADS(wdog_pads);
0c5e2667 FE	170	gpio_direction_output(WDT_TRG, 0);
0c5e2667 FE	171	gpio_direction_output(WDT_EN, 1);
db6801de	172	gpio_direction_input(WDT_TRG);
0c5e2667 FE	173	}
	174
	175	static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
	176
	177	int board_mmc_getcd(struct mmc *mmc)
	178	{
	179	return 1; /* Always present */
	180	}
	181
078813d2 GP	182	int board_eth_init(bd_t *bis)
	183	{
	184	uint32_t base = IMX_FEC_BASE;
	185	struct mii_dev *bus = NULL;
	186	struct phy_device *phydev = NULL;
	187	int ret;
	188
	189	setup_iomux_enet();
	190
	191	#ifdef CONFIG_FEC_MXC
	192	bus = fec_get_miibus(base, -1);
	193	if (!bus)
84c311f2	194	return -EINVAL;
078813d2 GP	195	/* scan phy 4,5,6,7 */
	196	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
	197
	198	if (!phydev) {
84c311f2 FE	199	ret = -EINVAL;
84c311f2 FE	200	goto free_bus;
078813d2 GP	201	}
	202	printf("using phy at %d\n", phydev->addr);
	203	ret = fec_probe(bis, -1, base, bus, phydev);
84c311f2 FE	204	if (ret)
84c311f2 FE	205	goto free_phydev;
078813d2 GP	206	#endif
078813d2 GP	207	return 0;
84c311f2 FE	208
	209	free_phydev:
	210	free(phydev);
	211	free_bus:
	212	free(bus);
	213	return ret;
078813d2 GP	214	}
078813d2 GP	215
0c5e2667 FE	216	int board_mmc_init(bd_t *bis)
0c5e2667 FE	217	{
78506c2f	218	SETUP_IOMUX_PADS(usdhc3_pads);
0c5e2667 FE	219	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	220	usdhc_cfg.max_bus_width = 4;
	221
	222	return fsl_esdhc_initialize(bis, &usdhc_cfg);
	223	}
	224
	225	int board_early_init_f(void)
	226	{
	227	setup_iomux_wdog();
	228	setup_iomux_uart();
	229
	230	return 0;
	231	}
	232
078813d2 GP	233	int board_phy_config(struct phy_device *phydev)
	234	{
	235	mx6_rgmii_rework(phydev);
	236	if (phydev->drv->config)
	237	phydev->drv->config(phydev);
	238
	239	return 0;
	240	}
	241
0c5e2667 FE	242	int board_init(void)
	243	{
	244	/* address of boot parameters */
	245	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	246
10e40d54	247	#ifdef CONFIG_SATA
78506c2f	248	if (is_cpu_type(MXC_CPU_MX6Q))
	249	setup_sata();
	250	#endif
	251	return 0;
	252	}
	253
	254	int board_late_init(void)
	255	{
	256	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	257	if (is_cpu_type(MXC_CPU_MX6Q))
	258	setenv("board_rev", "MX6Q");
	259	else
	260	setenv("board_rev", "MX6DL");
98d01229	261	#endif
0c5e2667 FE	262	return 0;
	263	}
	264
	265	int checkboard(void)
	266	{
78506c2f	267	if (is_cpu_type(MXC_CPU_MX6Q))
	268	puts("Board: Udoo Quad\n");
	269	else
	270	puts("Board: Udoo DualLite\n");
0c5e2667 FE	271
	272	return 0;
	273	}