[people/ms/u-boot.git] / board / v38b / v38b.c

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <asm/processor.h>


#ifndef CFG_RAMBOOT
static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif /* SDRAM_DDR */

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif /* !CFG_RAMBOOT */


phys_size_t initdram(int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;

#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif /* SDRAM_DDR */

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else
		dramsize = test2;

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0)
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	else
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else
		dramsize2 = test2;

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20))
		dramsize2 = 0;

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0)
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	else
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */

#else /* CFG_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13)
		dramsize = (1 << (dramsize - 0x13)) << 20;
	else
		dramsize = 0;

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13)
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	else
		dramsize2 = 0;

#endif /* CFG_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) &&
		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {

		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
		__asm__ volatile ("sync");
	}

	return dramsize + dramsize2;
}


int checkboard (void)
{
	puts("Board: MarelV38B\n");
	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_HW_WATCHDOG
	/*
	 * Enable and configure the direction (output) of PSC3_9 - watchdog
	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
	 * Manual.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
#endif /* CONFIG_HW_WATCHDOG */
	return 0;
}

int board_early_init_r(void)
{
	/*
	 * Now, when we are in RAM, enable flash write access for the
	 * detection process.  Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */

	/*
	 * Enable GPIO_WKUP_7 to "read the status of the actual power
	 * situation". Default direction is input, so no need to set it
	 * explicitly.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
	return 0;
}


#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset(void)
{
	debug("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
	/* Deassert reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}


void ide_set_reset(int idereset)
{
	debug("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
		/* Make a delay. MPC5200 spec says 25 usec min */
		udelay(500000);
	} else
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
}
#endif


#ifdef CONFIG_HW_WATCHDOG
void hw_watchdog_reset(void)
{
	/*
	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
}
#endif /* CONFIG_HW_WATCHDOG */
Commit	Line	Data
4707fb50 BS	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
	29	#include <asm/processor.h>
	30
25721b5c	31
4707fb50 BS	32	#ifndef CFG_RAMBOOT
	33	static void sdram_start(int hi_addr)
	34	{
	35	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	36
	37	/* unlock mode register */
25721b5c	38	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
4707fb50 BS	39	__asm__ volatile ("sync");
	40
	41	/* precharge all banks */
25721b5c	42	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
4707fb50 BS	43	__asm__ volatile ("sync");
	44
	45	#if SDRAM_DDR
	46	/* set mode register: extended mode */
25721b5c	47	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
4707fb50 BS	48	__asm__ volatile ("sync");
	49
	50	/* set mode register: reset DLL */
25721b5c	51	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
4707fb50 BS	52	__asm__ volatile ("sync");
	53	#endif /* SDRAM_DDR */
	54
	55	/* precharge all banks */
25721b5c	56	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
4707fb50 BS	57	__asm__ volatile ("sync");
	58
	59	/* auto refresh */
25721b5c	60	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
4707fb50 BS	61	__asm__ volatile ("sync");
	62
	63	/* set mode register */
25721b5c	64	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
4707fb50 BS	65	__asm__ volatile ("sync");
	66
	67	/* normal operation */
25721b5c	68	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
4707fb50 BS	69	__asm__ volatile ("sync");
	70	}
	71	#endif /* !CFG_RAMBOOT */
	72
	73
9973e3c6	74	phys_size_t initdram(int board_type)
4707fb50 BS	75	{
	76	ulong dramsize = 0;
	77	ulong dramsize2 = 0;
	78	uint svr, pvr;
	79
	80	#ifndef CFG_RAMBOOT
	81	ulong test1, test2;
	82
	83	/* setup SDRAM chip selects */
25721b5c BS	84	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
25721b5c BS	85	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
4707fb50 BS	86	__asm__ volatile ("sync");
	87
	88	/* setup config registers */
25721b5c BS	89	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
25721b5c BS	90	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
4707fb50 BS	91	__asm__ volatile ("sync");
	92
	93	#if SDRAM_DDR
	94	/* set tap delay */
25721b5c	95	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
4707fb50 BS	96	__asm__ volatile ("sync");
	97	#endif /* SDRAM_DDR */
	98
	99	/* find RAM size using SDRAM CS0 only */
	100	sdram_start(0);
	101	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	102	sdram_start(1);
	103	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	104	if (test1 > test2) {
	105	sdram_start(0);
	106	dramsize = test1;
	107	} else
	108	dramsize = test2;
	109
	110	/* memory smaller than 1MB is impossible */
	111	if (dramsize < (1 << 20))
	112	dramsize = 0;
	113
	114	/* set SDRAM CS0 size according to the amount of RAM found */
	115	if (dramsize > 0)
25721b5c	116	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
4707fb50	117	else
25721b5c	118	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
4707fb50 BS	119
4707fb50 BS	120	/* let SDRAM CS1 start right after CS0 */
25721b5c	121	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
4707fb50 BS	122
	123	/* find RAM size using SDRAM CS1 only */
	124	if (!dramsize)
	125	sdram_start(0);
25721b5c	126	test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
4707fb50 BS	127	if (!dramsize) {
4707fb50 BS	128	sdram_start(1);
25721b5c	129	test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
4707fb50 BS	130	}
	131	if (test1 > test2) {
	132	sdram_start(0);
	133	dramsize2 = test1;
	134	} else
	135	dramsize2 = test2;
	136
	137	/* memory smaller than 1MB is impossible */
	138	if (dramsize2 < (1 << 20))
	139	dramsize2 = 0;
	140
	141	/* set SDRAM CS1 size according to the amount of RAM found */
	142	if (dramsize2 > 0)
25721b5c	143	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize
4707fb50 BS	144	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
4707fb50 BS	145	else
25721b5c	146	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
4707fb50 BS	147
	148	#else /* CFG_RAMBOOT */
	149
	150	/* retrieve size of memory connected to SDRAM CS0 */
25721b5c	151	dramsize = (vu_long ) MPC5XXX_SDRAM_CS0CFG & 0xFF;
4707fb50 BS	152	if (dramsize >= 0x13)
	153	dramsize = (1 << (dramsize - 0x13)) << 20;
	154	else
	155	dramsize = 0;
	156
	157	/* retrieve size of memory connected to SDRAM CS1 */
25721b5c	158	dramsize2 = (vu_long ) MPC5XXX_SDRAM_CS1CFG & 0xFF;
4707fb50 BS	159	if (dramsize2 >= 0x13)
	160	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	161	else
	162	dramsize2 = 0;
	163
	164	#endif /* CFG_RAMBOOT */
	165
	166	/*
	167	* On MPC5200B we need to set the special configuration delay in the
	168	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	169	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	170	*
	171	* "The SDelay should be written to a value of 0x00000004. It is
	172	* required to account for changes caused by normal wafer processing
	173	* parameters."
	174	*/
	175	svr = get_svr();
	176	pvr = get_pvr();
	177	if ((SVR_MJREV(svr) >= 2) &&
	178	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	179
25721b5c	180	(vu_long ) MPC5XXX_SDRAM_SDELAY = 0x04;
4707fb50 BS	181	__asm__ volatile ("sync");
	182	}
	183
	184	return dramsize + dramsize2;
	185	}
	186
	187
	188	int checkboard (void)
	189	{
	190	puts("Board: MarelV38B\n");
	191	return 0;
	192	}
	193
cce4acbb	194	int board_early_init_f(void)
4707fb50	195	{
25721b5c BS	196	#ifdef CONFIG_HW_WATCHDOG
	197	/*
	198	* Enable and configure the direction (output) of PSC3_9 - watchdog
	199	* reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
	200	* Manual.
	201	*/
	202	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC3_9;
	203	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC3_9;
	204	#endif /* CONFIG_HW_WATCHDOG */
cce4acbb BS	205	return 0;
	206	}
	207
	208	int board_early_init_r(void)
	209	{
	210	/*
	211	* Now, when we are in RAM, enable flash write access for the
	212	* detection process. Note that CS_BOOT cannot be cleared when
	213	* executing in flash.
	214	*/
	215	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
25721b5c BS	216
	217	/*
	218	* Enable GPIO_WKUP_7 to "read the status of the actual power
	219	* situation". Default direction is input, so no need to set it
	220	* explicitly.
4707fb50	221	*/
25721b5c	222	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WKUP_7;
4707fb50 BS	223	return 0;
	224	}
	225
	226
d39b5741	227	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
4707fb50 BS	228	void init_ide_reset(void)
	229	{
	230	debug("init_ide_reset\n");
	231
	232	/* Configure PSC1_4 as GPIO output for ATA reset */
	233	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
25721b5c	234	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
4707fb50	235	/* Deassert reset */
25721b5c	236	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
4707fb50 BS	237	}
	238
	239
	240	void ide_set_reset(int idereset)
	241	{
	242	debug("ide_reset(%d)\n", idereset);
	243
	244	if (idereset) {
25721b5c	245	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
4707fb50 BS	246	/* Make a delay. MPC5200 spec says 25 usec min */
	247	udelay(500000);
	248	} else
25721b5c	249	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
4707fb50	250	}
d39b5741	251	#endif
4707fb50 BS	252
4707fb50 BS	253
25721b5c	254	#ifdef CONFIG_HW_WATCHDOG
4707fb50 BS	255	void hw_watchdog_reset(void)
4707fb50 BS	256	{
25721b5c BS	257	/*
	258	* MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
	259	* we need a positive or negative transition on WDI i.e., our PSC3_9.
	260	*/
	261	(vu_long ) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
4707fb50	262	}
25721b5c	263	#endif /* CONFIG_HW_WATCHDOG */