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PXA: Add necessary information for RELOC
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18a00dfd 1/*
f905432c 2 * Voipac PXA270 Support
18a00dfd 3 *
f905432c 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
18a00dfd
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5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <common.h>
23#include <asm/arch/hardware.h>
c7e61334 24#include <netdev.h>
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25#include <serial.h>
26#include <asm/io.h>
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27
28DECLARE_GLOBAL_DATA_PTR;
29
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30/*
31 * Miscelaneous platform dependent initialisations
32 */
f905432c 33int board_init(void)
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34{
35 /* memory and cpu-speed are setup before relocation */
36 /* so we do _nothing_ here */
37
f905432c 38 /* Arch number of vpac270 */
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39 gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
40
41 /* adress of boot parameters */
42 gd->bd->bi_boot_params = 0xa0000100;
43
44 return 0;
45}
46
f905432c 47struct serial_device *default_serial_console(void)
18a00dfd 48{
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49 return &serial_ffuart_device;
50}
18a00dfd 51
6ef6eb91 52
f905432c 53int dram_init(void)
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54{
55 gd->ram_size = PHYS_SDRAM_1_SIZE;
56#ifdef CONFIG_256M_U_BOOT
57 gd->ram_size += PHYS_SDRAM_2_SIZE;
58#endif
59 return 0;
60}
61
62void dram_init_banksize(void)
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63{
64 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
18a00dfd 65 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
18a00dfd 66
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67#ifdef CONFIG_256M_U_BOOT
68 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
69 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
70#endif
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71}
72
f905432c 73#ifdef CONFIG_CMD_USB
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74int usb_board_init(void)
75{
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76 writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
77 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
78 UHCHR);
18a00dfd 79
3ba8bf7c 80 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
18a00dfd 81
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82 while (readl(UHCHR) & UHCHR_FSBIR)
83 ;
18a00dfd 84
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85 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
86 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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87
88 /* Clear any OTG Pin Hold */
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89 if (readl(PSSR) & PSSR_OTGPH)
90 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
18a00dfd 91
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92 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
93 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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94
95 /* Set port power control mask bits, only 3 ports. */
3ba8bf7c 96 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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97
98 /* enable port 2 */
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99 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
100 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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101
102 return 0;
103}
104
105void usb_board_init_fail(void)
106{
107 return;
108}
109
110void usb_board_stop(void)
111{
3ba8bf7c 112 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
18a00dfd 113 udelay(11);
3ba8bf7c 114 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
18a00dfd 115
3ba8bf7c 116 writel(readl(UHCCOMS) | 1, UHCCOMS);
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117 udelay(10);
118
3ba8bf7c 119 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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120
121 return;
122}
f905432c 123#endif
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124
125#ifdef CONFIG_DRIVER_DM9000
126int board_eth_init(bd_t *bis)
127{
128 return dm9000_initialize(bis);
129}
130#endif