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18a00dfd | 1 | /* |
f905432c | 2 | * Voipac PXA270 Support |
18a00dfd | 3 | * |
f905432c | 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
18a00dfd MV |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <common.h> | |
23 | #include <asm/arch/hardware.h> | |
c7e61334 | 24 | #include <netdev.h> |
3ba8bf7c MV |
25 | #include <serial.h> |
26 | #include <asm/io.h> | |
18a00dfd MV |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
18a00dfd MV |
30 | /* |
31 | * Miscelaneous platform dependent initialisations | |
32 | */ | |
f905432c | 33 | int board_init(void) |
18a00dfd | 34 | { |
720a650c MV |
35 | /* We have RAM, disable cache */ |
36 | dcache_disable(); | |
37 | icache_disable(); | |
38 | ||
18a00dfd MV |
39 | /* memory and cpu-speed are setup before relocation */ |
40 | /* so we do _nothing_ here */ | |
41 | ||
f905432c | 42 | /* Arch number of vpac270 */ |
18a00dfd MV |
43 | gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
44 | ||
45 | /* adress of boot parameters */ | |
46 | gd->bd->bi_boot_params = 0xa0000100; | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
f905432c | 51 | struct serial_device *default_serial_console(void) |
18a00dfd | 52 | { |
f905432c MV |
53 | return &serial_ffuart_device; |
54 | } | |
18a00dfd | 55 | |
720a650c | 56 | extern void pxa_dram_init(void); |
f905432c | 57 | int dram_init(void) |
6ef6eb91 | 58 | { |
720a650c | 59 | pxa_dram_init(); |
6ef6eb91 | 60 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
6ef6eb91 MV |
61 | return 0; |
62 | } | |
63 | ||
64 | void dram_init_banksize(void) | |
f905432c MV |
65 | { |
66 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
18a00dfd | 67 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
18a00dfd | 68 | |
f97e9c65 | 69 | #ifdef CONFIG_RAM_256M |
f905432c MV |
70 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
71 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
72 | #endif | |
18a00dfd MV |
73 | } |
74 | ||
f905432c | 75 | #ifdef CONFIG_CMD_USB |
18a00dfd MV |
76 | int usb_board_init(void) |
77 | { | |
3ba8bf7c MV |
78 | writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
79 | ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), | |
80 | UHCHR); | |
18a00dfd | 81 | |
3ba8bf7c | 82 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
18a00dfd | 83 | |
3ba8bf7c MV |
84 | while (readl(UHCHR) & UHCHR_FSBIR) |
85 | ; | |
18a00dfd | 86 | |
3ba8bf7c MV |
87 | writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
88 | writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); | |
18a00dfd MV |
89 | |
90 | /* Clear any OTG Pin Hold */ | |
3ba8bf7c MV |
91 | if (readl(PSSR) & PSSR_OTGPH) |
92 | writel(readl(PSSR) | PSSR_OTGPH, PSSR); | |
18a00dfd | 93 | |
3ba8bf7c MV |
94 | writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); |
95 | writel(readl(UHCRHDA) | 0x100, UHCRHDA); | |
18a00dfd MV |
96 | |
97 | /* Set port power control mask bits, only 3 ports. */ | |
3ba8bf7c | 98 | writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
18a00dfd MV |
99 | |
100 | /* enable port 2 */ | |
3ba8bf7c MV |
101 | writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | |
102 | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); | |
18a00dfd MV |
103 | |
104 | return 0; | |
105 | } | |
106 | ||
107 | void usb_board_init_fail(void) | |
108 | { | |
109 | return; | |
110 | } | |
111 | ||
112 | void usb_board_stop(void) | |
113 | { | |
3ba8bf7c | 114 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
18a00dfd | 115 | udelay(11); |
3ba8bf7c | 116 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
18a00dfd | 117 | |
3ba8bf7c | 118 | writel(readl(UHCCOMS) | 1, UHCCOMS); |
18a00dfd MV |
119 | udelay(10); |
120 | ||
3ba8bf7c | 121 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
18a00dfd MV |
122 | |
123 | return; | |
124 | } | |
f905432c | 125 | #endif |
18a00dfd MV |
126 | |
127 | #ifdef CONFIG_DRIVER_DM9000 | |
128 | int board_eth_init(bd_t *bis) | |
129 | { | |
130 | return dm9000_initialize(bis); | |
131 | } | |
132 | #endif |