[people/ms/u-boot.git] / board / vscom / baltos / board.c

/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN		7
#define DIP_S1			44

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

static int baltos_set_console(void)
{
	int val, i, dips = 0;
	char buf[7];

	for (i = 0; i < 4; i++) {
		sprintf(buf, "dip_s%d", i + 1);

		if (gpio_request(DIP_S1 + i, buf)) {
			printf("failed to export GPIO %d\n", DIP_S1 + i);
			return 0;
		}

		if (gpio_direction_input(DIP_S1 + i)) {
			printf("failed to set GPIO %d direction\n", DIP_S1 + i);
			return 0;
		}

		val = gpio_get_value(DIP_S1 + i);
		dips |= val << i;
	}

	printf("DIPs: 0x%1x\n", (~dips) & 0xf);

	if ((dips & 0xf) == 0xe)
		setenv("console", "ttyUSB0,115200n8");

	return 0;
}

static int read_eeprom(BSP_VS_HWPARAM *header)
{
	i2c_set_bus_num(1);

	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally "
			"wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
		     sizeof(BSP_VS_HWPARAM))) {
		puts("Could not read the EEPROM; something fundamentally"
			" wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header->Magic != 0xDEADBEEF) {

		printf("Incorrect magic number (0x%x) in EEPROM\n",
				header->Magic);

		/* fill default values */
		header->SystemId = 211;
		header->MAC1[0] = 0x00;
		header->MAC1[1] = 0x00;
		header->MAC1[2] = 0x00;
		header->MAC1[3] = 0x00;
		header->MAC1[4] = 0x00;
		header->MAC1[5] = 0x01;

		header->MAC2[0] = 0x00;
		header->MAC2[1] = 0x00;
		header->MAC2[2] = 0x00;
		header->MAC2[3] = 0x00;
		header->MAC2[4] = 0x00;
		header->MAC2[5] = 0x02;

		header->MAC3[0] = 0x00;
		header->MAC3[1] = 0x00;
		header->MAC3[2] = 0x00;
		header->MAC3[3] = 0x00;
		header->MAC3[4] = 0x00;
		header->MAC3[5] = 0x03;
	}

	return 0;
}

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)

static const struct ddr_data ddr3_baltos_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static struct emif_regs ddr3_baltos_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	return (serial_tstc() && serial_getc() == 'c');
}
#endif

#define OSC	(V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
		266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
		303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_baltos = {
		400, OSC-1, 1, -1, -1, -1, -1};

void am33xx_spl_board_init(void)
{
	int mpu_vdd;
	int sil_rev;

	/* Get the frequency */
	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);

	/*
	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
	 * MPU frequencies we support we use a CORE voltage of
	 * 1.1375V.  For MPU voltage we need to switch based on
	 * the frequency we are running at.
	 */
	i2c_set_bus_num(1);

	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);

	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
		puts("i2c: cannot access TPS65910\n");
		return;
	}

	/*
	 * Depending on MPU clock and PG we will need a different
	 * VDD to drive at that speed.
	 */
	sil_rev = readl(&cdev->deviceid) >> 28;
	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
					      dpll_mpu_opp100.m);

	/* Tell the TPS65910 to use i2c */
	tps65910_set_i2c_control();

	/* First update MPU voltage. */
	if (tps65910_voltage_update(MPU, mpu_vdd))
		return;

	/* Second, update the CORE voltage. */
	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
		return;

	/* Set CORE Frequencies to OPP100 */
	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);

	/* Set MPU Frequency to what we detected now that voltages are set */
	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);

	writel(0x000010ff, PRM_DEVICE_INST + 4);
}

const struct dpll_params *get_dpll_ddr_params(void)
{
	enable_i2c1_pin_mux();
	i2c_set_bus_num(1);

	return &dpll_ddr_baltos;
}

void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_board_pin_mux();
}

const struct ctrl_ioregs ioregs_baltos = {
	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
};

void sdram_init(void)
{
	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	gpio_direction_output(GPIO_DDR_VTT_EN, 1);

	config_ddr(400, &ioregs_baltos,
		   &ddr3_baltos_data,
		   &ddr3_baltos_cmd_ctrl_data,
		   &ddr3_baltos_emif_reg_data, 0);
}
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
	hw_watchdog_init();
#endif

	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
	gpmc_init();
#endif
	return 0;
}

int ft_board_setup(void *blob, bd_t *bd)
{
	int node, ret;
	unsigned char mac_addr[6];
	BSP_VS_HWPARAM header;

	/* get production data */
	if (read_eeprom(&header))
		return 0;

	/* setup MAC1 */
	mac_addr[0] = header.MAC1[0];
	mac_addr[1] = header.MAC1[1];
	mac_addr[2] = header.MAC1[2];
	mac_addr[3] = header.MAC1[3];
	mac_addr[4] = header.MAC1[4];
	mac_addr[5] = header.MAC1[5];


	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
	if (node < 0) {
		printf("no /soc/fman/ethernet path offset\n");
		return -ENODEV;
	}

	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
	if (ret) {
		printf("error setting local-mac-address property\n");
		return -ENODEV;
	}

	/* setup MAC2 */
	mac_addr[0] = header.MAC2[0];
	mac_addr[1] = header.MAC2[1];
	mac_addr[2] = header.MAC2[2];
	mac_addr[3] = header.MAC2[3];
	mac_addr[4] = header.MAC2[4];
	mac_addr[5] = header.MAC2[5];

	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
	if (node < 0) {
		printf("no /soc/fman/ethernet path offset\n");
		return -ENODEV;
	}

	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
	if (ret) {
		printf("error setting local-mac-address property\n");
		return -ENODEV;
	}

	printf("\nFDT was successfully setup\n");

	return 0;
}

static struct module_pin_mux dip_pin_mux[] = {
	{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},	/* GPIO1_12 */
	{OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},	/* GPIO1_13 */
	{OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},	/* GPIO1_14 */
	{OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},	/* GPIO1_15 */
	{-1},
};

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	BSP_VS_HWPARAM header;
	char model[4];

	/* get production data */
	if (read_eeprom(&header)) {
		strcpy(model, "211");
	} else {
		sprintf(model, "%d", header.SystemId);
		if (header.SystemId == 215) {
			configure_module_pin_mux(dip_pin_mux);
			baltos_set_console();
		}
	}
	setenv("board_name", model);
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 7,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 2,
	.slave_data		= cpsw_slaves,
	.active_slave		= 1,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
		&& defined(CONFIG_SPL_BUILD)) || \
	((defined(CONFIG_DRIVER_TI_CPSW) || \
	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
	 !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;
	__maybe_unused struct am335x_baseboard_id header;

	/*
	 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
	 * CSPW0 has a 100Mbit PHY.
	 *
	 * On product, CPSW1 maps to port labeled WAN.
	 */

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid1l);
	mac_hi = readl(&cdev->macid1h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

#ifdef CONFIG_DRIVER_TI_CPSW
	writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
#endif

	/*
	 *
	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
	 * operating points.  So we must set the TX clock delay feature
	 * in the AR8051 PHY.  Since we only support a single ethernet
	 * device in U-Boot, we only do this for the first instance.
	 */
#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
#define AR8051_PHY_DEBUG_DATA_REG	0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
#define AR8051_RGMII_TX_CLK_DLY		0x100
	const char *devname;
	devname = miiphy_get_current_dev();

	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
			AR8051_DEBUG_RGMII_CLK_DLY_REG);
	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
			AR8051_RGMII_TX_CLK_DLY);
#endif
	return n;
}
#endif
Commit	Line	Data
6ce89324 YY	1	/*
	2	* board.c
	3	*
	4	* Board functions for TI AM335X based boards
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <errno.h>
73223f0e	13	#include <libfdt.h>
6ce89324 YY	14	#include <spl.h>
	15	#include <asm/arch/cpu.h>
	16	#include <asm/arch/hardware.h>
	17	#include <asm/arch/omap.h>
	18	#include <asm/arch/ddr_defs.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/gpio.h>
	21	#include <asm/arch/mmc_host_def.h>
	22	#include <asm/arch/sys_proto.h>
	23	#include <asm/arch/mem.h>
	24	#include <asm/arch/mux.h>
	25	#include <asm/io.h>
	26	#include <asm/emif.h>
	27	#include <asm/gpio.h>
	28	#include <i2c.h>
	29	#include <miiphy.h>
	30	#include <cpsw.h>
	31	#include <power/tps65217.h>
	32	#include <power/tps65910.h>
	33	#include <environment.h>
	34	#include <watchdog.h>
	35	#include "board.h"
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
	39	/* GPIO that controls power to DDR on EVM-SK */
	40	#define GPIO_DDR_VTT_EN 7
	41	#define DIP_S1 44
	42
	43	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	44
	45	static int baltos_set_console(void)
	46	{
	47	int val, i, dips = 0;
	48	char buf[7];
	49
	50	for (i = 0; i < 4; i++) {
	51	sprintf(buf, "dip_s%d", i + 1);
	52
	53	if (gpio_request(DIP_S1 + i, buf)) {
	54	printf("failed to export GPIO %d\n", DIP_S1 + i);
	55	return 0;
	56	}
	57
	58	if (gpio_direction_input(DIP_S1 + i)) {
	59	printf("failed to set GPIO %d direction\n", DIP_S1 + i);
	60	return 0;
	61	}
	62
	63	val = gpio_get_value(DIP_S1 + i);
	64	dips \|= val << i;
	65	}
	66
	67	printf("DIPs: 0x%1x\n", (~dips) & 0xf);
	68
	69	if ((dips & 0xf) == 0xe)
	70	setenv("console", "ttyUSB0,115200n8");
	71
	72	return 0;
	73	}
	74
	75	static int read_eeprom(BSP_VS_HWPARAM *header)
	76	{
	77	i2c_set_bus_num(1);
78
79	/* Check if baseboard eeprom is available */
80	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
81	puts("Could not probe the EEPROM; something fundamentally "
82	"wrong on the I2C bus.\n");
83	return -ENODEV;
84	}
85
86	/* read the eeprom using i2c */
87	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
88	sizeof(BSP_VS_HWPARAM))) {
89	puts("Could not read the EEPROM; something fundamentally"
90	" wrong on the I2C bus.\n");
91	return -EIO;
92	}
93
94	if (header->Magic != 0xDEADBEEF) {
95
96	printf("Incorrect magic number (0x%x) in EEPROM\n",
97	header->Magic);
98
99	/* fill default values */
100	header->SystemId = 211;
101	header->MAC1[0] = 0x00;
102	header->MAC1[1] = 0x00;
103	header->MAC1[2] = 0x00;
104	header->MAC1[3] = 0x00;
105	header->MAC1[4] = 0x00;
106	header->MAC1[5] = 0x01;
107
108	header->MAC2[0] = 0x00;
109	header->MAC2[1] = 0x00;
110	header->MAC2[2] = 0x00;
111	header->MAC2[3] = 0x00;
112	header->MAC2[4] = 0x00;
113	header->MAC2[5] = 0x02;
114
115	header->MAC3[0] = 0x00;
116	header->MAC3[1] = 0x00;
117	header->MAC3[2] = 0x00;
118	header->MAC3[3] = 0x00;
119	header->MAC3[4] = 0x00;
120	header->MAC3[5] = 0x03;
121	}
122
123	return 0;
124	}
125
126	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_NOR_BOOT)
127
128	static const struct ddr_data ddr3_baltos_data = {
129	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
130	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
131	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
132	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
133	};
134
135	static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
136	.cmd0csratio = MT41K256M16HA125E_RATIO,
137	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
138
139	.cmd1csratio = MT41K256M16HA125E_RATIO,
140	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
141
142	.cmd2csratio = MT41K256M16HA125E_RATIO,
143	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
144	};
145
146	static struct emif_regs ddr3_baltos_emif_reg_data = {
147	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
148	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
149	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
150	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
151	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
152	.zq_config = MT41K256M16HA125E_ZQ_CFG,
153	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
154	};
155
156	#ifdef CONFIG_SPL_OS_BOOT
157	int spl_start_uboot(void)
158	{
159	/* break into full u-boot on 'c' */
160	return (serial_tstc() && serial_getc() == 'c');
161	}
162	#endif
163
164	#define OSC (V_OSCK/1000000)
165	const struct dpll_params dpll_ddr = {
166	266, OSC-1, 1, -1, -1, -1, -1};
167	const struct dpll_params dpll_ddr_evm_sk = {
168	303, OSC-1, 1, -1, -1, -1, -1};
169	const struct dpll_params dpll_ddr_baltos = {
170	400, OSC-1, 1, -1, -1, -1, -1};
171
172	void am33xx_spl_board_init(void)
173	{
174	int mpu_vdd;
175	int sil_rev;
176
177	/* Get the frequency */
178	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
179
180	/*
181	* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
182	* MPU frequencies we support we use a CORE voltage of
183	* 1.1375V. For MPU voltage we need to switch based on
184	* the frequency we are running at.
185	*/
186	i2c_set_bus_num(1);
187
e6b1b58b YY	188	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
e6b1b58b YY	189
6ce89324 YY	190	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
	191	puts("i2c: cannot access TPS65910\n");
	192	return;
	193	}
	194
	195	/*
	196	* Depending on MPU clock and PG we will need a different
	197	* VDD to drive at that speed.
	198	*/
	199	sil_rev = readl(&cdev->deviceid) >> 28;
	200	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
	201	dpll_mpu_opp100.m);
	202
	203	/* Tell the TPS65910 to use i2c */
	204	tps65910_set_i2c_control();
	205
	206	/* First update MPU voltage. */
	207	if (tps65910_voltage_update(MPU, mpu_vdd))
	208	return;
	209
	210	/* Second, update the CORE voltage. */
	211	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
	212	return;
	213
	214	/* Set CORE Frequencies to OPP100 */
	215	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
	216
	217	/* Set MPU Frequency to what we detected now that voltages are set */
	218	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
	219
	220	writel(0x000010ff, PRM_DEVICE_INST + 4);
	221	}
	222
	223	const struct dpll_params *get_dpll_ddr_params(void)
	224	{
	225	enable_i2c1_pin_mux();
	226	i2c_set_bus_num(1);
	227
	228	return &dpll_ddr_baltos;
	229	}
	230
	231	void set_uart_mux_conf(void)
	232	{
	233	enable_uart0_pin_mux();
	234	}
	235
	236	void set_mux_conf_regs(void)
	237	{
	238	enable_board_pin_mux();
	239	}
	240
	241	const struct ctrl_ioregs ioregs_baltos = {
	242	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	243	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	244	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	245	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	246	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	247	};
	248
	249	void sdram_init(void)
	250	{
	251	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	252	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	253
254	config_ddr(400, &ioregs_baltos,
255	&ddr3_baltos_data,
256	&ddr3_baltos_cmd_ctrl_data,
257	&ddr3_baltos_emif_reg_data, 0);
258	}
259	#endif
260
261	/*
262	* Basic board specific setup. Pinmux has been handled already.
263	*/
264	int board_init(void)
265	{
266	#if defined(CONFIG_HW_WATCHDOG)
267	hw_watchdog_init();
268	#endif
269
270	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
271	#if defined(CONFIG_NOR) \|\| defined(CONFIG_NAND)
272	gpmc_init();
273	#endif
274	return 0;
275	}
276
277	int ft_board_setup(void blob, bd_t bd)
278	{
279	int node, ret;
280	unsigned char mac_addr[6];
281	BSP_VS_HWPARAM header;
282
283	/* get production data */
284	if (read_eeprom(&header))
285	return 0;
286
287	/* setup MAC1 */
288	mac_addr[0] = header.MAC1[0];
289	mac_addr[1] = header.MAC1[1];
290	mac_addr[2] = header.MAC1[2];
291	mac_addr[3] = header.MAC1[3];
292	mac_addr[4] = header.MAC1[4];
293	mac_addr[5] = header.MAC1[5];
294
295
296	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
297	if (node < 0) {
298	printf("no /soc/fman/ethernet path offset\n");
299	return -ENODEV;
300	}
301
302	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
303	if (ret) {
304	printf("error setting local-mac-address property\n");
305	return -ENODEV;
306	}
307
308	/* setup MAC2 */
309	mac_addr[0] = header.MAC2[0];
310	mac_addr[1] = header.MAC2[1];
311	mac_addr[2] = header.MAC2[2];
312	mac_addr[3] = header.MAC2[3];
313	mac_addr[4] = header.MAC2[4];
314	mac_addr[5] = header.MAC2[5];
315
316	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
317	if (node < 0) {
318	printf("no /soc/fman/ethernet path offset\n");
319	return -ENODEV;
320	}
321
322	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
323	if (ret) {
324	printf("error setting local-mac-address property\n");
325	return -ENODEV;
326	}
327
328	printf("\nFDT was successfully setup\n");
329
330	return 0;
331	}
332
333	static struct module_pin_mux dip_pin_mux[] = {
334	{OFFSET(gpmc_ad12), (MODE(7) \| RXACTIVE )}, /* GPIO1_12 */
335	{OFFSET(gpmc_ad13), (MODE(7) \| RXACTIVE )}, /* GPIO1_13 */
336	{OFFSET(gpmc_ad14), (MODE(7) \| RXACTIVE )}, /* GPIO1_14 */
337	{OFFSET(gpmc_ad15), (MODE(7) \| RXACTIVE )}, /* GPIO1_15 */
338	{-1},
339	};
340
341	#ifdef CONFIG_BOARD_LATE_INIT
342	int board_late_init(void)
343	{
344	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
345	BSP_VS_HWPARAM header;
346	char model[4];
347
348	/* get production data */
349	if (read_eeprom(&header)) {
192bc694	350	strcpy(model, "211");
6ce89324 YY	351	} else {
	352	sprintf(model, "%d", header.SystemId);
	353	if (header.SystemId == 215) {
	354	configure_module_pin_mux(dip_pin_mux);
	355	baltos_set_console();
	356	}
	357	}
	358	setenv("board_name", model);
	359	#endif
	360
	361	return 0;
	362	}
	363	#endif
	364
	365	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	366	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	367	static void cpsw_control(int enabled)
	368	{
	369	/* VTP can be added here */
	370
	371	return;
	372	}
	373
	374	static struct cpsw_slave_data cpsw_slaves[] = {
	375	{
	376	.slave_reg_ofs = 0x208,
	377	.sliver_reg_ofs = 0xd80,
	378	.phy_addr = 0,
	379	},
	380	{
	381	.slave_reg_ofs = 0x308,
	382	.sliver_reg_ofs = 0xdc0,
	383	.phy_addr = 7,
	384	},
	385	};
	386
	387	static struct cpsw_platform_data cpsw_data = {
	388	.mdio_base = CPSW_MDIO_BASE,
	389	.cpsw_base = CPSW_BASE,
	390	.mdio_div = 0xff,
	391	.channels = 8,
	392	.cpdma_reg_ofs = 0x800,
	393	.slaves = 2,
	394	.slave_data = cpsw_slaves,
	395	.active_slave = 1,
	396	.ale_reg_ofs = 0xd00,
	397	.ale_entries = 1024,
	398	.host_port_reg_ofs = 0x108,
	399	.hw_stats_reg_ofs = 0x900,
	400	.bd_ram_ofs = 0x2000,
	401	.mac_control = (1 << 5),
	402	.control = cpsw_control,
	403	.host_port_num = 0,
	404	.version = CPSW_CTRL_VERSION_2,
	405	};
	406	#endif
	407
	408	#if ((defined(CONFIG_SPL_ETH_SUPPORT) \|\| defined(CONFIG_SPL_USBETH_SUPPORT)) \
	409	&& defined(CONFIG_SPL_BUILD)) \|\| \
	410	((defined(CONFIG_DRIVER_TI_CPSW) \|\| \
95de1e2f	411	defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
6ce89324 YY	412	!defined(CONFIG_SPL_BUILD))
	413	int board_eth_init(bd_t *bis)
	414	{
	415	int rv, n = 0;
	416	uint8_t mac_addr[6];
	417	uint32_t mac_hi, mac_lo;
	418	__maybe_unused struct am335x_baseboard_id header;
	419
	420	/*
	421	* Note here that we're using CPSW1 since that has a 1Gbit PHY while
	422	* CSPW0 has a 100Mbit PHY.
	423	*
	424	* On product, CPSW1 maps to port labeled WAN.
	425	*/
	426
	427	/* try reading mac address from efuse */
	428	mac_lo = readl(&cdev->macid1l);
	429	mac_hi = readl(&cdev->macid1h);
	430	mac_addr[0] = mac_hi & 0xFF;
	431	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	432	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	433	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	434	mac_addr[4] = mac_lo & 0xFF;
	435	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	436
	437	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	438	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	439	if (!getenv("ethaddr")) {
	440	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
	441
	442	if (is_valid_ethaddr(mac_addr))
	443	eth_setenv_enetaddr("ethaddr", mac_addr);
	444	}
	445
	446	#ifdef CONFIG_DRIVER_TI_CPSW
	447	writel((GMII1_SEL_RMII \| GMII2_SEL_RGMII \| RGMII2_IDMODE), &cdev->miisel);
	448	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
	449	rv = cpsw_register(&cpsw_data);
	450	if (rv < 0)
	451	printf("Error %d registering CPSW switch\n", rv);
	452	else
	453	n += rv;
	454	#endif
	455
	456	/*
	457	*
	458	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	459	* operating points. So we must set the TX clock delay feature
	460	* in the AR8051 PHY. Since we only support a single ethernet
	461	* device in U-Boot, we only do this for the first instance.
	462	*/
	463	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	464	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	465	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	466	#define AR8051_RGMII_TX_CLK_DLY 0x100
	467	const char *devname;
	468	devname = miiphy_get_current_dev();
	469
	470	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
	471	AR8051_DEBUG_RGMII_CLK_DLY_REG);
	472	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
	473	AR8051_RGMII_TX_CLK_DLY);
	474	#endif
	475	return n;
476	}
477	#endif