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fe8c2806 WD |
1 | /*------------------------------------------------------------------------------+ */ |
2 | /* */ | |
3 | /* This source code has been made available to you by IBM on an AS-IS */ | |
4 | /* basis. Anyone receiving this source is licensed under IBM */ | |
5 | /* copyrights to use it in any way he or she deems fit, including */ | |
6 | /* copying it, modifying it, compiling it, and redistributing it either */ | |
7 | /* with or without modifications. No license under IBM patents or */ | |
8 | /* patent applications is to be implied by the copyright license. */ | |
9 | /* */ | |
10 | /* Any user of this software should understand that IBM cannot provide */ | |
11 | /* technical support for this software and will not be responsible for */ | |
12 | /* any consequences resulting from the use of this software. */ | |
13 | /* */ | |
14 | /* Any person who transfers this source code or any derivative work */ | |
15 | /* must include the IBM copyright notice, this paragraph, and the */ | |
16 | /* preceding two paragraphs in the transferred software. */ | |
17 | /* */ | |
18 | /* COPYRIGHT I B M CORPORATION 1995 */ | |
19 | /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ | |
20 | /*------------------------------------------------------------------------------- */ | |
21 | ||
22 | /*----------------------------------------------------------------------------- */ | |
23 | /* Function: ext_bus_cntlr_init */ | |
24 | /* Description: Initializes the External Bus Controller for the external */ | |
25 | /* peripherals. IMPORTANT: For pass1 this code must run from */ | |
26 | /* cache since you can not reliably change a peripheral banks */ | |
27 | /* timing register (pbxap) while running code from that bank. */ | |
28 | /* For ex., since we are running from ROM on bank 0, we can NOT */ | |
29 | /* execute the code that modifies bank 0 timings from ROM, so */ | |
30 | /* we run it from cache. */ | |
31 | /* Bank 0 - Flash and SRAM */ | |
32 | /* Bank 1 - NVRAM/RTC */ | |
33 | /* Bank 2 - Keyboard/Mouse controller */ | |
34 | /* Bank 3 - IR controller */ | |
35 | /* Bank 4 - not used */ | |
36 | /* Bank 5 - not used */ | |
37 | /* Bank 6 - not used */ | |
38 | /* Bank 7 - FPGA registers */ | |
39 | /*----------------------------------------------------------------------------- */ | |
40 | #include <ppc4xx.h> | |
41 | ||
42 | #include <ppc_asm.tmpl> | |
43 | #include <ppc_defs.h> | |
44 | ||
45 | #include <asm/cache.h> | |
46 | #include <asm/mmu.h> | |
47 | ||
48 | ||
8bde7f77 | 49 | .globl ext_bus_cntlr_init |
fe8c2806 | 50 | ext_bus_cntlr_init: |
8bde7f77 WD |
51 | mflr r4 /* save link register */ |
52 | bl ..getAddr | |
fe8c2806 | 53 | ..getAddr: |
8bde7f77 WD |
54 | mflr r3 /* get address of ..getAddr */ |
55 | mtlr r4 /* restore link register */ | |
56 | addi r4,0,14 /* set ctr to 10; used to prefetch */ | |
57 | mtctr r4 /* 10 cache lines to fit this function */ | |
58 | /* in cache (gives us 8x10=80 instrctns) */ | |
fe8c2806 | 59 | ..ebcloop: |
8bde7f77 WD |
60 | icbt r0,r3 /* prefetch cache line for addr in r3 */ |
61 | addi r3,r3,32 /* move to next cache line */ | |
62 | bdnz ..ebcloop /* continue for 10 cache lines */ | |
fe8c2806 | 63 | |
8bde7f77 WD |
64 | /*------------------------------------------------------------------- */ |
65 | /* Delay to ensure all accesses to ROM are complete before changing */ | |
fe8c2806 | 66 | /* bank 0 timings. 200usec should be enough. */ |
8bde7f77 WD |
67 | /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ |
68 | /*------------------------------------------------------------------- */ | |
fe8c2806 | 69 | addis r3,0,0x0 |
8bde7f77 WD |
70 | ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ |
71 | mtctr r3 | |
fe8c2806 | 72 | ..spinlp: |
8bde7f77 | 73 | bdnz ..spinlp /* spin loop */ |
fe8c2806 | 74 | |
8bde7f77 WD |
75 | /*----------------------------------------------------------------------- */ |
76 | /* Memory Bank 0 (Flash and SRAM) initialization */ | |
77 | /*----------------------------------------------------------------------- */ | |
78 | addi r4,0,pb0ap | |
79 | mtdcr ebccfga,r4 | |
80 | addis r4,0,0x9B01 | |
81 | ori r4,r4,0x5480 | |
82 | mtdcr ebccfgd,r4 | |
fe8c2806 | 83 | |
8bde7f77 WD |
84 | addi r4,0,pb0cr |
85 | mtdcr ebccfga,r4 | |
86 | addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ | |
87 | ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ | |
88 | mtdcr ebccfgd,r4 | |
fe8c2806 | 89 | |
8bde7f77 | 90 | blr |
fe8c2806 WD |
91 | |
92 | ||
93 | /*----------------------------------------------------------------------------- */ | |
94 | /* Function: sdram_init */ | |
95 | /* Description: Dummy implementation here - done in C later */ | |
96 | /*----------------------------------------------------------------------------- */ | |
8bde7f77 | 97 | .globl sdram_init |
fe8c2806 | 98 | sdram_init: |
8bde7f77 | 99 | blr |