[people/ms/u-boot.git] / board / wandboard / spl.c

/*
 * Copyright (C) 2014 Wandboard
 * Author: Tungyi Lin <tungyilin1127@gmail.com>
 *         Richard Hu <hakahu@gmail.com>
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
 * Driving strength:
 *   0x30 == 40 Ohm
 *   0x28 == 48 Ohm
 */

#define IMX6DQ_DRIVE_STRENGTH		0x30
#define IMX6SDL_DRIVE_STRENGTH		0x28
#define IMX6QP_DRIVE_STRENGTH		0x28

/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
};

/* configure MX6QP mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
	.dram_cas = IMX6QP_DRIVE_STRENGTH,
	.dram_ras = IMX6QP_DRIVE_STRENGTH,
	.dram_reset = IMX6QP_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
};

/* configure MX6QP mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6QP_DRIVE_STRENGTH,
	.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
	.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};

/* H5T04G63AFR-PB */
static struct mx6_ddr3_cfg h5t04g63afr = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* H5TQ2G63DFR-H9 */
static struct mx6_ddr3_cfg h5tq2g63dfr = {
	.mem_speed = 1333,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1350,
	.trcmin = 4950,
	.trasmin = 3600,
};

static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001f001f,
	.p0_mpwldectrl1 = 0x001f001f,
	.p1_mpwldectrl0 = 0x001f001f,
	.p1_mpwldectrl1 = 0x001f001f,
	.p0_mpdgctrl0 = 0x4301030d,
	.p0_mpdgctrl1 = 0x03020277,
	.p1_mpdgctrl0 = 0x4300030a,
	.p1_mpdgctrl1 = 0x02780248,
	.p0_mprddlctl = 0x4536393b,
	.p1_mprddlctl = 0x36353441,
	.p0_mpwrdlctl = 0x41414743,
	.p1_mpwrdlctl = 0x462f453f,
};

/* DDR 64bit 2GB */
static struct mx6_ddr_sysinfo mem_q = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 0,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
	.refsel = 1,	/* Refresh cycles at 32KHz */
	.refr = 3,	/* 4 refresh commands per refresh cycle */
};

static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001f001f,
	.p0_mpwldectrl1 = 0x001f001f,
	.p1_mpwldectrl0 = 0x001f001f,
	.p1_mpwldectrl1 = 0x001f001f,
	.p0_mpdgctrl0 = 0x420e020e,
	.p0_mpdgctrl1 = 0x02000200,
	.p1_mpdgctrl0 = 0x42020202,
	.p1_mpdgctrl1 = 0x01720172,
	.p0_mprddlctl = 0x494c4f4c,
	.p1_mprddlctl = 0x4a4c4c49,
	.p0_mpwrdlctl = 0x3f3f3133,
	.p1_mpwrdlctl = 0x39373f2e,
};

static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
	.p0_mpwldectrl0 = 0x0040003c,
	.p0_mpwldectrl1 = 0x0032003e,
	.p0_mpdgctrl0 = 0x42350231,
	.p0_mpdgctrl1 = 0x021a0218,
	.p0_mprddlctl = 0x4b4b4e49,
	.p0_mpwrdlctl = 0x3f3f3035,
};

/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 0,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
	.refsel = 1,	/* Refresh cycles at 32KHz */
	.refr = 3,	/* 4 refresh commands per refresh cycle */
};

/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
	.dsize		= 1,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 0,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
	.refsel = 1,	/* Refresh cycles at 32KHz */
	.refr = 3,	/* 4 refresh commands per refresh cycle */
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF03000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void spl_dram_init_imx6qp_lpddr3(void)
{
	/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
	/* Calibrations - ZQ */
	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
	/* write leveling */
	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
	/*
	 * DQS gating, read delay, write delay calibration values
	 * based on calibration compare of 0x00ffff00
	 */
	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
	/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
	/* add NOC DDR configuration */
	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
}

static void spl_dram_init(void)
{
	if (is_mx6dqp()) {
		mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
		spl_dram_init_imx6qp_lpddr3();
	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
	}

	udelay(100);
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	gpr_init();

	/* iomux */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();
}
#endif
Commit	Line	Data
0d1ea052 FE	1	/*
	2	* Copyright (C) 2014 Wandboard
	3	* Author: Tungyi Lin <tungyilin1127@gmail.com>
	4	* Richard Hu <hakahu@gmail.com>
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/imx-regs.h>
	10	#include <asm/arch/iomux.h>
	11	#include <asm/arch/mx6-pins.h>
1221ce45	12	#include <linux/errno.h>
0d1ea052	13	#include <asm/gpio.h>
552a848e SB	14	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	15	#include <asm/mach-imx/video.h>
0d1ea052 FE	16	#include <mmc.h>
	17	#include <fsl_esdhc.h>
	18	#include <asm/arch/crm_regs.h>
	19	#include <asm/io.h>
	20	#include <asm/arch/sys_proto.h>
	21	#include <spl.h>
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	#if defined(CONFIG_SPL_BUILD)
	26	#include <asm/arch/mx6-ddr.h>
	27	/*
	28	* Driving strength:
	29	* 0x30 == 40 Ohm
	30	* 0x28 == 48 Ohm
	31	*/
	32
	33	#define IMX6DQ_DRIVE_STRENGTH 0x30
	34	#define IMX6SDL_DRIVE_STRENGTH 0x28
e1f0715f	35	#define IMX6QP_DRIVE_STRENGTH 0x28
0d1ea052 FE	36
	37	/* configure MX6Q/DUAL mmdc DDR io registers */
	38	static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	39	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	40	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	41	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	42	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	43	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	44	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	45	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	46	.dram_sdba2 = 0x00000000,
	47	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	48	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	49	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	50	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	51	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	52	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	53	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	54	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	55	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	56	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	57	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	58	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	59	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	60	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	61	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	62	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	63	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	64	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
	65	};
	66
e1f0715f FE	67	/* configure MX6QP mmdc DDR io registers */
	68	static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
	69	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
	70	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
	71	.dram_cas = IMX6QP_DRIVE_STRENGTH,
	72	.dram_ras = IMX6QP_DRIVE_STRENGTH,
	73	.dram_reset = IMX6QP_DRIVE_STRENGTH,
	74	.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
	75	.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
	76	.dram_sdba2 = 0x00000000,
	77	.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
	78	.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
	79	.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
	80	.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
	81	.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
	82	.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
	83	.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
	84	.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
	85	.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
	86	.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
	87	.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
	88	.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
	89	.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
	90	.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
	91	.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
	92	.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
	93	.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
	94	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
	95	};
	96
0d1ea052 FE	97	/* configure MX6Q/DUAL mmdc GRP io registers */
	98	static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	99	.grp_ddr_type = 0x000c0000,
	100	.grp_ddrmode_ctl = 0x00020000,
	101	.grp_ddrpke = 0x00000000,
	102	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	103	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	104	.grp_ddrmode = 0x00020000,
	105	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	106	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	107	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	108	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	109	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	110	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	111	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	112	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
	113	};
	114
e1f0715f FE	115	/* configure MX6QP mmdc GRP io registers */
	116	static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
	117	.grp_ddr_type = 0x000c0000,
	118	.grp_ddrmode_ctl = 0x00020000,
	119	.grp_ddrpke = 0x00000000,
	120	.grp_addds = IMX6QP_DRIVE_STRENGTH,
	121	.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
	122	.grp_ddrmode = 0x00020000,
	123	.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
	124	.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
	125	.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
	126	.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
	127	.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
	128	.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
	129	.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
	130	.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
	131	};
	132
0d1ea052 FE	133	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	134	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	135	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
	136	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
	137	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
	138	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
	139	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
	140	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
	141	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
	142	.dram_sdba2 = 0x00000000,
	143	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
	144	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
	145	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
	146	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
	147	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
	148	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
	149	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
	150	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
	151	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
	152	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
	153	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
	154	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
	155	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
	156	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
	157	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
	158	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
	159	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
	160	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
	161	};
	162
	163	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
	164	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	165	.grp_ddr_type = 0x000c0000,
	166	.grp_ddrmode_ctl = 0x00020000,
	167	.grp_ddrpke = 0x00000000,
	168	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
	169	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
	170	.grp_ddrmode = 0x00020000,
	171	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
	172	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
	173	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
	174	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
	175	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
	176	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
	177	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
	178	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
	179	};
	180
	181	/* H5T04G63AFR-PB */
	182	static struct mx6_ddr3_cfg h5t04g63afr = {
	183	.mem_speed = 1600,
	184	.density = 4,
	185	.width = 16,
	186	.banks = 8,
	187	.rowaddr = 15,
	188	.coladdr = 10,
	189	.pagesz = 2,
	190	.trcd = 1375,
	191	.trcmin = 4875,
	192	.trasmin = 3500,
	193	};
	194
	195	/* H5TQ2G63DFR-H9 */
	196	static struct mx6_ddr3_cfg h5tq2g63dfr = {
197	.mem_speed = 1333,
198	.density = 2,
199	.width = 16,
200	.banks = 8,
201	.rowaddr = 14,
202	.coladdr = 10,
203	.pagesz = 2,
204	.trcd = 1350,
205	.trcmin = 4950,
206	.trasmin = 3600,
207	};
208
209	static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
210	.p0_mpwldectrl0 = 0x001f001f,
211	.p0_mpwldectrl1 = 0x001f001f,
212	.p1_mpwldectrl0 = 0x001f001f,
213	.p1_mpwldectrl1 = 0x001f001f,
214	.p0_mpdgctrl0 = 0x4301030d,
215	.p0_mpdgctrl1 = 0x03020277,
216	.p1_mpdgctrl0 = 0x4300030a,
217	.p1_mpdgctrl1 = 0x02780248,
218	.p0_mprddlctl = 0x4536393b,
219	.p1_mprddlctl = 0x36353441,
220	.p0_mpwrdlctl = 0x41414743,
221	.p1_mpwrdlctl = 0x462f453f,
222	};
223
224	/* DDR 64bit 2GB */
225	static struct mx6_ddr_sysinfo mem_q = {
226	.dsize = 2,
227	.cs1_mirror = 0,
228	/* config for full 4GB range so that get_mem_size() works */
229	.cs_density = 32,
230	.ncs = 1,
231	.bi_on = 1,
232	.rtt_nom = 1,
233	.rtt_wr = 0,
234	.ralat = 5,
235	.walat = 0,
236	.mif3_mode = 3,
237	.rst_to_cke = 0x23,
238	.sde_to_rst = 0x10,
edf00937	239	.refsel = 1, /* Refresh cycles at 32KHz */
ba4e159f	240	.refr = 3, /* 4 refresh commands per refresh cycle */
0d1ea052 FE	241	};
	242
	243	static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
	244	.p0_mpwldectrl0 = 0x001f001f,
	245	.p0_mpwldectrl1 = 0x001f001f,
	246	.p1_mpwldectrl0 = 0x001f001f,
	247	.p1_mpwldectrl1 = 0x001f001f,
	248	.p0_mpdgctrl0 = 0x420e020e,
	249	.p0_mpdgctrl1 = 0x02000200,
	250	.p1_mpdgctrl0 = 0x42020202,
	251	.p1_mpdgctrl1 = 0x01720172,
	252	.p0_mprddlctl = 0x494c4f4c,
	253	.p1_mprddlctl = 0x4a4c4c49,
	254	.p0_mpwrdlctl = 0x3f3f3133,
	255	.p1_mpwrdlctl = 0x39373f2e,
	256	};
	257
	258	static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
	259	.p0_mpwldectrl0 = 0x0040003c,
	260	.p0_mpwldectrl1 = 0x0032003e,
	261	.p0_mpdgctrl0 = 0x42350231,
	262	.p0_mpdgctrl1 = 0x021a0218,
	263	.p0_mprddlctl = 0x4b4b4e49,
	264	.p0_mpwrdlctl = 0x3f3f3035,
	265	};
	266
	267	/* DDR 64bit 1GB */
	268	static struct mx6_ddr_sysinfo mem_dl = {
	269	.dsize = 2,
	270	.cs1_mirror = 0,
	271	/* config for full 4GB range so that get_mem_size() works */
	272	.cs_density = 32,
	273	.ncs = 1,
	274	.bi_on = 1,
	275	.rtt_nom = 1,
	276	.rtt_wr = 0,
	277	.ralat = 5,
	278	.walat = 0,
	279	.mif3_mode = 3,
	280	.rst_to_cke = 0x23,
	281	.sde_to_rst = 0x10,
edf00937	282	.refsel = 1, /* Refresh cycles at 32KHz */
ba4e159f	283	.refr = 3, /* 4 refresh commands per refresh cycle */
0d1ea052 FE	284	};
	285
	286	/* DDR 32bit 512MB */
	287	static struct mx6_ddr_sysinfo mem_s = {
	288	.dsize = 1,
	289	.cs1_mirror = 0,
	290	/* config for full 4GB range so that get_mem_size() works */
	291	.cs_density = 32,
	292	.ncs = 1,
	293	.bi_on = 1,
	294	.rtt_nom = 1,
	295	.rtt_wr = 0,
	296	.ralat = 5,
	297	.walat = 0,
	298	.mif3_mode = 3,
	299	.rst_to_cke = 0x23,
	300	.sde_to_rst = 0x10,
edf00937	301	.refsel = 1, /* Refresh cycles at 32KHz */
ba4e159f	302	.refr = 3, /* 4 refresh commands per refresh cycle */
0d1ea052 FE	303	};
	304
	305	static void ccgr_init(void)
	306	{
	307	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	308
	309	writel(0x00C03F3F, &ccm->CCGR0);
	310	writel(0x0030FC03, &ccm->CCGR1);
	311	writel(0x0FFFC000, &ccm->CCGR2);
e1f0715f	312	writel(0x3FF03000, &ccm->CCGR3);
0d1ea052 FE	313	writel(0x00FFF300, &ccm->CCGR4);
	314	writel(0x0F0000C3, &ccm->CCGR5);
	315	writel(0x000003FF, &ccm->CCGR6);
	316	}
	317
e1f0715f FE	318	static void spl_dram_init_imx6qp_lpddr3(void)
	319	{
	320	/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
	321	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
	322	/* Calibrations - ZQ */
	323	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
	324	/* write leveling */
	325	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
	326	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
	327	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
	328	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
	329	/*
	330	* DQS gating, read delay, write delay calibration values
	331	* based on calibration compare of 0x00ffff00
	332	*/
	333	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
	334	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
	335	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
	336	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
	337	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
	338	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
	339	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
	340	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
	341	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
	342	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
	343	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
	344	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
	345	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
	346	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
	347	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
	348	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
	349	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
	350	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
	351	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
	352	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
	353	/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
	354	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
	355	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
	356	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
	357	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
	358	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
	359	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
	360	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
	361	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
	362	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
	363	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
	364	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
	365	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
	366	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
	367	/* add NOC DDR configuration */
	368	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
	369	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
	370	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
	371	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
	372	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
	373	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
	374	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
	375	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
	376	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
	377	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
	378	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
	379	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
	380	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
	381	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
382	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
383	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
384	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
385	}
386
0d1ea052 FE	387	static void spl_dram_init(void)
0d1ea052 FE	388	{
e1f0715f FE	389	if (is_mx6dqp()) {
	390	mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
	391	spl_dram_init_imx6qp_lpddr3();
	392	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
0d1ea052 FE	393	mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	394	mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
	395	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
	396	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	397	mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
	398	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
	399	mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
	400	mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
	401	}
401cabc2 FE	402
401cabc2 FE	403	udelay(100);
0d1ea052 FE	404	}
	405
	406	void board_init_f(ulong dummy)
	407	{
	408	ccgr_init();
	409
	410	/* setup AIPS and disable watchdog */
	411	arch_cpu_init();
	412
	413	gpr_init();
	414
	415	/* iomux */
	416	board_early_init_f();
	417
	418	/* setup GP timer */
	419	timer_init();
	420
	421	/* UART clocks enabled and gd valid - init serial console */
	422	preloader_console_init();
	423
	424	/* DDR initialization */
	425	spl_dram_init();
0d1ea052 FE	426	}
0d1ea052 FE	427	#endif