[people/ms/u-boot.git] / board / wandboard / wandboard.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 * Copyright (C) 2014 O.S. Systems Software LTDA.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
#include <phy.h>
#include <input.h>
#include <i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
#define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
#define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
#define REV_DETECTION		IMX_GPIO_NR(2, 28)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	/* Carrier MicroSD Card Detect */
	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	/* SOM MicroSD Card Detect */
	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const enet_pads[] = {
	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	/* AR8031 PHY Reset */
	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const rev_detection_pad[] = {
	IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static void setup_iomux_uart(void)
{
	SETUP_IOMUX_PADS(uart1_pads);
}

static void setup_iomux_enet(void)
{
	SETUP_IOMUX_PADS(enet_pads);

	/* Reset AR8031 PHY */
	gpio_direction_output(ETH_PHY_RESET, 0);
	mdelay(10);
	gpio_set_value(ETH_PHY_RESET, 1);
	udelay(100);
}

static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC3_BASE_ADDR},
	{USDHC1_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = !gpio_get_value(USDHC3_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;
	u32 index = 0;

	/*
	 * Following map is done:
	 * (U-Boot device node)    (Physical Port)
	 * mmc0                    SOM MicroSD
	 * mmc1                    Carrier board MicroSD
	 */
	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
		switch (index) {
		case 0:
			SETUP_IOMUX_PADS(usdhc3_pads);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			usdhc_cfg[0].max_bus_width = 4;
			gpio_direction_input(USDHC3_CD_GPIO);
			break;
		case 1:
			SETUP_IOMUX_PADS(usdhc1_pads);
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			usdhc_cfg[1].max_bus_width = 4;
			gpio_direction_input(USDHC1_CD_GPIO);
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
			       "(%d) then supported by the board (%d)\n",
			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
		if (ret)
			return ret;
	}

	return 0;
}

#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
	.scl = {
		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(4, 12)
	},
	.sda = {
		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(4, 13)
	}
};

struct i2c_pads_info mx6dl_i2c2_pad_info = {
	.scl = {
		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(4, 12)
	},
	.sda = {
		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
			| MUX_PAD_CTRL(I2C_PAD_CTRL),
		.gp = IMX_GPIO_NR(4, 13)
	}
};

static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04	| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
};

static void do_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

static int detect_i2c(struct display_info_t const *dev)
{
	return (0 == i2c_set_bus_num(dev->bus)) &&
			(0 == i2c_probe(dev->addr));
}

static void enable_fwadapt_7wvga(struct display_info_t const *dev)
{
	SETUP_IOMUX_PADS(fwadapt_7wvga_pads);

	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
}

struct display_info_t const displays[] = {{
	.bus	= -1,
	.addr	= 0,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_hdmi,
	.enable	= do_enable_hdmi,
	.mode	= {
		.name           = "HDMI",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 15385,
		.left_margin    = 220,
		.right_margin   = 40,
		.upper_margin   = 21,
		.lower_margin   = 7,
		.hsync_len      = 60,
		.vsync_len      = 10,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED
} }, {
	.bus	= 1,
	.addr	= 0x10,
	.pixfmt	= IPU_PIX_FMT_RGB666,
	.detect	= detect_i2c,
	.enable	= enable_fwadapt_7wvga,
	.mode	= {
		.name           = "FWBADAPT-LCD-F07A-0102",
		.refresh        = 60,
		.xres           = 800,
		.yres           = 480,
		.pixclock       = 33260,
		.left_margin    = 128,
		.right_margin   = 128,
		.upper_margin   = 22,
		.lower_margin   = 22,
		.hsync_len      = 1,
		.vsync_len      = 1,
		.sync           = 0,
		.vmode          = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);

static void setup_display(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;

	enable_ipu_clock();
	imx_setup_hdmi();

	reg = readl(&mxc_ccm->chsccdr);
	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);

	/* Disable LCD backlight */
	SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
	gpio_direction_input(IMX_GPIO_NR(4, 20));
}
#endif /* CONFIG_VIDEO_IPUV3 */

int board_eth_init(bd_t *bis)
{
	setup_iomux_enet();

	return cpu_eth_init(bis);
}

int board_early_init_f(void)
{
	setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
	setup_display();
#endif
	return 0;
}

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"mmc0",	  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"mmc1",	  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

static bool is_revc1(void)
{
	SETUP_IOMUX_PADS(rev_detection_pad);
	gpio_direction_input(REV_DETECTION);

	if (gpio_get_value(REV_DETECTION))
		return true;
	else
		return false;
}

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
		setenv("board_rev", "MX6Q");
	else
		setenv("board_rev", "MX6DL");

	if (is_revc1())
		setenv("board_name", "C1");
	else
		setenv("board_name", "B1");
#endif
	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
	else
		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);

	return 0;
}

int checkboard(void)
{
	if (is_revc1())
		puts("Board: Wandboard rev C1\n");
	else
		puts("Board: Wandboard rev B1\n");

	return 0;
}
Commit	Line	Data
e2d282a1 FE	1	/*
e2d282a1 FE	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
8bc7c487	3	* Copyright (C) 2014 O.S. Systems Software LTDA.
e2d282a1 FE	4	*
	5	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
e2d282a1 FE	8	*/
	9
	10	#include <asm/arch/clock.h>
7bcb983f	11	#include <asm/arch/crm_regs.h>
e2d282a1 FE	12	#include <asm/arch/iomux.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/mx6-pins.h>
7bcb983f	15	#include <asm/arch/mxc_hdmi.h>
e2d282a1 FE	16	#include <asm/arch/sys_proto.h>
	17	#include <asm/gpio.h>
	18	#include <asm/imx-common/iomux-v3.h>
8bc7c487	19	#include <asm/imx-common/mxc_i2c.h>
eaffaa2d	20	#include <asm/imx-common/boot_mode.h>
8bc7c487	21	#include <asm/imx-common/video.h>
e2d282a1	22	#include <asm/io.h>
1ace4022	23	#include <linux/sizes.h>
e2d282a1 FE	24	#include <common.h>
	25	#include <fsl_esdhc.h>
	26	#include <mmc.h>
	27	#include <miiphy.h>
	28	#include <netdev.h>
2fb63964	29	#include <phy.h>
67a9abe9	30	#include <input.h>
8bc7c487	31	#include <i2c.h>
e2d282a1 FE	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
7e2173cf BT	35	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	36	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	37	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
e2d282a1	38
7e2173cf BT	39	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	40	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	41	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
e2d282a1	42
7e2173cf BT	43	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
7e2173cf BT	44	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
e2d282a1	45
8bc7c487 OS	46	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	47	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	48	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	49
5ed15738	50	#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
08f32f7d	51	#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
e2d282a1	52	#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
9a8804a8	53	#define REV_DETECTION IMX_GPIO_NR(2, 28)
e2d282a1 FE	54
	55	int dram_init(void)
	56	{
0d1ea052	57	gd->ram_size = imx_ddr_size();
e2d282a1 FE	58
	59	return 0;
	60	}
	61
	62	static iomux_v3_cfg_t const uart1_pads[] = {
0d1ea052 FE	63	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
0d1ea052 FE	64	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
e2d282a1 FE	65	};
e2d282a1 FE	66
afb92665	67	static iomux_v3_cfg_t const usdhc1_pads[] = {
0d1ea052 FE	68	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	69	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	70	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	71	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	72	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	73	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
5ed15738	74	/* Carrier MicroSD Card Detect */
0d1ea052	75	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
5ed15738 OS	76	};
5ed15738 OS	77
e2d282a1	78	static iomux_v3_cfg_t const usdhc3_pads[] = {
0d1ea052 FE	79	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	80	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	81	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	82	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	83	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	84	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
08f32f7d	85	/* SOM MicroSD Card Detect */
0d1ea052	86	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e2d282a1 FE	87	};
	88
	89	static iomux_v3_cfg_t const enet_pads[] = {
0d1ea052 FE	90	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	91	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	92	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	93	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	94	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	95	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	96	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	97	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	98	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	99	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	100	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	101	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	102	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	103	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	104	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
e2d282a1	105	/* AR8031 PHY Reset */
0d1ea052	106	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e2d282a1 FE	107	};
e2d282a1 FE	108
9a8804a8 FE	109	static iomux_v3_cfg_t const rev_detection_pad[] = {
	110	IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	111	};
	112
e2d282a1 FE	113	static void setup_iomux_uart(void)
e2d282a1 FE	114	{
0d1ea052	115	SETUP_IOMUX_PADS(uart1_pads);
e2d282a1 FE	116	}
	117
	118	static void setup_iomux_enet(void)
	119	{
0d1ea052	120	SETUP_IOMUX_PADS(enet_pads);
e2d282a1 FE	121
	122	/* Reset AR8031 PHY */
	123	gpio_direction_output(ETH_PHY_RESET, 0);
59a6ca54	124	mdelay(10);
e2d282a1	125	gpio_set_value(ETH_PHY_RESET, 1);
59a6ca54	126	udelay(100);
e2d282a1 FE	127	}
e2d282a1 FE	128
5ed15738	129	static struct fsl_esdhc_cfg usdhc_cfg[2] = {
e2d282a1	130	{USDHC3_BASE_ADDR},
5ed15738	131	{USDHC1_BASE_ADDR},
e2d282a1 FE	132	};
e2d282a1 FE	133
08f32f7d OS	134	int board_mmc_getcd(struct mmc *mmc)
	135	{
	136	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	137	int ret = 0;
	138
	139	switch (cfg->esdhc_base) {
5ed15738 OS	140	case USDHC1_BASE_ADDR:
	141	ret = !gpio_get_value(USDHC1_CD_GPIO);
	142	break;
08f32f7d OS	143	case USDHC3_BASE_ADDR:
	144	ret = !gpio_get_value(USDHC3_CD_GPIO);
	145	break;
	146	}
	147
	148	return ret;
	149	}
	150
e2d282a1 FE	151	int board_mmc_init(bd_t *bis)
e2d282a1 FE	152	{
05beb8e0	153	int ret;
5ed15738 OS	154	u32 index = 0;
	155
	156	/*
	157	* Following map is done:
a187559e	158	* (U-Boot device node) (Physical Port)
5ed15738 OS	159	* mmc0 SOM MicroSD
	160	* mmc1 Carrier board MicroSD
	161	*/
	162	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
	163	switch (index) {
	164	case 0:
0d1ea052	165	SETUP_IOMUX_PADS(usdhc3_pads);
5ed15738 OS	166	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	167	usdhc_cfg[0].max_bus_width = 4;
	168	gpio_direction_input(USDHC3_CD_GPIO);
	169	break;
	170	case 1:
0d1ea052	171	SETUP_IOMUX_PADS(usdhc1_pads);
5ed15738 OS	172	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	173	usdhc_cfg[1].max_bus_width = 4;
	174	gpio_direction_input(USDHC1_CD_GPIO);
	175	break;
	176	default:
	177	printf("Warning: you configured more USDHC controllers"
	178	"(%d) then supported by the board (%d)\n",
	179	index + 1, CONFIG_SYS_FSL_USDHC_NUM);
05beb8e0	180	return -EINVAL;
5ed15738 OS	181	}
5ed15738 OS	182
05beb8e0 FE	183	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	184	if (ret)
	185	return ret;
5ed15738	186	}
aad4659a	187
05beb8e0	188	return 0;
e2d282a1 FE	189	}
e2d282a1 FE	190
7bcb983f	191	#if defined(CONFIG_VIDEO_IPUV3)
0d1ea052	192	struct i2c_pads_info mx6q_i2c2_pad_info = {
8bc7c487	193	.scl = {
0d1ea052	194	.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
8bc7c487	195	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
0d1ea052	196	.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
8bc7c487 OS	197	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	198	.gp = IMX_GPIO_NR(4, 12)
	199	},
	200	.sda = {
0d1ea052	201	.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
8bc7c487	202	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
0d1ea052 FE	203	.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
	204	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	205	.gp = IMX_GPIO_NR(4, 13)
	206	}
	207	};
	208
	209	struct i2c_pads_info mx6dl_i2c2_pad_info = {
	210	.scl = {
	211	.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
	212	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	213	.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
	214	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	215	.gp = IMX_GPIO_NR(4, 12)
	216	},
	217	.sda = {
	218	.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
	219	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	220	.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
8bc7c487 OS	221	\| MUX_PAD_CTRL(I2C_PAD_CTRL),
	222	.gp = IMX_GPIO_NR(4, 13)
	223	}
7bcb983f FE	224	};
7bcb983f FE	225
8bc7c487	226	static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
0d1ea052 FE	227	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	228	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
	229	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
	230	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 \| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
	231	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
	232	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
	233	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
	234	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
	235	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
	236	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
	237	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
	238	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
	239	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
	240	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
	241	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
	242	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
	243	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
	244	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
	245	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
	246	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
	247	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
	248	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
	249	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
	250	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
	251	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
8bc7c487	252	};
7bcb983f	253
8bc7c487 OS	254	static void do_enable_hdmi(struct display_info_t const *dev)
	255	{
	256	imx_enable_hdmi_phy();
	257	}
7bcb983f	258
8bc7c487 OS	259	static int detect_i2c(struct display_info_t const *dev)
	260	{
	261	return (0 == i2c_set_bus_num(dev->bus)) &&
	262	(0 == i2c_probe(dev->addr));
	263	}
7bcb983f	264
8bc7c487 OS	265	static void enable_fwadapt_7wvga(struct display_info_t const *dev)
8bc7c487 OS	266	{
0d1ea052	267	SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
7bcb983f	268
8bc7c487 OS	269	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
8bc7c487 OS	270	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
7bcb983f FE	271	}
7bcb983f FE	272
8bc7c487 OS	273	struct display_info_t const displays[] = {{
	274	.bus = -1,
	275	.addr = 0,
	276	.pixfmt = IPU_PIX_FMT_RGB24,
	277	.detect = detect_hdmi,
	278	.enable = do_enable_hdmi,
	279	.mode = {
	280	.name = "HDMI",
	281	.refresh = 60,
	282	.xres = 1024,
	283	.yres = 768,
	284	.pixclock = 15385,
	285	.left_margin = 220,
	286	.right_margin = 40,
	287	.upper_margin = 21,
	288	.lower_margin = 7,
	289	.hsync_len = 60,
	290	.vsync_len = 10,
	291	.sync = FB_SYNC_EXT,
	292	.vmode = FB_VMODE_NONINTERLACED
	293	} }, {
	294	.bus = 1,
	295	.addr = 0x10,
	296	.pixfmt = IPU_PIX_FMT_RGB666,
	297	.detect = detect_i2c,
	298	.enable = enable_fwadapt_7wvga,
	299	.mode = {
	300	.name = "FWBADAPT-LCD-F07A-0102",
	301	.refresh = 60,
	302	.xres = 800,
	303	.yres = 480,
	304	.pixclock = 33260,
	305	.left_margin = 128,
	306	.right_margin = 128,
	307	.upper_margin = 22,
	308	.lower_margin = 22,
	309	.hsync_len = 1,
	310	.vsync_len = 1,
	311	.sync = 0,
	312	.vmode = FB_VMODE_NONINTERLACED
	313	} } };
	314	size_t display_count = ARRAY_SIZE(displays);
	315
7bcb983f FE	316	static void setup_display(void)
	317	{
	318	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
7bcb983f FE	319	int reg;
7bcb983f FE	320
5ea7f0e3 PKS	321	enable_ipu_clock();
5ea7f0e3 PKS	322	imx_setup_hdmi();
7bcb983f FE	323
7bcb983f FE	324	reg = readl(&mxc_ccm->chsccdr);
7bcb983f	325	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
5ea7f0e3	326	<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
7bcb983f	327	writel(reg, &mxc_ccm->chsccdr);
8bc7c487 OS	328
8bc7c487 OS	329	/* Disable LCD backlight */
0d1ea052	330	SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
8bc7c487	331	gpio_direction_input(IMX_GPIO_NR(4, 20));
7bcb983f FE	332	}
	333	#endif /* CONFIG_VIDEO_IPUV3 */
	334
e2d282a1 FE	335	int board_eth_init(bd_t *bis)
e2d282a1 FE	336	{
e2d282a1 FE	337	setup_iomux_enet();
e2d282a1 FE	338
14da759f	339	return cpu_eth_init(bis);
e2d282a1 FE	340	}
	341
	342	int board_early_init_f(void)
	343	{
	344	setup_iomux_uart();
7bcb983f FE	345	#if defined(CONFIG_VIDEO_IPUV3)
	346	setup_display();
	347	#endif
e2d282a1 FE	348	return 0;
	349	}
	350
7bcb983f FE	351	/*
	352	* Do not overwrite the console
	353	* Use always serial for U-Boot console
	354	*/
	355	int overwrite_console(void)
	356	{
	357	return 1;
	358	}
	359
eaffaa2d OS	360	#ifdef CONFIG_CMD_BMODE
	361	static const struct boot_mode board_boot_modes[] = {
	362	/* 4 bit bus width */
	363	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	364	{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	365	{NULL, 0},
	366	};
	367	#endif
	368
9a8804a8 FE	369	static bool is_revc1(void)
	370	{
	371	SETUP_IOMUX_PADS(rev_detection_pad);
	372	gpio_direction_input(REV_DETECTION);
	373
	374	if (gpio_get_value(REV_DETECTION))
	375	return true;
	376	else
	377	return false;
	378	}
	379
eaffaa2d OS	380	int board_late_init(void)
	381	{
	382	#ifdef CONFIG_CMD_BMODE
	383	add_board_boot_modes(board_boot_modes);
	384	#endif
	385
0d1ea052 FE	386	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	387	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D))
	388	setenv("board_rev", "MX6Q");
	389	else
	390	setenv("board_rev", "MX6DL");
9a8804a8 FE	391
	392	if (is_revc1())
	393	setenv("board_name", "C1");
	394	else
	395	setenv("board_name", "B1");
0d1ea052	396	#endif
eaffaa2d OS	397	return 0;
	398	}
	399
e2d282a1 FE	400	int board_init(void)
	401	{
	402	/* address of boot parameters */
	403	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	404
0d1ea052 FE	405	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
	406	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D))
	407	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
	408	else
	409	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
8bc7c487	410
e2d282a1 FE	411	return 0;
	412	}
	413
e2d282a1 FE	414	int checkboard(void)
e2d282a1 FE	415	{
9a8804a8 FE	416	if (is_revc1())
	417	puts("Board: Wandboard rev C1\n");
	418	else
	419	puts("Board: Wandboard rev B1\n");
e2d282a1 FE	420
	421	return 0;
	422	}