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Commit | Line | Data |
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ba56f625 | 1 | /* |
e0299076 | 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
1a459660 | 3 | * SPDX-License-Identifier: GPL-2.0+ |
ba56f625 WD |
4 | */ |
5 | ||
6 | #include <ppc_asm.tmpl> | |
cf6eb6da | 7 | #include <asm/mmu.h> |
ba56f625 | 8 | #include <config.h> |
550650dd | 9 | #include <asm/ppc4xx.h> |
ba56f625 | 10 | |
e0299076 | 11 | /* |
ba56f625 WD |
12 | * TLB TABLE |
13 | * | |
14 | * This table is used by the cpu boot code to setup the initial tlb | |
15 | * entries. Rather than make broad assumptions in the cpu source tree, | |
16 | * this table lets each board set things up however they like. | |
17 | * | |
e0299076 PT |
18 | * Pointer to the table is returned in r1 |
19 | */ | |
ba56f625 WD |
20 | |
21 | .section .bootpg,"ax" | |
22 | .globl tlbtab | |
23 | ||
24 | tlbtab: | |
25 | tlbtab_start | |
cf6eb6da SR |
26 | tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
27 | tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) | |
28 | tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) | |
29 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) | |
30 | tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) | |
31 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) | |
32 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) | |
ba56f625 | 33 | tlbtab_end |