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Commit | Line | Data |
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ba56f625 | 1 | /* |
e0299076 | 2 | * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> |
ba56f625 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ba56f625 WD |
5 | */ |
6 | ||
ba56f625 | 7 | #include <common.h> |
24b852a7 | 8 | #include <console.h> |
ba56f625 WD |
9 | #include <asm/processor.h> |
10 | #include <spd_sdram.h> | |
11 | #include <i2c.h> | |
d2567be9 | 12 | #include <net.h> |
ba56f625 | 13 | |
d87080b7 WD |
14 | DECLARE_GLOBAL_DATA_PTR; |
15 | ||
3c74e32a | 16 | int board_early_init_f(void) |
ba56f625 WD |
17 | { |
18 | unsigned long sdrreg; | |
e0299076 | 19 | |
b88da157 PT |
20 | /* |
21 | * Enable GPIO for pins 18 - 24 | |
22 | * 18 = SEEPROM_WP | |
23 | * 19 = #M_RST | |
24 | * 20 = #MONARCH | |
25 | * 21 = #LED_ALARM | |
26 | * 22 = #LED_ACT | |
27 | * 23 = #LED_STATUS1 | |
28 | * 24 = #LED_STATUS2 | |
29 | */ | |
d1c3b275 SR |
30 | mfsdr(SDR0_PFC0, sdrreg); |
31 | mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); | |
6d0f6bcf | 32 | out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); |
ba56f625 WD |
33 | LED0_OFF(); |
34 | LED1_OFF(); | |
35 | LED2_OFF(); | |
36 | LED3_OFF(); | |
37 | ||
e0299076 | 38 | /* Setup the external bus controller/chip selects */ |
d1c3b275 SR |
39 | mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ |
40 | mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ | |
41 | mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ | |
42 | mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ | |
43 | mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ | |
44 | mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ | |
45 | mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ | |
46 | mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ | |
ba56f625 | 47 | |
5de85140 | 48 | /* |
e0299076 PT |
49 | * Setup the interrupt controller polarities, triggers, etc. |
50 | * | |
5de85140 SR |
51 | * Because of the interrupt handling rework to handle 440GX interrupts |
52 | * with the common code, we needed to change names of the UIC registers. | |
53 | * Here the new relationship: | |
54 | * | |
55 | * U-Boot name 440GX name | |
56 | * ----------------------- | |
57 | * UIC0 UICB0 | |
58 | * UIC1 UIC0 | |
59 | * UIC2 UIC1 | |
60 | * UIC3 UIC2 | |
61 | */ | |
952e7760 SR |
62 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
63 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
64 | mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ | |
65 | mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ | |
66 | mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ | |
67 | mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ | |
68 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
e0299076 | 69 | |
952e7760 SR |
70 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
71 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
72 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
73 | mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ | |
74 | mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ | |
75 | mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ | |
76 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
e0299076 | 77 | |
952e7760 SR |
78 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ |
79 | mtdcr(UIC3ER, 0x00000000); /* disable all */ | |
80 | mtdcr(UIC3CR, 0x00000000); /* all non-critical */ | |
81 | mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ | |
82 | mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ | |
83 | mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ | |
84 | mtdcr(UIC3SR, 0xffffffff); /* clear all */ | |
e0299076 | 85 | |
952e7760 SR |
86 | mtdcr(UIC0SR, 0xfc000000); /* clear all */ |
87 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
88 | mtdcr(UIC0CR, 0x00000000); /* all non-critical */ | |
89 | mtdcr(UIC0PR, 0xfc000000); /* */ | |
90 | mtdcr(UIC0TR, 0x00000000); /* */ | |
91 | mtdcr(UIC0VR, 0x00000001); /* */ | |
ba56f625 WD |
92 | |
93 | LED0_ON(); | |
94 | ||
ba56f625 WD |
95 | return 0; |
96 | } | |
97 | ||
e0299076 | 98 | int checkboard(void) |
ba56f625 | 99 | { |
f0c0b3a9 WD |
100 | char buf[64]; |
101 | int i; | |
54381b79 PT |
102 | |
103 | printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME); | |
104 | printf(" "); | |
f0c0b3a9 WD |
105 | i = getenv_f("board_rev", buf, sizeof(buf)); |
106 | if (i > 0) | |
107 | printf("Rev %s, ", buf); | |
108 | i = getenv_f("serial#", buf, sizeof(buf)); | |
109 | if (i > 0) | |
110 | printf("Serial# %s, ", buf); | |
111 | i = getenv_f("board_cfg", buf, sizeof(buf)); | |
112 | if (i > 0) | |
113 | printf("Cfg %s", buf); | |
54381b79 | 114 | printf("\n"); |
ba56f625 | 115 | |
e0299076 | 116 | return 0; |
ba56f625 WD |
117 | } |
118 | ||
f1683aa7 | 119 | int dram_init(void) |
ba56f625 | 120 | { |
088454cd SG |
121 | gd->ram_size = spd_sdram(); |
122 | ||
123 | return 0; | |
ba56f625 | 124 | } |
ba56f625 | 125 | |
e0299076 | 126 | /* |
a760b020 SR |
127 | * Override weak pci_pre_init() |
128 | * | |
e0299076 PT |
129 | * This routine is called just prior to registering the hose and gives |
130 | * the board the opportunity to check things. Returning a value of zero | |
131 | * indicates that things are bad & PCI initialization should be aborted. | |
ba56f625 | 132 | * |
e0299076 PT |
133 | * Different boards may wish to customize the pci controller structure |
134 | * (add regions, override default access routines, etc) or perform | |
135 | * certain pre-initialization actions. | |
136 | */ | |
466fff1a | 137 | #if defined(CONFIG_PCI) |
e0299076 | 138 | int pci_pre_init(struct pci_controller * hose) |
ba56f625 WD |
139 | { |
140 | unsigned long strap; | |
e0299076 | 141 | |
3c74e32a | 142 | /* See if we're supposed to setup the pci */ |
d1c3b275 | 143 | mfsdr(SDR0_SDSTP1, strap); |
e0299076 PT |
144 | if ((strap & 0x00010000) == 0) |
145 | return 0; | |
ba56f625 | 146 | |
6d0f6bcf | 147 | #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) |
ddc922ff | 148 | /* Setup System Device Register PCIL0_XCR */ |
d1c3b275 | 149 | mfsdr(SDR0_XCR, strap); |
3c74e32a | 150 | strap &= 0x0f000000; |
d1c3b275 | 151 | mtsdr(SDR0_XCR, strap); |
3c74e32a | 152 | #endif |
e0299076 | 153 | |
ba56f625 WD |
154 | return 1; |
155 | } | |
466fff1a | 156 | #endif /* defined(CONFIG_PCI) */ |
ba56f625 | 157 | |
e0299076 PT |
158 | #if defined(CONFIG_PCI) |
159 | /* | |
9a81c612 SR |
160 | * Override weak is_pci_host() |
161 | * | |
e0299076 PT |
162 | * This routine is called to determine if a pci scan should be |
163 | * performed. With various hardware environments (especially cPCI and | |
164 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
165 | * bit in the strap register, or generic host/adapter assumptions. | |
ba56f625 | 166 | * |
e0299076 PT |
167 | * Rather than hard-code a bad assumption in the general 440 code, the |
168 | * 440 pci code requires the board to decide at runtime. | |
ba56f625 | 169 | * |
e0299076 PT |
170 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
171 | */ | |
ba56f625 WD |
172 | int is_pci_host(struct pci_controller *hose) |
173 | { | |
6d0f6bcf | 174 | return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); |
ba56f625 WD |
175 | } |
176 | #endif /* defined(CONFIG_PCI) */ | |
177 | ||
178 | #ifdef CONFIG_POST | |
179 | /* | |
180 | * Returns 1 if keys pressed to start the power-on long-running tests | |
181 | * Called from board_init_f(). | |
182 | */ | |
183 | int post_hotkeys_pressed(void) | |
184 | { | |
e0299076 | 185 | return ctrlc(); |
ba56f625 | 186 | } |
e0299076 | 187 | #endif |