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76316a31 MS |
1 | /* |
2 | * (C) Copyright 2007 Michal Simek | |
3 | * | |
4 | * Michal SIMEK <monstr@monstr.eu> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
76316a31 MS |
7 | */ |
8 | ||
9 | /* This is a board specific file. It's OK to include board specific | |
10 | * header files */ | |
11 | ||
12 | #include <common.h> | |
342cd097 | 13 | #include <config.h> |
e945f6dc | 14 | #include <fdtdec.h> |
2380b8f5 | 15 | #include <asm/processor.h> |
19bf1fba MS |
16 | #include <asm/microblaze_intc.h> |
17 | #include <asm/asm.h> | |
4e779ad2 MS |
18 | #include <asm/gpio.h> |
19 | ||
e945f6dc MS |
20 | DECLARE_GLOBAL_DATA_PTR; |
21 | ||
4e779ad2 MS |
22 | #ifdef CONFIG_XILINX_GPIO |
23 | static int reset_pin = -1; | |
24 | #endif | |
76316a31 | 25 | |
e945f6dc MS |
26 | ulong ram_base; |
27 | ||
28 | void dram_init_banksize(void) | |
29 | { | |
30 | gd->bd->bi_dram[0].start = ram_base; | |
31 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
32 | } | |
33 | ||
34 | int dram_init(void) | |
35 | { | |
36 | int node; | |
37 | fdt_addr_t addr; | |
38 | fdt_size_t size; | |
39 | const void *blob = gd->fdt_blob; | |
40 | ||
41 | node = fdt_node_offset_by_prop_value(blob, -1, "device_type", | |
42 | "memory", 7); | |
43 | if (node == -FDT_ERR_NOTFOUND) { | |
44 | debug("DRAM: Can't get memory node\n"); | |
45 | return 1; | |
46 | } | |
47 | addr = fdtdec_get_addr_size(blob, node, "reg", &size); | |
48 | if (addr == FDT_ADDR_T_NONE || size == 0) { | |
49 | debug("DRAM: Can't get base address or size\n"); | |
50 | return 1; | |
51 | } | |
52 | ram_base = addr; | |
53 | ||
54 | gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ | |
55 | gd->ram_size = size; | |
56 | ||
57 | return 0; | |
58 | }; | |
e945f6dc | 59 | |
882b7d72 | 60 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
76316a31 | 61 | { |
b5e9b9a9 | 62 | #ifndef CONFIG_SPL_BUILD |
4e779ad2 MS |
63 | #ifdef CONFIG_XILINX_GPIO |
64 | if (reset_pin != -1) | |
65 | gpio_direction_output(reset_pin, 1); | |
76316a31 | 66 | #endif |
b364727a | 67 | |
0f21f98d MS |
68 | #ifdef CONFIG_XILINX_TB_WATCHDOG |
69 | hw_watchdog_disable(); | |
70 | #endif | |
b5e9b9a9 | 71 | #endif |
76316a31 | 72 | puts ("Reseting board\n"); |
8848668e MS |
73 | __asm__ __volatile__ (" mts rmsr, r0;" \ |
74 | "bra r0"); | |
b364727a | 75 | |
882b7d72 | 76 | return 0; |
76316a31 MS |
77 | } |
78 | ||
38c4761c | 79 | static int gpio_init(void) |
76316a31 | 80 | { |
4e779ad2 MS |
81 | #ifdef CONFIG_XILINX_GPIO |
82 | reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); | |
83 | if (reset_pin != -1) | |
84 | gpio_request(reset_pin, "reset_pin"); | |
76316a31 MS |
85 | #endif |
86 | return 0; | |
87 | } | |
19bf1fba | 88 | |
38c4761c | 89 | int board_late_init(void) |
2380b8f5 MS |
90 | { |
91 | gpio_init(); | |
38c4761c MS |
92 | |
93 | return 0; | |
2380b8f5 | 94 | } |