[people/ms/u-boot.git] / board / xilinx / ppc405-generic / xparameters.h

/*
 * (C) Copyright 2008
 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
 * This work has been supported by: QTechnology  http://qtec.com/
 * based on xparameters-ml507.h by Xilinx
 *
 * SPDX-License-Identifier:	GPL-2.0+
*/

#ifndef XPARAMETER_H
#define XPARAMETER_H

#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
#define XPAR_INTC_0_BASEADDR		0x81800000
#define XPAR_SPI_0_BASEADDR             0x83400000
#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
#define XPAR_SPI_0_NUM_TRANSFER_BITS	8
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000

#endif
Commit	Line	Data
1f4d5326 RR	1	/*
1f4d5326 RR	2	* (C) Copyright 2008
5b218ae1	3	* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
1f4d5326 RR	4	* This work has been supported by: QTechnology http://qtec.com/
	5	* based on xparameters-ml507.h by Xilinx
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
1f4d5326 RR	8	*/
	9
	10	#ifndef XPARAMETER_H
	11	#define XPARAMETER_H
	12
	13	#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
	14	#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
	15	#define XPAR_INTC_0_BASEADDR 0x81800000
	16	#define XPAR_SPI_0_BASEADDR 0x83400000
1f4d5326 RR	17	#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
	18	#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
	19	#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
6a2c1aaa	20	#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
1f4d5326	21	#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
6a2c1aaa	22	#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
1f4d5326 RR	23
1f4d5326 RR	24	#endif