[people/ms/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	u32 ver;
	char *name;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x10,
		.ver = 0x2c,
		.name = "3cg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x11,
		.ver = 0x2c,
		.name = "2cg",
	},
	{
		.id = 0x20,
		.name = "5ev",
	},
	{
		.id = 0x20,
		.ver = 0x100,
		.name = "5eg",
	},
	{
		.id = 0x20,
		.ver = 0x12c,
		.name = "5cg",
	},
	{
		.id = 0x21,
		.name = "4ev",
	},
	{
		.id = 0x21,
		.ver = 0x100,
		.name = "4eg",
	},
	{
		.id = 0x21,
		.ver = 0x12c,
		.name = "4cg",
	},
	{
		.id = 0x30,
		.name = "7ev",
	},
	{
		.id = 0x30,
		.ver = 0x100,
		.name = "7eg",
	},
	{
		.id = 0x30,
		.ver = 0x12c,
		.name = "7cg",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x38,
		.ver = 0x2c,
		.name = "9cg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x39,
		.ver = 0x2c,
		.name = "6cg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{ /* For testing purpose only */
		.id = 0x50,
		.ver = 0x2c,
		.name = "15cg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
	{
		.id = 0x61,
		.name = "21dr",
	},
	{
		.id = 0x63,
		.name = "23dr",
	},
	{
		.id = 0x65,
		.name = "25dr",
	},
	{
		.id = 0x64,
		.name = "27dr",
	},
	{
		.id = 0x60,
		.name = "28dr",
	},
	{
		.id = 0x62,
		.name = "29dr",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 * regs[1][63:32] = CSU.IDCODE2 register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		case IDCODE2:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id, ver;

	id = chip_id(IDCODE);
	ver = chip_id(IDCODE2);

	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
			return zynqmp_devices[i].name;
	}
	return "unknown";
}
#endif

int board_early_init_f(void)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	zynqmp_pmufw_version();
#endif

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	psu_init();
#endif

	return 0;
}

#define ZYNQMP_VERSION_SIZE	9

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		static char version[ZYNQMP_VERSION_SIZE];

		strncat(version, "xczu", 4);
		zynqmppl.name = strncat(version,
					zynqmp_get_silicon_idcode_name(),
					ZYNQMP_VERSION_SIZE - 5);
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (current_el() == 3 && !val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	return fdtdec_setup_memory_banksize();
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	const char *mode;
	char *new_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	reg = readl(&crlapb_base->boot_mode);
	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		mode = "mmc0";
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		mode = "mmc1";
#else
		mode = "mmc0";
#endif
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	new_targets = calloc(1, strlen(mode) +
				strlen(env_get("boot_targets")) + 2);

	sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
	env_set("boot_targets", new_targets);

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data0 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

static struct dwc3_device dwc3_device_data1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(index);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	debug("%s: index %x\n", __func__, index);

#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
#endif

	switch (index) {
	case 0:
		return dwc3_uboot_init(&dwc3_device_data0);
	case 1:
		return dwc3_uboot_init(&dwc3_device_data1);
	};

	return -1;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
679b994a	9	#include <sata.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
b72894f1	12	#include <malloc.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/io.h>
16fa00a7 SDPP	17	#include <usb.h>
16fa00a7 SDPP	18	#include <dwc3-uboot.h>
47e60cbd	19	#include <zynqmppl.h>
6919b4bf	20	#include <i2c.h>
9feff385	21	#include <g_dnl.h>
84c7204b MS	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
47e60cbd MS	25	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	26	!defined(CONFIG_SPL_BUILD)
	27	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	28
	29	static const struct {
8ebdf9ef	30	u32 id;
494fffe7	31	u32 ver;
47e60cbd MS	32	char *name;
	33	} zynqmp_devices[] = {
	34	{
	35	.id = 0x10,
	36	.name = "3eg",
	37	},
494fffe7 MS	38	{
	39	.id = 0x10,
	40	.ver = 0x2c,
	41	.name = "3cg",
	42	},
47e60cbd MS	43	{
	44	.id = 0x11,
	45	.name = "2eg",
	46	},
494fffe7 MS	47	{
	48	.id = 0x11,
	49	.ver = 0x2c,
	50	.name = "2cg",
	51	},
47e60cbd MS	52	{
	53	.id = 0x20,
	54	.name = "5ev",
	55	},
494fffe7 MS	56	{
	57	.id = 0x20,
	58	.ver = 0x100,
	59	.name = "5eg",
	60	},
	61	{
	62	.id = 0x20,
	63	.ver = 0x12c,
	64	.name = "5cg",
	65	},
47e60cbd MS	66	{
	67	.id = 0x21,
	68	.name = "4ev",
	69	},
494fffe7 MS	70	{
	71	.id = 0x21,
	72	.ver = 0x100,
	73	.name = "4eg",
	74	},
	75	{
	76	.id = 0x21,
	77	.ver = 0x12c,
	78	.name = "4cg",
	79	},
47e60cbd MS	80	{
	81	.id = 0x30,
	82	.name = "7ev",
	83	},
494fffe7 MS	84	{
	85	.id = 0x30,
	86	.ver = 0x100,
	87	.name = "7eg",
	88	},
	89	{
	90	.id = 0x30,
	91	.ver = 0x12c,
	92	.name = "7cg",
	93	},
47e60cbd MS	94	{
	95	.id = 0x38,
	96	.name = "9eg",
	97	},
494fffe7 MS	98	{
	99	.id = 0x38,
	100	.ver = 0x2c,
	101	.name = "9cg",
	102	},
47e60cbd MS	103	{
	104	.id = 0x39,
	105	.name = "6eg",
	106	},
494fffe7 MS	107	{
	108	.id = 0x39,
	109	.ver = 0x2c,
	110	.name = "6cg",
	111	},
47e60cbd MS	112	{
	113	.id = 0x40,
	114	.name = "11eg",
	115	},
494fffe7 MS	116	{ /* For testing purpose only */
	117	.id = 0x50,
	118	.ver = 0x2c,
	119	.name = "15cg",
	120	},
47e60cbd MS	121	{
	122	.id = 0x50,
	123	.name = "15eg",
	124	},
	125	{
	126	.id = 0x58,
	127	.name = "19eg",
	128	},
	129	{
	130	.id = 0x59,
	131	.name = "17eg",
	132	},
b030fedf MS	133	{
	134	.id = 0x61,
	135	.name = "21dr",
	136	},
	137	{
	138	.id = 0x63,
	139	.name = "23dr",
	140	},
	141	{
	142	.id = 0x65,
	143	.name = "25dr",
	144	},
	145	{
	146	.id = 0x64,
	147	.name = "27dr",
	148	},
	149	{
	150	.id = 0x60,
	151	.name = "28dr",
	152	},
	153	{
	154	.id = 0x62,
	155	.name = "29dr",
	156	},
47e60cbd	157	};
74ba69db	158	#endif
47e60cbd	159
f52bf5a3	160	int chip_id(unsigned char id)
47e60cbd MS	161	{
47e60cbd MS	162	struct pt_regs regs;
db3123b4	163	int val = -EINVAL;
47e60cbd	164
74ba69db SDPP	165	if (current_el() != 3) {
	166	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	167	regs.regs[1] = 0;
	168	regs.regs[2] = 0;
	169	regs.regs[3] = 0;
	170
	171	smc_call(&regs);
	172
	173	/*
	174	* SMC returns:
	175	* regs[0][31:0] = status of the operation
	176	* regs[0][63:32] = CSU.IDCODE register
	177	* regs[1][31:0] = CSU.version register
494fffe7	178	* regs[1][63:32] = CSU.IDCODE2 register
74ba69db SDPP	179	*/
	180	switch (id) {
	181	case IDCODE:
	182	regs.regs[0] = upper_32_bits(regs.regs[0]);
	183	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	184	ZYNQMP_CSU_IDCODE_SVD_MASK;
	185	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	186	val = regs.regs[0];
	187	break;
	188	case VERSION:
	189	regs.regs[1] = lower_32_bits(regs.regs[1]);
	190	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	191	val = regs.regs[1];
	192	break;
494fffe7 MS	193	case IDCODE2:
	194	regs.regs[1] = lower_32_bits(regs.regs[1]);
	195	regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
	196	val = regs.regs[1];
	197	break;
74ba69db SDPP	198	default:
	199	printf("%s, Invalid Req:0x%x\n", __func__, id);
	200	}
	201	} else {
	202	switch (id) {
	203	case IDCODE:
	204	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	205	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	206	ZYNQMP_CSU_IDCODE_SVD_MASK;
	207	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	208	break;
	209	case VERSION:
	210	val = readl(ZYNQMP_CSU_VER_ADDR);
	211	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	212	break;
	213	default:
	214	printf("%s, Invalid Req:0x%x\n", __func__, id);
	215	}
db3123b4	216	}
0cba6abb	217
db3123b4	218	return val;
47e60cbd MS	219	}
47e60cbd MS	220
74ba69db SDPP	221	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	222	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	223	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	224	{
494fffe7	225	u32 i, id, ver;
47e60cbd	226
db3123b4	227	id = chip_id(IDCODE);
494fffe7 MS	228	ver = chip_id(IDCODE2);
494fffe7 MS	229
47e60cbd	230	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
494fffe7	231	if (zynqmp_devices[i].id == id && zynqmp_devices[i].ver == ver)
47e60cbd MS	232	return zynqmp_devices[i].name;
	233	}
	234	return "unknown";
	235	}
	236	#endif
	237
fb4000e8 MS	238	int board_early_init_f(void)
	239	{
	240	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	241	zynqmp_pmufw_version();
	242	#endif
55de0929	243
fd1b635c	244	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
55de0929 MS	245	psu_init();
	246	#endif
	247
fb4000e8 MS	248	return 0;
	249	}
	250
47e60cbd MS	251	#define ZYNQMP_VERSION_SIZE 9
47e60cbd MS	252
84c7204b MS	253	int board_init(void)
84c7204b MS	254	{
a0736efb MS	255	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	256
47e60cbd MS	257	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	258	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	259	defined(CONFIG_SPL_BUILD))
	260	if (current_el() != 3) {
	261	static char version[ZYNQMP_VERSION_SIZE];
	262
df1cd46f	263	strncat(version, "xczu", 4);
47e60cbd MS	264	zynqmppl.name = strncat(version,
47e60cbd MS	265	zynqmp_get_silicon_idcode_name(),
df1cd46f	266	ZYNQMP_VERSION_SIZE - 5);
47e60cbd MS	267	printf("Chip ID:\t%s\n", zynqmppl.name);
	268	fpga_init();
	269	fpga_add(fpga_xilinx, &zynqmppl);
	270	}
	271	#endif
	272
84c7204b MS	273	return 0;
	274	}
	275
	276	int board_early_init_r(void)
	277	{
	278	u32 val;
	279
90a35db4 MS	280	val = readl(&crlapb_base->timestamp_ref_ctrl);
	281	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	282
	283	if (current_el() == 3 && !val) {
0785dfd8 MS	284	val = readl(&crlapb_base->timestamp_ref_ctrl);
	285	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	286	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	287
0785dfd8 MS	288	/* Program freq register in System counter */
	289	writel(zynqmp_get_system_timer_freq(),
	290	&iou_scntr_secure->base_frequency_id_register);
	291	/* And enable system counter */
	292	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	293	&iou_scntr_secure->counter_control_register);
	294	}
84c7204b MS	295	return 0;
	296	}
	297
6919b4bf MS	298	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	299	{
	300	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	301	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	302	defined(CONFIG_ZYNQ_EEPROM_BUS)
	303	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	304
	305	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	306	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	307	ethaddr, 6))
	308	printf("I2C EEPROM MAC address read failed\n");
	309	#endif
	310
	311	return 0;
	312	}
	313
8d59d7f6	314	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	315	int dram_init_banksize(void)
361a8799	316	{
da3f003b	317	return fdtdec_setup_memory_banksize();
8a5db0ab	318	}
8d59d7f6	319
361a8799	320	int dram_init(void)
8a5db0ab	321	{
950f86ca NR	322	if (fdtdec_setup_memory_size() != 0)
950f86ca NR	323	return -EINVAL;
8a5db0ab	324
361a8799	325	return 0;
8d59d7f6 MS	326	}
8d59d7f6 MS	327	#else
84c7204b MS	328	int dram_init(void)
	329	{
	330	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	331
	332	return 0;
	333	}
8d59d7f6	334	#endif
84c7204b	335
84c7204b MS	336	void reset_cpu(ulong addr)
	337	{
	338	}
	339
84c7204b MS	340	int board_late_init(void)
	341	{
	342	u32 reg = 0;
	343	u8 bootmode;
b72894f1 MS	344	const char *mode;
	345	char *new_targets;
	346
	347	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	348	debug("Saved variables - Skipping\n");
	349	return 0;
	350	}
84c7204b MS	351
84c7204b MS	352	reg = readl(&crlapb_base->boot_mode);
47359a03 MS	353	if (reg >> BOOT_MODE_ALT_SHIFT)
	354	reg >>= BOOT_MODE_ALT_SHIFT;
	355
84c7204b MS	356	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	357
fb90917c	358	puts("Bootmode: ");
84c7204b	359	switch (bootmode) {
d58fc12e MS	360	case USB_MODE:
	361	puts("USB_MODE\n");
	362	mode = "usb";
	363	break;
0a5bcc8c	364	case JTAG_MODE:
fb90917c	365	puts("JTAG_MODE\n");
b72894f1	366	mode = "pxe dhcp";
0a5bcc8c SDPP	367	break;
	368	case QSPI_MODE_24BIT:
	369	case QSPI_MODE_32BIT:
b72894f1	370	mode = "qspi0";
fb90917c	371	puts("QSPI_MODE\n");
0a5bcc8c	372	break;
39c56f55	373	case EMMC_MODE:
78678fee	374	puts("EMMC_MODE\n");
b72894f1	375	mode = "mmc0";
78678fee MS	376	break;
78678fee MS	377	case SD_MODE:
fb90917c	378	puts("SD_MODE\n");
b72894f1	379	mode = "mmc0";
84c7204b	380	break;
e1992276 SDPP	381	case SD1_LSHFT_MODE:
	382	puts("LVL_SHFT_");
	383	/* fall through */
af813acd	384	case SD_MODE1:
fb90917c	385	puts("SD_MODE1\n");
2d9925bc	386	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
b72894f1 MS	387	mode = "mmc1";
	388	#else
	389	mode = "mmc0";
2d9925bc	390	#endif
af813acd MS	391	break;
af813acd MS	392	case NAND_MODE:
fb90917c	393	puts("NAND_MODE\n");
b72894f1	394	mode = "nand0";
af813acd	395	break;
84c7204b	396	default:
b72894f1	397	mode = "";
84c7204b MS	398	printf("Invalid Boot Mode:0x%x\n", bootmode);
	399	break;
	400	}
	401
b72894f1 MS	402	/*
	403	* One terminating char + one byte for space between mode
	404	* and default boot_targets
	405	*/
	406	new_targets = calloc(1, strlen(mode) +
00caae6d	407	strlen(env_get("boot_targets")) + 2);
b72894f1	408
00caae6d	409	sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
382bee57	410	env_set("boot_targets", new_targets);
b72894f1	411
84c7204b MS	412	return 0;
84c7204b MS	413	}
84696ff5 SDPP	414
	415	int checkboard(void)
	416	{
5af08556	417	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	418	return 0;
84696ff5 SDPP	419	}
16fa00a7 SDPP	420
16fa00a7 SDPP	421	#ifdef CONFIG_USB_DWC3
275bd6d1	422	static struct dwc3_device dwc3_device_data0 = {
16fa00a7 SDPP	423	.maximum_speed = USB_SPEED_HIGH,
	424	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	425	.dr_mode = USB_DR_MODE_PERIPHERAL,
	426	.index = 0,
	427	};
	428
275bd6d1 MS	429	static struct dwc3_device dwc3_device_data1 = {
	430	.maximum_speed = USB_SPEED_HIGH,
	431	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	432	.dr_mode = USB_DR_MODE_PERIPHERAL,
	433	.index = 1,
	434	};
	435
9feff385	436	int usb_gadget_handle_interrupts(int index)
16fa00a7	437	{
9feff385	438	dwc3_uboot_handle_interrupt(index);
16fa00a7 SDPP	439	return 0;
	440	}
	441
	442	int board_usb_init(int index, enum usb_init_type init)
	443	{
275bd6d1 MS	444	debug("%s: index %x\n", __func__, index);
275bd6d1 MS	445
8ecd50c8 MS	446	#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	447	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
	448	#endif
	449
275bd6d1 MS	450	switch (index) {
	451	case 0:
	452	return dwc3_uboot_init(&dwc3_device_data0);
	453	case 1:
	454	return dwc3_uboot_init(&dwc3_device_data1);
	455	};
	456
	457	return -1;
16fa00a7 SDPP	458	}
	459
	460	int board_usb_cleanup(int index, enum usb_init_type init)
	461	{
	462	dwc3_uboot_exit(index);
	463	return 0;
	464	}
	465	#endif