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81a8824f 1/*
3f4978c7
HS
2 * (C) Copyright 2009
3 * Sergey Kubushyn, himself, ksi@koi8.net
4 *
5 * Changes for unified multibus/multiadapter I2C support.
6 *
81a8824f
WD
7 * (C) Copyright 2001
8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
81a8824f
WD
11 */
12
13/*
14 * I2C Functions similar to the standard memory functions.
15 *
16 * There are several parameters in many of the commands that bear further
17 * explanations:
18 *
81a8824f
WD
19 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
20 * Each I2C chip on the bus has a unique address. On the I2C data bus,
21 * the address is the upper seven bits and the LSB is the "read/write"
22 * bit. Note that the {i2c_chip} address specified on the command
23 * line is not shifted up: e.g. a typical EEPROM memory chip may have
24 * an I2C address of 0x50, but the data put on the bus will be 0xA0
25 * for write and 0xA1 for read. This "non shifted" address notation
26 * matches at least half of the data sheets :-/.
27 *
28 * {addr} is the address (or offset) within the chip. Small memory
29 * chips have 8 bit addresses. Large memory chips have 16 bit
30 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
31 * Many non-memory chips have multiple registers and {addr} is used
32 * as the register index. Some non-memory chips have only one register
33 * and therefore don't need any {addr} parameter.
34 *
35 * The default {addr} parameter is one byte (.1) which works well for
36 * memories and registers with 8 bits of address space.
37 *
38 * You can specify the length of the {addr} field with the optional .0,
39 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
40 * manipulating a single register device which doesn't use an address
41 * field, use "0.0" for the address and the ".0" length field will
42 * suppress the address in the I2C data stream. This also works for
43 * successive reads using the I2C auto-incrementing memory pointer.
44 *
45 * If you are manipulating a large memory with 2-byte addresses, use
46 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
47 *
48 * Then there are the unfortunate memory chips that spill the most
49 * significant 1, 2, or 3 bits of address into the chip address byte.
50 * This effectively makes one chip (logically) look like 2, 4, or
51 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 52 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
53 * {addr} field (since .1 is the default, it doesn't actually have to
54 * be specified). Examples: given a memory chip at I2C chip address
55 * 0x50, the following would happen...
0f89c54b 56 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 57 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 58 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 59 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 60 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
61 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
62 * This is awfully ugly. It would be nice if someone would think up
63 * a better way of handling this.
64 *
65 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
66 */
67
68#include <common.h>
0098e179 69#include <bootretry.h>
18d66533 70#include <cli.h>
81a8824f 71#include <command.h>
24b852a7 72#include <console.h>
63656b76 73#include <dm.h>
735987c5 74#include <edid.h>
67b23a32 75#include <environment.h>
63656b76 76#include <errno.h>
81a8824f 77#include <i2c.h>
67b23a32 78#include <malloc.h>
81a8824f 79#include <asm/byteorder.h>
2515d843 80#include <linux/compiler.h>
81a8824f 81
3f4978c7
HS
82DECLARE_GLOBAL_DATA_PTR;
83
81a8824f
WD
84/* Display values from last command.
85 * Memory modify remembered values are different from display memory.
86 */
5468461d 87static uint i2c_dp_last_chip;
81a8824f
WD
88static uint i2c_dp_last_addr;
89static uint i2c_dp_last_alen;
90static uint i2c_dp_last_length = 0x10;
91
5468461d 92static uint i2c_mm_last_chip;
81a8824f
WD
93static uint i2c_mm_last_addr;
94static uint i2c_mm_last_alen;
95
bb99ad6d
BW
96/* If only one I2C bus is present, the list of devices to ignore when
97 * the probe command is issued is represented by a 1D array of addresses.
98 * When multiple buses are present, the list is an array of bus-address
99 * pairs. The following macros take care of this */
100
6d0f6bcf 101#if defined(CONFIG_SYS_I2C_NOPROBES)
9a2accb4 102#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
bb99ad6d
BW
103static struct
104{
105 uchar bus;
106 uchar addr;
6d0f6bcf 107} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
108#define GET_BUS_NUM i2c_get_bus_num()
109#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
110#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
111#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
112#else /* single bus */
6d0f6bcf 113static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
114#define GET_BUS_NUM 0
115#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
116#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
117#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
3f4978c7 118#endif /* defined(CONFIG_SYS_I2C) */
67b23a32
HS
119#endif
120
a266fe95
FM
121#define DISP_LINE_LEN 16
122
63656b76
SG
123/*
124 * Default for driver model is to use the chip's existing address length.
125 * For legacy code, this is not stored, so we need to use a suitable
126 * default.
127 */
128#ifdef CONFIG_DM_I2C
129#define DEFAULT_ADDR_LEN (-1)
130#else
131#define DEFAULT_ADDR_LEN 1
132#endif
133
134#ifdef CONFIG_DM_I2C
135static struct udevice *i2c_cur_bus;
136
f9a4c2da 137static int cmd_i2c_set_bus_num(unsigned int busnum)
63656b76
SG
138{
139 struct udevice *bus;
140 int ret;
141
142 ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
143 if (ret) {
144 debug("%s: No bus %d\n", __func__, busnum);
145 return ret;
146 }
147 i2c_cur_bus = bus;
148
149 return 0;
150}
151
152static int i2c_get_cur_bus(struct udevice **busp)
153{
e46f8a33
LM
154#ifdef CONFIG_I2C_SET_DEFAULT_BUS_NUM
155 if (!i2c_cur_bus) {
156 if (cmd_i2c_set_bus_num(CONFIG_I2C_DEFAULT_BUS_NUMBER)) {
157 printf("Default I2C bus %d not found\n",
158 CONFIG_I2C_DEFAULT_BUS_NUMBER);
159 return -ENODEV;
160 }
161 }
162#endif
163
63656b76
SG
164 if (!i2c_cur_bus) {
165 puts("No I2C bus selected\n");
166 return -ENODEV;
167 }
168 *busp = i2c_cur_bus;
169
170 return 0;
171}
172
173static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
174{
175 struct udevice *bus;
176 int ret;
177
178 ret = i2c_get_cur_bus(&bus);
179 if (ret)
180 return ret;
181
25ab4b03 182 return i2c_get_chip(bus, chip_addr, 1, devp);
63656b76
SG
183}
184
185#endif
186
06afa388
MV
187/**
188 * i2c_init_board() - Board-specific I2C bus init
189 *
190 * This function is the default no-op implementation of I2C bus
62a3b7dd 191 * initialization. This function can be overridden by board-specific
06afa388
MV
192 * implementation if needed.
193 */
2515d843
MV
194__weak
195void i2c_init_board(void)
c649dda5 196{
c649dda5 197}
c649dda5 198
655b34a7 199/* TODO: Implement architecture-specific get/set functions */
06afa388
MV
200
201/**
202 * i2c_get_bus_speed() - Return I2C bus speed
203 *
204 * This function is the default implementation of function for retrieveing
205 * the current I2C bus speed in Hz.
206 *
207 * A driver implementing runtime switching of I2C bus speed must override
208 * this function to report the speed correctly. Simple or legacy drivers
209 * can use this fallback.
210 *
211 * Returns I2C bus speed in Hz.
212 */
63656b76 213#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
3f4978c7
HS
214/*
215 * TODO: Implement architecture-specific get/set functions
216 * Should go away, if we switched completely to new multibus support
217 */
2515d843
MV
218__weak
219unsigned int i2c_get_bus_speed(void)
655b34a7
PT
220{
221 return CONFIG_SYS_I2C_SPEED;
222}
655b34a7 223
06afa388
MV
224/**
225 * i2c_set_bus_speed() - Configure I2C bus speed
226 * @speed: Newly set speed of the I2C bus in Hz
227 *
228 * This function is the default implementation of function for setting
229 * the I2C bus speed in Hz.
230 *
231 * A driver implementing runtime switching of I2C bus speed must override
232 * this function to report the speed correctly. Simple or legacy drivers
233 * can use this fallback.
234 *
235 * Returns zero on success, negative value on error.
236 */
2515d843
MV
237__weak
238int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
239{
240 if (speed != CONFIG_SYS_I2C_SPEED)
241 return -1;
242
243 return 0;
244}
3f4978c7 245#endif
655b34a7 246
06afa388
MV
247/**
248 * get_alen() - Small parser helper function to get address length
249 *
250 * Returns the address length.
2c0dc990 251 */
63656b76 252static uint get_alen(char *arg, int default_len)
2c0dc990
FM
253{
254 int j;
255 int alen;
256
63656b76 257 alen = default_len;
2c0dc990
FM
258 for (j = 0; j < 8; j++) {
259 if (arg[j] == '.') {
260 alen = arg[j+1] - '0';
2c0dc990
FM
261 break;
262 } else if (arg[j] == '\0')
263 break;
264 }
265 return alen;
266}
267
c1a6f371
SG
268enum i2c_err_op {
269 I2C_ERR_READ,
270 I2C_ERR_WRITE,
271};
272
273static int i2c_report_err(int ret, enum i2c_err_op op)
274{
275 printf("Error %s the chip: %d\n",
276 op == I2C_ERR_READ ? "reading" : "writing", ret);
277
278 return CMD_RET_FAILURE;
279}
280
06afa388
MV
281/**
282 * do_i2c_read() - Handle the "i2c read" command-line command
283 * @cmdtp: Command data struct pointer
284 * @flag: Command flag
285 * @argc: Command-line argument count
286 * @argv: Array of command-line arguments
287 *
288 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
289 * on error.
290 *
652e5354
FM
291 * Syntax:
292 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
293 */
54841ab5 294static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
652e5354 295{
5468461d 296 uint chip;
63656b76
SG
297 uint devaddr, length;
298 int alen;
652e5354 299 u_char *memaddr;
63656b76
SG
300 int ret;
301#ifdef CONFIG_DM_I2C
302 struct udevice *dev;
303#endif
652e5354 304
47e26b1b 305 if (argc != 5)
4c12eeb8 306 return CMD_RET_USAGE;
652e5354
FM
307
308 /*
309 * I2C chip address
310 */
311 chip = simple_strtoul(argv[1], NULL, 16);
312
313 /*
314 * I2C data address within the chip. This can be 1 or
315 * 2 bytes long. Some day it might be 3 bytes long :-).
316 */
317 devaddr = simple_strtoul(argv[2], NULL, 16);
63656b76 318 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 319 if (alen > 3)
4c12eeb8 320 return CMD_RET_USAGE;
652e5354
FM
321
322 /*
323 * Length is the number of objects, not number of bytes.
324 */
325 length = simple_strtoul(argv[3], NULL, 16);
326
327 /*
328 * memaddr is the address where to store things in memory
329 */
330 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
331
63656b76
SG
332#ifdef CONFIG_DM_I2C
333 ret = i2c_get_cur_bus_chip(chip, &dev);
334 if (!ret && alen != -1)
335 ret = i2c_set_chip_offset_len(dev, alen);
336 if (!ret)
f9a4c2da 337 ret = dm_i2c_read(dev, devaddr, memaddr, length);
63656b76
SG
338#else
339 ret = i2c_read(chip, devaddr, alen, memaddr, length);
340#endif
341 if (ret)
342 return i2c_report_err(ret, I2C_ERR_READ);
343
652e5354
FM
344 return 0;
345}
346
ff5d2dce
YS
347static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
348{
5468461d 349 uint chip;
63656b76
SG
350 uint devaddr, length;
351 int alen;
ff5d2dce 352 u_char *memaddr;
63656b76
SG
353 int ret;
354#ifdef CONFIG_DM_I2C
355 struct udevice *dev;
ed16f146 356 struct dm_i2c_chip *i2c_chip;
63656b76 357#endif
ff5d2dce 358
ed16f146 359 if ((argc < 5) || (argc > 6))
ff5d2dce
YS
360 return cmd_usage(cmdtp);
361
362 /*
363 * memaddr is the address where to store things in memory
364 */
365 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
366
367 /*
368 * I2C chip address
369 */
370 chip = simple_strtoul(argv[2], NULL, 16);
371
372 /*
373 * I2C data address within the chip. This can be 1 or
374 * 2 bytes long. Some day it might be 3 bytes long :-).
375 */
376 devaddr = simple_strtoul(argv[3], NULL, 16);
63656b76 377 alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
ff5d2dce
YS
378 if (alen > 3)
379 return cmd_usage(cmdtp);
380
381 /*
ed16f146 382 * Length is the number of bytes.
ff5d2dce
YS
383 */
384 length = simple_strtoul(argv[4], NULL, 16);
385
63656b76
SG
386#ifdef CONFIG_DM_I2C
387 ret = i2c_get_cur_bus_chip(chip, &dev);
388 if (!ret && alen != -1)
389 ret = i2c_set_chip_offset_len(dev, alen);
390 if (ret)
391 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
392 i2c_chip = dev_get_parent_platdata(dev);
393 if (!i2c_chip)
394 return i2c_report_err(ret, I2C_ERR_WRITE);
63656b76
SG
395#endif
396
ed16f146
LP
397 if (argc == 6 && !strcmp(argv[5], "-s")) {
398 /*
399 * Write all bytes in a single I2C transaction. If the target
400 * device is an EEPROM, it is your responsibility to not cross
401 * a page boundary. No write delay upon completion, take this
402 * into account if linking commands.
403 */
63656b76 404#ifdef CONFIG_DM_I2C
ed16f146
LP
405 i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
406 ret = dm_i2c_write(dev, devaddr, memaddr, length);
63656b76 407#else
ed16f146 408 ret = i2c_write(chip, devaddr, alen, memaddr, length);
63656b76
SG
409#endif
410 if (ret)
411 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
412 } else {
413 /*
414 * Repeated addressing - perform <length> separate
415 * write transactions of one byte each
416 */
417 while (length-- > 0) {
418#ifdef CONFIG_DM_I2C
419 i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
420 ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
421#else
422 ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
423#endif
424 if (ret)
425 return i2c_report_err(ret, I2C_ERR_WRITE);
ff5d2dce
YS
426/*
427 * No write delay with FRAM devices.
428 */
429#if !defined(CONFIG_SYS_I2C_FRAM)
ed16f146 430 udelay(11000);
ff5d2dce 431#endif
ed16f146 432 }
ff5d2dce
YS
433 }
434 return 0;
435}
436
63656b76
SG
437#ifdef CONFIG_DM_I2C
438static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
439 char *const argv[])
440{
441 struct udevice *dev;
442 uint flags;
443 int chip;
444 int ret;
445
446 if (argc < 2)
447 return CMD_RET_USAGE;
448
449 chip = simple_strtoul(argv[1], NULL, 16);
450 ret = i2c_get_cur_bus_chip(chip, &dev);
451 if (ret)
452 return i2c_report_err(ret, I2C_ERR_READ);
453
454 if (argc > 2) {
455 flags = simple_strtoul(argv[2], NULL, 16);
456 ret = i2c_set_chip_flags(dev, flags);
457 } else {
458 ret = i2c_get_chip_flags(dev, &flags);
459 if (!ret)
460 printf("%x\n", flags);
461 }
462 if (ret)
463 return i2c_report_err(ret, I2C_ERR_READ);
464
465 return 0;
466}
c10c8e31
SG
467
468static int do_i2c_olen(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
469{
470 struct udevice *dev;
471 uint olen;
472 int chip;
473 int ret;
474
475 if (argc < 2)
476 return CMD_RET_USAGE;
477
478 chip = simple_strtoul(argv[1], NULL, 16);
479 ret = i2c_get_cur_bus_chip(chip, &dev);
480 if (ret)
481 return i2c_report_err(ret, I2C_ERR_READ);
482
483 if (argc > 2) {
484 olen = simple_strtoul(argv[2], NULL, 16);
485 ret = i2c_set_chip_offset_len(dev, olen);
486 } else {
487 ret = i2c_get_chip_offset_len(dev);
488 if (ret >= 0) {
489 printf("%x\n", ret);
490 ret = 0;
491 }
492 }
493 if (ret)
494 return i2c_report_err(ret, I2C_ERR_READ);
495
496 return 0;
497}
63656b76
SG
498#endif
499
06afa388
MV
500/**
501 * do_i2c_md() - Handle the "i2c md" command-line command
502 * @cmdtp: Command data struct pointer
503 * @flag: Command flag
504 * @argc: Command-line argument count
505 * @argv: Array of command-line arguments
506 *
507 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
508 * on error.
509 *
4a8cf338
FM
510 * Syntax:
511 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
512 */
54841ab5 513static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 514{
5468461d 515 uint chip;
63656b76
SG
516 uint addr, length;
517 int alen;
81a8824f 518 int j, nbytes, linebytes;
63656b76
SG
519 int ret;
520#ifdef CONFIG_DM_I2C
521 struct udevice *dev;
522#endif
81a8824f
WD
523
524 /* We use the last specified parameters, unless new ones are
525 * entered.
526 */
527 chip = i2c_dp_last_chip;
528 addr = i2c_dp_last_addr;
529 alen = i2c_dp_last_alen;
530 length = i2c_dp_last_length;
531
47e26b1b 532 if (argc < 3)
4c12eeb8 533 return CMD_RET_USAGE;
81a8824f
WD
534
535 if ((flag & CMD_FLAG_REPEAT) == 0) {
536 /*
537 * New command specified.
538 */
81a8824f
WD
539
540 /*
541 * I2C chip address
542 */
543 chip = simple_strtoul(argv[1], NULL, 16);
544
545 /*
546 * I2C data address within the chip. This can be 1 or
547 * 2 bytes long. Some day it might be 3 bytes long :-).
548 */
549 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 550 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 551 if (alen > 3)
4c12eeb8 552 return CMD_RET_USAGE;
81a8824f
WD
553
554 /*
555 * If another parameter, it is the length to display.
556 * Length is the number of objects, not number of bytes.
557 */
558 if (argc > 3)
559 length = simple_strtoul(argv[3], NULL, 16);
560 }
561
63656b76
SG
562#ifdef CONFIG_DM_I2C
563 ret = i2c_get_cur_bus_chip(chip, &dev);
564 if (!ret && alen != -1)
565 ret = i2c_set_chip_offset_len(dev, alen);
566 if (ret)
567 return i2c_report_err(ret, I2C_ERR_READ);
568#endif
569
81a8824f
WD
570 /*
571 * Print the lines.
572 *
573 * We buffer all read data, so we can make sure data is read only
574 * once.
575 */
576 nbytes = length;
577 do {
578 unsigned char linebuf[DISP_LINE_LEN];
579 unsigned char *cp;
580
581 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
582
63656b76 583#ifdef CONFIG_DM_I2C
f9a4c2da 584 ret = dm_i2c_read(dev, addr, linebuf, linebytes);
63656b76
SG
585#else
586 ret = i2c_read(chip, addr, alen, linebuf, linebytes);
587#endif
588 if (ret)
9e533cb0 589 return i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 590 else {
81a8824f
WD
591 printf("%04x:", addr);
592 cp = linebuf;
593 for (j=0; j<linebytes; j++) {
594 printf(" %02x", *cp++);
595 addr++;
596 }
4b9206ed 597 puts (" ");
81a8824f
WD
598 cp = linebuf;
599 for (j=0; j<linebytes; j++) {
600 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 601 puts (".");
81a8824f
WD
602 else
603 printf("%c", *cp);
604 cp++;
605 }
4b9206ed 606 putc ('\n');
81a8824f
WD
607 }
608 nbytes -= linebytes;
609 } while (nbytes > 0);
610
611 i2c_dp_last_chip = chip;
612 i2c_dp_last_addr = addr;
613 i2c_dp_last_alen = alen;
614 i2c_dp_last_length = length;
615
616 return 0;
617}
618
06afa388
MV
619/**
620 * do_i2c_mw() - Handle the "i2c mw" command-line command
621 * @cmdtp: Command data struct pointer
622 * @flag: Command flag
623 * @argc: Command-line argument count
624 * @argv: Array of command-line arguments
625 *
626 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
627 * on error.
81a8824f
WD
628 *
629 * Syntax:
0f89c54b 630 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 631 */
54841ab5 632static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 633{
5468461d 634 uint chip;
81a8824f 635 ulong addr;
63656b76 636 int alen;
81a8824f
WD
637 uchar byte;
638 int count;
63656b76
SG
639 int ret;
640#ifdef CONFIG_DM_I2C
641 struct udevice *dev;
642#endif
81a8824f 643
47e26b1b 644 if ((argc < 4) || (argc > 5))
4c12eeb8 645 return CMD_RET_USAGE;
81a8824f
WD
646
647 /*
53677ef1
WD
648 * Chip is always specified.
649 */
81a8824f
WD
650 chip = simple_strtoul(argv[1], NULL, 16);
651
652 /*
653 * Address is always specified.
654 */
655 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 656 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 657 if (alen > 3)
4c12eeb8 658 return CMD_RET_USAGE;
81a8824f 659
63656b76
SG
660#ifdef CONFIG_DM_I2C
661 ret = i2c_get_cur_bus_chip(chip, &dev);
662 if (!ret && alen != -1)
663 ret = i2c_set_chip_offset_len(dev, alen);
664 if (ret)
665 return i2c_report_err(ret, I2C_ERR_WRITE);
666#endif
81a8824f
WD
667 /*
668 * Value to write is always specified.
669 */
670 byte = simple_strtoul(argv[3], NULL, 16);
671
672 /*
673 * Optional count
674 */
e857a5bd 675 if (argc == 5)
81a8824f 676 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 677 else
81a8824f 678 count = 1;
81a8824f
WD
679
680 while (count-- > 0) {
63656b76 681#ifdef CONFIG_DM_I2C
f9a4c2da 682 ret = dm_i2c_write(dev, addr++, &byte, 1);
63656b76
SG
683#else
684 ret = i2c_write(chip, addr++, alen, &byte, 1);
685#endif
686 if (ret)
9e533cb0 687 return i2c_report_err(ret, I2C_ERR_WRITE);
81a8824f
WD
688 /*
689 * Wait for the write to complete. The write can take
690 * up to 10mSec (we allow a little more time).
81a8824f 691 */
d4f5c728 692/*
693 * No write delay with FRAM devices.
694 */
6d0f6bcf 695#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 696 udelay(11000);
d4f5c728 697#endif
81a8824f
WD
698 }
699
06afa388 700 return 0;
81a8824f
WD
701}
702
06afa388
MV
703/**
704 * do_i2c_crc() - Handle the "i2c crc32" command-line command
705 * @cmdtp: Command data struct pointer
706 * @flag: Command flag
707 * @argc: Command-line argument count
708 * @argv: Array of command-line arguments
709 *
710 * Calculate a CRC on memory
711 *
712 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
713 * on error.
81a8824f
WD
714 *
715 * Syntax:
0f89c54b 716 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 717 */
54841ab5 718static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 719{
5468461d 720 uint chip;
81a8824f 721 ulong addr;
63656b76 722 int alen;
81a8824f
WD
723 int count;
724 uchar byte;
725 ulong crc;
726 ulong err;
63656b76
SG
727 int ret = 0;
728#ifdef CONFIG_DM_I2C
729 struct udevice *dev;
730#endif
81a8824f 731
47e26b1b 732 if (argc < 4)
4c12eeb8 733 return CMD_RET_USAGE;
81a8824f
WD
734
735 /*
53677ef1
WD
736 * Chip is always specified.
737 */
81a8824f
WD
738 chip = simple_strtoul(argv[1], NULL, 16);
739
740 /*
741 * Address is always specified.
742 */
743 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 744 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 745 if (alen > 3)
4c12eeb8 746 return CMD_RET_USAGE;
81a8824f 747
63656b76
SG
748#ifdef CONFIG_DM_I2C
749 ret = i2c_get_cur_bus_chip(chip, &dev);
750 if (!ret && alen != -1)
751 ret = i2c_set_chip_offset_len(dev, alen);
752 if (ret)
753 return i2c_report_err(ret, I2C_ERR_READ);
754#endif
81a8824f
WD
755 /*
756 * Count is always specified
757 */
758 count = simple_strtoul(argv[3], NULL, 16);
759
760 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
761 /*
762 * CRC a byte at a time. This is going to be slooow, but hey, the
763 * memories are small and slow too so hopefully nobody notices.
764 */
765 crc = 0;
766 err = 0;
e857a5bd 767 while (count-- > 0) {
63656b76 768#ifdef CONFIG_DM_I2C
f9a4c2da 769 ret = dm_i2c_read(dev, addr, &byte, 1);
63656b76
SG
770#else
771 ret = i2c_read(chip, addr, alen, &byte, 1);
772#endif
773 if (ret)
81a8824f 774 err++;
81a8824f
WD
775 crc = crc32 (crc, &byte, 1);
776 addr++;
777 }
e857a5bd 778 if (err > 0)
63656b76 779 i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 780 else
81a8824f 781 printf ("%08lx\n", crc);
81a8824f
WD
782
783 return 0;
784}
785
06afa388
MV
786/**
787 * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
788 * @cmdtp: Command data struct pointer
789 * @flag: Command flag
790 * @argc: Command-line argument count
791 * @argv: Array of command-line arguments
792 *
793 * Modify memory.
794 *
795 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
796 * on error.
81a8824f
WD
797 *
798 * Syntax:
0f89c54b
PT
799 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
800 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f 801 */
81a8824f 802static int
54841ab5 803mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
81a8824f 804{
5468461d 805 uint chip;
81a8824f 806 ulong addr;
63656b76 807 int alen;
81a8824f
WD
808 ulong data;
809 int size = 1;
810 int nbytes;
63656b76
SG
811 int ret;
812#ifdef CONFIG_DM_I2C
813 struct udevice *dev;
814#endif
81a8824f 815
47e26b1b 816 if (argc != 3)
4c12eeb8 817 return CMD_RET_USAGE;
81a8824f 818
b26440f1 819 bootretry_reset_cmd_timeout(); /* got a good command to get here */
81a8824f
WD
820 /*
821 * We use the last specified parameters, unless new ones are
822 * entered.
823 */
824 chip = i2c_mm_last_chip;
825 addr = i2c_mm_last_addr;
826 alen = i2c_mm_last_alen;
827
828 if ((flag & CMD_FLAG_REPEAT) == 0) {
829 /*
830 * New command specified. Check for a size specification.
831 * Defaults to byte if no or incorrect specification.
832 */
833 size = cmd_get_data_size(argv[0], 1);
834
835 /*
53677ef1
WD
836 * Chip is always specified.
837 */
81a8824f
WD
838 chip = simple_strtoul(argv[1], NULL, 16);
839
840 /*
841 * Address is always specified.
842 */
843 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 844 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 845 if (alen > 3)
4c12eeb8 846 return CMD_RET_USAGE;
81a8824f
WD
847 }
848
63656b76
SG
849#ifdef CONFIG_DM_I2C
850 ret = i2c_get_cur_bus_chip(chip, &dev);
851 if (!ret && alen != -1)
852 ret = i2c_set_chip_offset_len(dev, alen);
853 if (ret)
854 return i2c_report_err(ret, I2C_ERR_WRITE);
855#endif
856
81a8824f
WD
857 /*
858 * Print the address, followed by value. Then accept input for
859 * the next value. A non-converted value exits.
860 */
861 do {
862 printf("%08lx:", addr);
63656b76 863#ifdef CONFIG_DM_I2C
f9a4c2da 864 ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
63656b76
SG
865#else
866 ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
867#endif
868 if (ret)
9e533cb0
MY
869 return i2c_report_err(ret, I2C_ERR_READ);
870
871 data = cpu_to_be32(data);
872 if (size == 1)
873 printf(" %02lx", (data >> 24) & 0x000000FF);
874 else if (size == 2)
875 printf(" %04lx", (data >> 16) & 0x0000FFFF);
876 else
877 printf(" %08lx", data);
81a8824f 878
e1bf824d 879 nbytes = cli_readline(" ? ");
81a8824f
WD
880 if (nbytes == 0) {
881 /*
882 * <CR> pressed as only input, don't modify current
883 * location and move to next.
884 */
885 if (incrflag)
886 addr += size;
887 nbytes = size;
b26440f1
SG
888 /* good enough to not time out */
889 bootretry_reset_cmd_timeout();
81a8824f
WD
890 }
891#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 892 else if (nbytes == -2)
81a8824f 893 break; /* timed out, exit the command */
81a8824f
WD
894#endif
895 else {
896 char *endp;
897
898 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 899 if (size == 1)
81a8824f 900 data = data << 24;
e857a5bd 901 else if (size == 2)
81a8824f 902 data = data << 16;
81a8824f
WD
903 data = be32_to_cpu(data);
904 nbytes = endp - console_buffer;
905 if (nbytes) {
81a8824f
WD
906 /*
907 * good enough to not time out
908 */
b26440f1 909 bootretry_reset_cmd_timeout();
63656b76 910#ifdef CONFIG_DM_I2C
f9a4c2da
SG
911 ret = dm_i2c_write(dev, addr, (uchar *)&data,
912 size);
63656b76
SG
913#else
914 ret = i2c_write(chip, addr, alen,
915 (uchar *)&data, size);
916#endif
917 if (ret)
9e533cb0
MY
918 return i2c_report_err(ret,
919 I2C_ERR_WRITE);
6d0f6bcf
JCPV
920#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
921 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 922#endif
81a8824f
WD
923 if (incrflag)
924 addr += size;
925 }
926 }
927 } while (nbytes);
928
0800707b
PT
929 i2c_mm_last_chip = chip;
930 i2c_mm_last_addr = addr;
931 i2c_mm_last_alen = alen;
81a8824f
WD
932
933 return 0;
934}
935
06afa388
MV
936/**
937 * do_i2c_probe() - Handle the "i2c probe" command-line command
938 * @cmdtp: Command data struct pointer
939 * @flag: Command flag
940 * @argc: Command-line argument count
941 * @argv: Array of command-line arguments
942 *
943 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
944 * on error.
945 *
81a8824f 946 * Syntax:
54b99e51
EN
947 * i2c probe {addr}
948 *
949 * Returns zero (success) if one or more I2C devices was found
81a8824f 950 */
54841ab5 951static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
952{
953 int j;
54b99e51
EN
954 int addr = -1;
955 int found = 0;
6d0f6bcf 956#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 957 int k, skip;
3f4978c7 958 unsigned int bus = GET_BUS_NUM;
bb99ad6d 959#endif /* NOPROBES */
63656b76
SG
960 int ret;
961#ifdef CONFIG_DM_I2C
962 struct udevice *bus, *dev;
963
964 if (i2c_get_cur_bus(&bus))
965 return CMD_RET_FAILURE;
966#endif
81a8824f 967
54b99e51
EN
968 if (argc == 2)
969 addr = simple_strtol(argv[1], 0, 16);
970
4b9206ed 971 puts ("Valid chip addresses:");
e857a5bd 972 for (j = 0; j < 128; j++) {
54b99e51
EN
973 if ((0 <= addr) && (j != addr))
974 continue;
975
6d0f6bcf 976#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 977 skip = 0;
cfb25cc4 978 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 979 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
980 skip = 1;
981 break;
982 }
983 }
984 if (skip)
985 continue;
986#endif
63656b76 987#ifdef CONFIG_DM_I2C
f9a4c2da 988 ret = dm_i2c_probe(bus, j, 0, &dev);
63656b76
SG
989#else
990 ret = i2c_probe(j);
991#endif
992 if (ret == 0) {
81a8824f 993 printf(" %02X", j);
54b99e51
EN
994 found++;
995 }
81a8824f 996 }
4b9206ed 997 putc ('\n');
81a8824f 998
6d0f6bcf 999#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 1000 puts ("Excluded chip addresses:");
cfb25cc4 1001 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 1002 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
1003 printf(" %02X", NO_PROBE_ADDR(k));
1004 }
4b9206ed 1005 putc ('\n');
81a8824f
WD
1006#endif
1007
54b99e51 1008 return (0 == found);
81a8824f
WD
1009}
1010
06afa388
MV
1011/**
1012 * do_i2c_loop() - Handle the "i2c loop" command-line command
1013 * @cmdtp: Command data struct pointer
1014 * @flag: Command flag
1015 * @argc: Command-line argument count
1016 * @argv: Array of command-line arguments
1017 *
1018 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1019 * on error.
1020 *
81a8824f 1021 * Syntax:
0f89c54b 1022 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
1023 * {length} - Number of bytes to read
1024 * {delay} - A DECIMAL number and defaults to 1000 uSec
1025 */
54841ab5 1026static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 1027{
5468461d 1028 uint chip;
63656b76 1029 int alen;
81a8824f
WD
1030 uint addr;
1031 uint length;
1032 u_char bytes[16];
1033 int delay;
63656b76
SG
1034 int ret;
1035#ifdef CONFIG_DM_I2C
1036 struct udevice *dev;
1037#endif
81a8824f 1038
47e26b1b 1039 if (argc < 3)
4c12eeb8 1040 return CMD_RET_USAGE;
81a8824f
WD
1041
1042 /*
1043 * Chip is always specified.
1044 */
1045 chip = simple_strtoul(argv[1], NULL, 16);
1046
1047 /*
1048 * Address is always specified.
1049 */
1050 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 1051 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 1052 if (alen > 3)
4c12eeb8 1053 return CMD_RET_USAGE;
63656b76
SG
1054#ifdef CONFIG_DM_I2C
1055 ret = i2c_get_cur_bus_chip(chip, &dev);
1056 if (!ret && alen != -1)
1057 ret = i2c_set_chip_offset_len(dev, alen);
1058 if (ret)
1059 return i2c_report_err(ret, I2C_ERR_WRITE);
1060#endif
81a8824f
WD
1061
1062 /*
1063 * Length is the number of objects, not number of bytes.
1064 */
1065 length = 1;
1066 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 1067 if (length > sizeof(bytes))
81a8824f 1068 length = sizeof(bytes);
81a8824f
WD
1069
1070 /*
1071 * The delay time (uSec) is optional.
1072 */
1073 delay = 1000;
e857a5bd 1074 if (argc > 3)
81a8824f 1075 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
1076 /*
1077 * Run the loop...
1078 */
e857a5bd 1079 while (1) {
63656b76 1080#ifdef CONFIG_DM_I2C
f9a4c2da 1081 ret = dm_i2c_read(dev, addr, bytes, length);
63656b76
SG
1082#else
1083 ret = i2c_read(chip, addr, alen, bytes, length);
1084#endif
1085 if (ret)
1086 i2c_report_err(ret, I2C_ERR_READ);
81a8824f
WD
1087 udelay(delay);
1088 }
1089
1090 /* NOTREACHED */
1091 return 0;
1092}
1093
81a8824f
WD
1094/*
1095 * The SDRAM command is separately configured because many
1096 * (most?) embedded boards don't use SDRAM DIMMs.
06afa388
MV
1097 *
1098 * FIXME: Document and probably move elsewhere!
81a8824f 1099 */
c76fe474 1100#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
1101static void print_ddr2_tcyc (u_char const b)
1102{
1103 printf ("%d.", (b >> 4) & 0x0F);
1104 switch (b & 0x0F) {
1105 case 0x0:
1106 case 0x1:
1107 case 0x2:
1108 case 0x3:
1109 case 0x4:
1110 case 0x5:
1111 case 0x6:
1112 case 0x7:
1113 case 0x8:
1114 case 0x9:
1115 printf ("%d ns\n", b & 0x0F);
1116 break;
1117 case 0xA:
1118 puts ("25 ns\n");
1119 break;
1120 case 0xB:
1121 puts ("33 ns\n");
1122 break;
1123 case 0xC:
1124 puts ("66 ns\n");
1125 break;
1126 case 0xD:
1127 puts ("75 ns\n");
1128 break;
1129 default:
1130 puts ("?? ns\n");
1131 break;
1132 }
1133}
1134
1135static void decode_bits (u_char const b, char const *str[], int const do_once)
1136{
1137 u_char mask;
1138
1139 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1140 if (b & mask) {
1141 puts (*str);
1142 if (do_once)
1143 return;
1144 }
1145 }
1146}
81a8824f
WD
1147
1148/*
1149 * Syntax:
0f89c54b 1150 * i2c sdram {i2c_chip}
81a8824f 1151 */
54841ab5 1152static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
81a8824f 1153{
18c4e7f7 1154 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type;
632de067 1155
5468461d 1156 uint chip;
81a8824f
WD
1157 u_char data[128];
1158 u_char cksum;
28df8ed0
NI
1159 int j, ret;
1160#ifdef CONFIG_DM_I2C
1161 struct udevice *dev;
1162#endif
81a8824f 1163
632de067
LJ
1164 static const char *decode_CAS_DDR2[] = {
1165 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1166 };
1167
1168 static const char *decode_CAS_default[] = {
1169 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1170 };
1171
1172 static const char *decode_CS_WE_default[] = {
1173 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1174 };
1175
1176 static const char *decode_byte21_default[] = {
1177 " TBD (bit 7)\n",
1178 " Redundant row address\n",
1179 " Differential clock input\n",
1180 " Registerd DQMB inputs\n",
1181 " Buffered DQMB inputs\n",
1182 " On-card PLL\n",
1183 " Registered address/control lines\n",
1184 " Buffered address/control lines\n"
1185 };
1186
1187 static const char *decode_byte22_DDR2[] = {
1188 " TBD (bit 7)\n",
1189 " TBD (bit 6)\n",
1190 " TBD (bit 5)\n",
1191 " TBD (bit 4)\n",
1192 " TBD (bit 3)\n",
1193 " Supports partial array self refresh\n",
1194 " Supports 50 ohm ODT\n",
1195 " Supports weak driver\n"
1196 };
1197
1198 static const char *decode_row_density_DDR2[] = {
1199 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1200 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1201 };
1202
1203 static const char *decode_row_density_default[] = {
1204 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1205 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1206 };
1207
47e26b1b 1208 if (argc < 2)
4c12eeb8 1209 return CMD_RET_USAGE;
47e26b1b 1210
81a8824f
WD
1211 /*
1212 * Chip is always specified.
632de067
LJ
1213 */
1214 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 1215
28df8ed0
NI
1216#ifdef CONFIG_DM_I2C
1217 ret = i2c_get_cur_bus_chip(chip, &dev);
1218 if (!ret)
1219 ret = dm_i2c_read(dev, 0, data, sizeof(data));
1220#else
1221 ret = i2c_read(chip, 0, 1, data, sizeof(data));
1222#endif
1223 if (ret) {
4b9206ed 1224 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
1225 return 1;
1226 }
1227
1228 cksum = 0;
1229 for (j = 0; j < 63; j++) {
1230 cksum += data[j];
1231 }
e857a5bd 1232 if (cksum != data[63]) {
81a8824f 1233 printf ("WARNING: Configuration data checksum failure:\n"
632de067 1234 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 1235 }
632de067 1236 printf ("SPD data revision %d.%d\n",
81a8824f 1237 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
1238 printf ("Bytes used 0x%02X\n", data[0]);
1239 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1240
4b9206ed 1241 puts ("Memory type ");
632de067 1242 switch (data[2]) {
0df6b844
LJ
1243 case 2:
1244 type = EDO;
1245 puts ("EDO\n");
1246 break;
1247 case 4:
1248 type = SDRAM;
1249 puts ("SDRAM\n");
1250 break;
18c4e7f7
MS
1251 case 7:
1252 type = DDR;
1253 puts("DDR\n");
1254 break;
0df6b844
LJ
1255 case 8:
1256 type = DDR2;
1257 puts ("DDR2\n");
1258 break;
18c4e7f7
MS
1259 case 11:
1260 type = DDR3;
1261 puts("DDR3\n");
1262 break;
1263 case 12:
1264 type = DDR4;
1265 puts("DDR4\n");
1266 break;
0df6b844
LJ
1267 default:
1268 type = unknown;
1269 puts ("unknown\n");
1270 break;
81a8824f 1271 }
632de067 1272
4b9206ed 1273 puts ("Row address bits ");
e857a5bd 1274 if ((data[3] & 0x00F0) == 0)
632de067 1275 printf ("%d\n", data[3] & 0x0F);
e857a5bd 1276 else
632de067
LJ
1277 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1278
4b9206ed 1279 puts ("Column address bits ");
e857a5bd 1280 if ((data[4] & 0x00F0) == 0)
632de067 1281 printf ("%d\n", data[4] & 0x0F);
e857a5bd 1282 else
632de067 1283 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
1284
1285 switch (type) {
1286 case DDR2:
632de067
LJ
1287 printf ("Number of ranks %d\n",
1288 (data[5] & 0x07) + 1);
0df6b844
LJ
1289 break;
1290 default:
632de067 1291 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
1292 break;
1293 }
1294
1295 switch (type) {
1296 case DDR2:
632de067 1297 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
1298 break;
1299 default:
632de067
LJ
1300 printf ("Module data width %d bits\n",
1301 (data[7] << 8) | data[6]);
0df6b844
LJ
1302 break;
1303 }
1304
4b9206ed 1305 puts ("Interface signal levels ");
81a8824f 1306 switch(data[8]) {
0df6b844 1307 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 1308 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
1309 case 2: puts ("HSTL 1.5 V\n"); break;
1310 case 3: puts ("SSTL 3.3 V\n"); break;
1311 case 4: puts ("SSTL 2.5 V\n"); break;
1312 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 1313 default: puts ("unknown\n"); break;
81a8824f 1314 }
0df6b844
LJ
1315
1316 switch (type) {
1317 case DDR2:
632de067
LJ
1318 printf ("SDRAM cycle time ");
1319 print_ddr2_tcyc (data[9]);
0df6b844
LJ
1320 break;
1321 default:
632de067
LJ
1322 printf ("SDRAM cycle time %d.%d ns\n",
1323 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
1324 break;
1325 }
1326
1327 switch (type) {
1328 case DDR2:
632de067
LJ
1329 printf ("SDRAM access time 0.%d%d ns\n",
1330 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1331 break;
1332 default:
632de067
LJ
1333 printf ("SDRAM access time %d.%d ns\n",
1334 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1335 break;
1336 }
1337
4b9206ed 1338 puts ("EDC configuration ");
632de067 1339 switch (data[11]) {
4b9206ed
WD
1340 case 0: puts ("None\n"); break;
1341 case 1: puts ("Parity\n"); break;
1342 case 2: puts ("ECC\n"); break;
1343 default: puts ("unknown\n"); break;
81a8824f 1344 }
632de067 1345
e857a5bd 1346 if ((data[12] & 0x80) == 0)
4b9206ed 1347 puts ("No self refresh, rate ");
e857a5bd 1348 else
4b9206ed 1349 puts ("Self refresh, rate ");
632de067 1350
81a8824f 1351 switch(data[12] & 0x7F) {
632de067
LJ
1352 case 0: puts ("15.625 us\n"); break;
1353 case 1: puts ("3.9 us\n"); break;
1354 case 2: puts ("7.8 us\n"); break;
1355 case 3: puts ("31.3 us\n"); break;
1356 case 4: puts ("62.5 us\n"); break;
1357 case 5: puts ("125 us\n"); break;
4b9206ed 1358 default: puts ("unknown\n"); break;
81a8824f 1359 }
0df6b844
LJ
1360
1361 switch (type) {
1362 case DDR2:
632de067 1363 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
1364 break;
1365 default:
632de067 1366 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 1367 if ((data[13] & 0x80) != 0) {
632de067
LJ
1368 printf (" (second bank) %d\n",
1369 2 * (data[13] & 0x7F));
0df6b844
LJ
1370 }
1371 break;
1372 }
1373
1374 switch (type) {
1375 case DDR2:
1376 if (data[14] != 0)
632de067 1377 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
1378 break;
1379 default:
1380 if (data[14] != 0) {
632de067
LJ
1381 printf ("EDC width %d\n",
1382 data[14] & 0x7F);
0df6b844
LJ
1383
1384 if ((data[14] & 0x80) != 0) {
632de067
LJ
1385 printf (" (second bank) %d\n",
1386 2 * (data[14] & 0x7F));
0df6b844
LJ
1387 }
1388 }
1389 break;
81a8824f 1390 }
0df6b844 1391
632de067
LJ
1392 if (DDR2 != type) {
1393 printf ("Min clock delay, back-to-back random column addresses "
1394 "%d\n", data[15]);
0df6b844
LJ
1395 }
1396
4b9206ed
WD
1397 puts ("Burst length(s) ");
1398 if (data[16] & 0x80) puts (" Page");
1399 if (data[16] & 0x08) puts (" 8");
1400 if (data[16] & 0x04) puts (" 4");
1401 if (data[16] & 0x02) puts (" 2");
1402 if (data[16] & 0x01) puts (" 1");
1403 putc ('\n');
632de067 1404 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1405
1406 switch (type) {
1407 case DDR2:
1408 puts ("CAS latency(s) ");
632de067 1409 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1410 putc ('\n');
1411 break;
1412 default:
1413 puts ("CAS latency(s) ");
632de067 1414 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1415 putc ('\n');
1416 break;
1417 }
1418
1419 if (DDR2 != type) {
1420 puts ("CS latency(s) ");
632de067 1421 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1422 putc ('\n');
1423 }
1424
1425 if (DDR2 != type) {
1426 puts ("WE latency(s) ");
632de067 1427 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1428 putc ('\n');
1429 }
1430
1431 switch (type) {
1432 case DDR2:
1433 puts ("Module attributes:\n");
1434 if (data[21] & 0x80)
1435 puts (" TBD (bit 7)\n");
1436 if (data[21] & 0x40)
1437 puts (" Analysis probe installed\n");
1438 if (data[21] & 0x20)
1439 puts (" TBD (bit 5)\n");
1440 if (data[21] & 0x10)
1441 puts (" FET switch external enable\n");
632de067 1442 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1443 if (data[20] & 0x11) {
632de067
LJ
1444 printf (" %d active registers on DIMM\n",
1445 (data[21] & 0x03) + 1);
0df6b844
LJ
1446 }
1447 break;
1448 default:
1449 puts ("Module attributes:\n");
1450 if (!data[21])
1451 puts (" (none)\n");
632de067
LJ
1452 else
1453 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1454 break;
1455 }
1456
1457 switch (type) {
1458 case DDR2:
632de067 1459 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1460 break;
1461 default:
1462 puts ("Device attributes:\n");
1463 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1464 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1465 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1466 else puts (" Upper Vcc tolerance 10%\n");
1467 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1468 else puts (" Lower Vcc tolerance 10%\n");
1469 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1470 if (data[22] & 0x04) puts (" Supports precharge all\n");
1471 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1472 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1473 break;
1474 }
1475
1476 switch (type) {
1477 case DDR2:
632de067
LJ
1478 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1479 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1480 break;
1481 default:
632de067
LJ
1482 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1483 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1484 break;
1485 }
1486
1487 switch (type) {
1488 case DDR2:
632de067
LJ
1489 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1490 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1491 break;
1492 default:
632de067
LJ
1493 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1494 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1495 break;
1496 }
1497
1498 switch (type) {
1499 case DDR2:
632de067
LJ
1500 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1501 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1502 break;
1503 default:
632de067
LJ
1504 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1505 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1506 break;
1507 }
1508
1509 switch (type) {
1510 case DDR2:
632de067
LJ
1511 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1512 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1513 break;
1514 default:
632de067
LJ
1515 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1516 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1517 break;
1518 }
1519
1520 switch (type) {
1521 case DDR2:
632de067
LJ
1522 printf ("Minimum row precharge %d.%02d ns\n",
1523 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1524 break;
1525 default:
632de067 1526 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1527 break;
1528 }
1529
1530 switch (type) {
1531 case DDR2:
632de067
LJ
1532 printf ("Row active to row active min %d.%02d ns\n",
1533 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1534 break;
1535 default:
632de067 1536 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1537 break;
1538 }
1539
1540 switch (type) {
1541 case DDR2:
632de067
LJ
1542 printf ("RAS to CAS delay min %d.%02d ns\n",
1543 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1544 break;
1545 default:
632de067 1546 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1547 break;
1548 }
1549
632de067 1550 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1551
1552 switch (type) {
1553 case DDR2:
632de067
LJ
1554 puts ("Density of each row ");
1555 decode_bits (data[31], decode_row_density_DDR2, 1);
1556 putc ('\n');
0df6b844
LJ
1557 break;
1558 default:
632de067
LJ
1559 puts ("Density of each row ");
1560 decode_bits (data[31], decode_row_density_default, 1);
1561 putc ('\n');
0df6b844
LJ
1562 break;
1563 }
1564
1565 switch (type) {
1566 case DDR2:
632de067 1567 puts ("Command and Address setup ");
0df6b844 1568 if (data[32] >= 0xA0) {
632de067
LJ
1569 printf ("1.%d%d ns\n",
1570 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1571 } else {
632de067
LJ
1572 printf ("0.%d%d ns\n",
1573 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1574 }
1575 break;
1576 default:
632de067
LJ
1577 printf ("Command and Address setup %c%d.%d ns\n",
1578 (data[32] & 0x80) ? '-' : '+',
1579 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1580 break;
1581 }
1582
1583 switch (type) {
1584 case DDR2:
632de067 1585 puts ("Command and Address hold ");
0df6b844 1586 if (data[33] >= 0xA0) {
632de067
LJ
1587 printf ("1.%d%d ns\n",
1588 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1589 } else {
632de067
LJ
1590 printf ("0.%d%d ns\n",
1591 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1592 }
1593 break;
1594 default:
632de067
LJ
1595 printf ("Command and Address hold %c%d.%d ns\n",
1596 (data[33] & 0x80) ? '-' : '+',
1597 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1598 break;
1599 }
1600
1601 switch (type) {
1602 case DDR2:
632de067
LJ
1603 printf ("Data signal input setup 0.%d%d ns\n",
1604 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1605 break;
1606 default:
632de067
LJ
1607 printf ("Data signal input setup %c%d.%d ns\n",
1608 (data[34] & 0x80) ? '-' : '+',
1609 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1610 break;
1611 }
1612
1613 switch (type) {
1614 case DDR2:
632de067
LJ
1615 printf ("Data signal input hold 0.%d%d ns\n",
1616 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1617 break;
1618 default:
632de067
LJ
1619 printf ("Data signal input hold %c%d.%d ns\n",
1620 (data[35] & 0x80) ? '-' : '+',
1621 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1622 break;
1623 }
1624
4b9206ed 1625 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1626 for (j = 64; j <= 71; j++)
632de067 1627 printf ("%02X ", data[j]);
4b9206ed 1628 putc ('\n');
632de067 1629 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1630 puts ("Manufacturer's Part Number ");
e857a5bd 1631 for (j = 73; j <= 90; j++)
632de067 1632 printf ("%02X ", data[j]);
4b9206ed 1633 putc ('\n');
632de067
LJ
1634 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1635 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1636 puts ("Assembly Serial Number ");
e857a5bd 1637 for (j = 95; j <= 98; j++)
632de067 1638 printf ("%02X ", data[j]);
4b9206ed 1639 putc ('\n');
81a8824f 1640
0df6b844 1641 if (DDR2 != type) {
632de067
LJ
1642 printf ("Speed rating PC%d\n",
1643 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1644 }
81a8824f
WD
1645 return 0;
1646}
90253178 1647#endif
81a8824f 1648
735987c5
TWHT
1649/*
1650 * Syntax:
1651 * i2c edid {i2c_chip}
1652 */
1653#if defined(CONFIG_I2C_EDID)
1654int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1655{
5468461d 1656 uint chip;
735987c5 1657 struct edid1_info edid;
63656b76
SG
1658 int ret;
1659#ifdef CONFIG_DM_I2C
1660 struct udevice *dev;
1661#endif
735987c5
TWHT
1662
1663 if (argc < 2) {
1664 cmd_usage(cmdtp);
1665 return 1;
1666 }
1667
1668 chip = simple_strtoul(argv[1], NULL, 16);
63656b76
SG
1669#ifdef CONFIG_DM_I2C
1670 ret = i2c_get_cur_bus_chip(chip, &dev);
1671 if (!ret)
f9a4c2da 1672 ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
63656b76
SG
1673#else
1674 ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1675#endif
1676 if (ret)
1677 return i2c_report_err(ret, I2C_ERR_READ);
735987c5
TWHT
1678
1679 if (edid_check_info(&edid)) {
1680 puts("Content isn't valid EDID.\n");
1681 return 1;
1682 }
1683
1684 edid_print_info(&edid);
1685 return 0;
1686
1687}
1688#endif /* CONFIG_I2C_EDID */
1689
59aa9df3
SG
1690#ifdef CONFIG_DM_I2C
1691static void show_bus(struct udevice *bus)
1692{
1693 struct udevice *dev;
1694
1695 printf("Bus %d:\t%s", bus->req_seq, bus->name);
1696 if (device_active(bus))
1697 printf(" (active %d)", bus->seq);
1698 printf("\n");
1699 for (device_find_first_child(bus, &dev);
1700 dev;
1701 device_find_next_child(&dev)) {
1702 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
1703
1704 printf(" %02x: %s, offset len %x, flags %x\n",
1705 chip->chip_addr, dev->name, chip->offset_len,
1706 chip->flags);
1707 }
1708}
1709#endif
1710
06afa388 1711/**
3f4978c7 1712 * do_i2c_show_bus() - Handle the "i2c bus" command-line command
06afa388
MV
1713 * @cmdtp: Command data struct pointer
1714 * @flag: Command flag
1715 * @argc: Command-line argument count
1716 * @argv: Array of command-line arguments
1717 *
1718 * Returns zero always.
1719 */
59aa9df3 1720#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
0e350f81
JH
1721static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
1722 char * const argv[])
67b23a32 1723{
67b23a32
HS
1724 if (argc == 1) {
1725 /* show all busses */
59aa9df3
SG
1726#ifdef CONFIG_DM_I2C
1727 struct udevice *bus;
1728 struct uclass *uc;
1729 int ret;
1730
1731 ret = uclass_get(UCLASS_I2C, &uc);
1732 if (ret)
1733 return CMD_RET_FAILURE;
1734 uclass_foreach_dev(bus, uc)
1735 show_bus(bus);
1736#else
1737 int i;
1738
3f4978c7
HS
1739 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1740 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1741#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3
SG
1742 int j;
1743
3f4978c7
HS
1744 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1745 if (i2c_bus[i].next_hop[j].chip == 0)
1746 break;
1747 printf("->%s@0x%2x:%d",
1748 i2c_bus[i].next_hop[j].mux.name,
1749 i2c_bus[i].next_hop[j].chip,
1750 i2c_bus[i].next_hop[j].channel);
67b23a32 1751 }
3f4978c7
HS
1752#endif
1753 printf("\n");
67b23a32 1754 }
59aa9df3 1755#endif
67b23a32 1756 } else {
59aa9df3
SG
1757 int i;
1758
3f4978c7
HS
1759 /* show specific bus */
1760 i = simple_strtoul(argv[1], NULL, 10);
59aa9df3
SG
1761#ifdef CONFIG_DM_I2C
1762 struct udevice *bus;
1763 int ret;
1764
1765 ret = uclass_get_device_by_seq(UCLASS_I2C, i, &bus);
1766 if (ret) {
1767 printf("Invalid bus %d: err=%d\n", i, ret);
1768 return CMD_RET_FAILURE;
1769 }
1770 show_bus(bus);
1771#else
3f4978c7
HS
1772 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1773 printf("Invalid bus %d\n", i);
1774 return -1;
1775 }
1776 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1777#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3 1778 int j;
3f4978c7
HS
1779 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1780 if (i2c_bus[i].next_hop[j].chip == 0)
1781 break;
1782 printf("->%s@0x%2x:%d",
1783 i2c_bus[i].next_hop[j].mux.name,
1784 i2c_bus[i].next_hop[j].chip,
1785 i2c_bus[i].next_hop[j].channel);
1786 }
1787#endif
1788 printf("\n");
59aa9df3 1789#endif
67b23a32 1790 }
3f4978c7
HS
1791
1792 return 0;
67b23a32 1793}
3f4978c7 1794#endif
67b23a32 1795
06afa388
MV
1796/**
1797 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1798 * @cmdtp: Command data struct pointer
1799 * @flag: Command flag
1800 * @argc: Command-line argument count
1801 * @argv: Array of command-line arguments
1802 *
1803 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1804 * on error.
1805 */
63656b76
SG
1806#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1807 defined(CONFIG_DM_I2C)
0e350f81
JH
1808static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
1809 char * const argv[])
bb99ad6d 1810{
3f4978c7 1811 int ret = 0;
63656b76 1812 int bus_no;
bb99ad6d 1813
63656b76 1814 if (argc == 1) {
e857a5bd 1815 /* querying current setting */
63656b76
SG
1816#ifdef CONFIG_DM_I2C
1817 struct udevice *bus;
1818
1819 if (!i2c_get_cur_bus(&bus))
1820 bus_no = bus->seq;
1821 else
1822 bus_no = -1;
1823#else
1824 bus_no = i2c_get_bus_num();
1825#endif
1826 printf("Current bus is %d\n", bus_no);
1827 } else {
3f4978c7 1828 bus_no = simple_strtoul(argv[1], NULL, 10);
880a4127 1829#if defined(CONFIG_SYS_I2C)
3f4978c7
HS
1830 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1831 printf("Invalid bus %d\n", bus_no);
1832 return -1;
1833 }
880a4127 1834#endif
3f4978c7 1835 printf("Setting bus to %d\n", bus_no);
f9a4c2da
SG
1836#ifdef CONFIG_DM_I2C
1837 ret = cmd_i2c_set_bus_num(bus_no);
1838#else
3f4978c7 1839 ret = i2c_set_bus_num(bus_no);
f9a4c2da 1840#endif
e857a5bd 1841 if (ret)
bb99ad6d 1842 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d 1843 }
4fbd258e
SG
1844
1845 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d 1846}
3f4978c7 1847#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d 1848
06afa388
MV
1849/**
1850 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1851 * @cmdtp: Command data struct pointer
1852 * @flag: Command flag
1853 * @argc: Command-line argument count
1854 * @argv: Array of command-line arguments
1855 *
1856 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1857 * on error.
1858 */
54841ab5 1859static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1860{
1861 int speed, ret=0;
1862
63656b76
SG
1863#ifdef CONFIG_DM_I2C
1864 struct udevice *bus;
1865
1866 if (i2c_get_cur_bus(&bus))
1867 return 1;
1868#endif
1869 if (argc == 1) {
1870#ifdef CONFIG_DM_I2C
ca88b9b9 1871 speed = dm_i2c_get_bus_speed(bus);
63656b76
SG
1872#else
1873 speed = i2c_get_bus_speed();
1874#endif
e857a5bd 1875 /* querying current speed */
63656b76
SG
1876 printf("Current bus speed=%d\n", speed);
1877 } else {
bb99ad6d
BW
1878 speed = simple_strtoul(argv[1], NULL, 10);
1879 printf("Setting bus speed to %d Hz\n", speed);
63656b76 1880#ifdef CONFIG_DM_I2C
ca88b9b9 1881 ret = dm_i2c_set_bus_speed(bus, speed);
63656b76 1882#else
bb99ad6d 1883 ret = i2c_set_bus_speed(speed);
63656b76 1884#endif
e857a5bd 1885 if (ret)
bb99ad6d 1886 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d 1887 }
4fbd258e
SG
1888
1889 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d
BW
1890}
1891
06afa388
MV
1892/**
1893 * do_i2c_mm() - Handle the "i2c mm" command-line command
1894 * @cmdtp: Command data struct pointer
1895 * @flag: Command flag
1896 * @argc: Command-line argument count
1897 * @argv: Array of command-line arguments
1898 *
1899 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1900 * on error.
1901 */
54841ab5 1902static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1903{
bfc3b77e
FM
1904 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1905}
1906
06afa388
MV
1907/**
1908 * do_i2c_nm() - Handle the "i2c nm" command-line command
1909 * @cmdtp: Command data struct pointer
1910 * @flag: Command flag
1911 * @argc: Command-line argument count
1912 * @argv: Array of command-line arguments
1913 *
1914 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1915 * on error.
1916 */
54841ab5 1917static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1918{
1919 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1920}
e96ad5d3 1921
06afa388
MV
1922/**
1923 * do_i2c_reset() - Handle the "i2c reset" command-line command
1924 * @cmdtp: Command data struct pointer
1925 * @flag: Command flag
1926 * @argc: Command-line argument count
1927 * @argv: Array of command-line arguments
1928 *
1929 * Returns zero always.
1930 */
54841ab5 1931static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e 1932{
63656b76
SG
1933#if defined(CONFIG_DM_I2C)
1934 struct udevice *bus;
1935
1936 if (i2c_get_cur_bus(&bus))
1937 return CMD_RET_FAILURE;
1938 if (i2c_deblock(bus)) {
1939 printf("Error: Not supported by the driver\n");
1940 return CMD_RET_FAILURE;
1941 }
1942#elif defined(CONFIG_SYS_I2C)
3f4978c7
HS
1943 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1944#else
bfc3b77e 1945 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3f4978c7 1946#endif
bfc3b77e
FM
1947 return 0;
1948}
1949
1950static cmd_tbl_t cmd_i2c_sub[] = {
59aa9df3 1951#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 1952 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
9a2accb4 1953#endif
bfc3b77e 1954 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
3f4978c7 1955#if defined(CONFIG_SYS_I2C) || \
63656b76 1956 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
bfc3b77e 1957 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1958#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1959#if defined(CONFIG_I2C_EDID)
1960 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1961#endif /* CONFIG_I2C_EDID */
bfc3b77e
FM
1962 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1963 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1964 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1965 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1966 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1967 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1968 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ed16f146 1969 U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
63656b76
SG
1970#ifdef CONFIG_DM_I2C
1971 U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
c10c8e31 1972 U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
63656b76 1973#endif
bfc3b77e 1974 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1975#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1976 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1977#endif
bfc3b77e
FM
1978 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1979};
1980
e4099c8b
MS
1981static __maybe_unused void i2c_reloc(void)
1982{
1983 static int relocated;
1984
1985 if (!relocated) {
1986 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1987 relocated = 1;
1988 };
f1d2b313 1989}
f1d2b313 1990
06afa388
MV
1991/**
1992 * do_i2c() - Handle the "i2c" command-line command
1993 * @cmdtp: Command data struct pointer
1994 * @flag: Command flag
1995 * @argc: Command-line argument count
1996 * @argv: Array of command-line arguments
1997 *
1998 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1999 * on error.
2000 */
54841ab5 2001static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
2002{
2003 cmd_tbl_t *c;
2004
e4099c8b
MS
2005#ifdef CONFIG_NEEDS_MANUAL_RELOC
2006 i2c_reloc();
2007#endif
2008
4444b221 2009 if (argc < 2)
4c12eeb8 2010 return CMD_RET_USAGE;
4444b221 2011
bfc3b77e
FM
2012 /* Strip off leading 'i2c' command argument */
2013 argc--;
2014 argv++;
2015
2016 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
2017
47e26b1b 2018 if (c)
4c12eeb8 2019 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 2020 else
4c12eeb8 2021 return CMD_RET_USAGE;
bb99ad6d 2022}
8bde7f77
WD
2023
2024/***************************************************/
088f1b19
KP
2025#ifdef CONFIG_SYS_LONGHELP
2026static char i2c_help_text[] =
59aa9df3 2027#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 2028 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
9a2accb4 2029#endif
fb0070e9 2030 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
3f4978c7 2031#if defined(CONFIG_SYS_I2C) || \
63656b76 2032 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
9bc2e4ee 2033 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 2034#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
2035#if defined(CONFIG_I2C_EDID)
2036 "i2c edid chip - print EDID configuration information\n"
2037#endif /* CONFIG_I2C_EDID */
fb0070e9 2038 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
2039 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
2040 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
2041 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
2042 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 2043 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
63656b76 2044 "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
ed16f146
LP
2045 "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
2046 " to I2C; the -s option selects bulk write in a single transaction\n"
63656b76
SG
2047#ifdef CONFIG_DM_I2C
2048 "i2c flags chip [flags] - set or get chip flags\n"
c10c8e31 2049 "i2c olen chip [offset_length] - set or get chip offset length\n"
63656b76 2050#endif
e43a27c4 2051 "i2c reset - re-init the I2C Controller\n"
c76fe474 2052#if defined(CONFIG_CMD_SDRAM)
fb0070e9 2053 "i2c sdram chip - print SDRAM configuration information\n"
90253178 2054#endif
088f1b19
KP
2055 "i2c speed [speed] - show or set I2C bus speed";
2056#endif
2057
2058U_BOOT_CMD(
ed16f146 2059 i2c, 7, 1, do_i2c,
088f1b19
KP
2060 "I2C sub-system",
2061 i2c_help_text
d9fc7032 2062);