[people/ms/u-boot.git] / common / cmd_eeprom.c

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Support for read and write access to EEPROM like memory devices. This
 * includes regular EEPROM as well as  FRAM (ferroelectic nonvolaile RAM).
 * FRAM devices read and write data at bus speed. In particular, there is no
 * write delay. Also, there is no limit imposed on the numer of bytes that can
 * be transferred with a single read or write.
 *
 * Use the following configuration options to ensure no unneeded performance
 * degradation (typical for EEPROM) is incured for FRAM memory:
 *
 * #define CONFIG_SYS_I2C_FRAM
 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 *
 */

#include <common.h>
#include <config.h>
#include <command.h>
#include <i2c.h>

extern void eeprom_init  (void);
extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
extern int  eeprom_write (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
#if defined(CONFIG_SYS_EEPROM_WREN)
extern int eeprom_write_enable (unsigned dev_addr, int state);
#endif


#if defined(CONFIG_SYS_EEPROM_X40430)
	/* Maximum number of times to poll for acknowledge after write */
#define MAX_ACKNOWLEDGE_POLLS	10
#endif

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_CMD_EEPROM)
int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	const char *const fmt =
		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";

#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
	if (argc == 6) {
		ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
		ulong addr = simple_strtoul (argv[3], NULL, 16);
		ulong off  = simple_strtoul (argv[4], NULL, 16);
		ulong cnt  = simple_strtoul (argv[5], NULL, 16);
#else
	if (argc == 5) {
		ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
		ulong addr = simple_strtoul (argv[2], NULL, 16);
		ulong off  = simple_strtoul (argv[3], NULL, 16);
		ulong cnt  = simple_strtoul (argv[4], NULL, 16);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

# ifndef CONFIG_SPI
		eeprom_init ();
# endif /* !CONFIG_SPI */

		if (strcmp (argv[1], "read") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		} else if (strcmp (argv[1], "write") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		}
	}

	cmd_usage(cmdtp);
	return 1;
}
#endif

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

#ifndef CONFIG_SPI
#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif

int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

	/* Read data until done or would cross a page boundary.
	 * We must write the address again when changing pages
	 * because the next page may be in a different device.
	 */
	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be ccessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)
		maxlen = 0x100 - blk_off;
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;
		if (len > maxlen)
			len = maxlen;
#endif

#ifdef CONFIG_SPI
		spi_read (addr, alen, buffer, len);
#else
		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;
#endif
		buffer += len;
		offset += len;
	}

	return rcode;
}

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

#if defined(CONFIG_SYS_EEPROM_X40430)
	uchar	contr_r_addr[2];
	uchar	addr_void[2];
	uchar	contr_reg[2];
	uchar	ctrl_reg_v;
	int	i;
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,1);
#endif
	/* Write data until done or would cross a write page boundary.
	 * We must write the address again when changing pages
	 * because the address counter only increments within a page.
	 */

	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be ccessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)

#define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
#define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))

		maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
#else
		maxlen = 0x100 - blk_off;
#endif
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;

		if (len > maxlen)
			len = maxlen;
#endif

#ifdef CONFIG_SPI
		spi_write (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_EEPROM_X40430)
		/* Get the value of the control register.
		 * Set current address (internal pointer in the x40430)
		 * to 0x1ff.
		 */
		contr_r_addr[0] = 9;
		contr_r_addr[1] = 0xff;
		addr_void[0]    = 0;
		addr_void[1]    = addr[1];
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
		contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
		addr_void[0]    |= CONFIG_SYS_I2C_EEPROM_ADDR;
#endif
		contr_reg[0] = 0xff;
		if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
			rcode = 1;
		}
		ctrl_reg_v = contr_reg[0];

		/* Are any of the eeprom blocks write protected?
		 */
		if (ctrl_reg_v & 0x18) {
			ctrl_reg_v &= ~0x18;   /* reset block protect bits  */
			ctrl_reg_v |=  0x02;   /* set write enable latch    */
			ctrl_reg_v &= ~0x04;   /* clear RWEL                */

			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Set register write enable latch.
			 */
			contr_reg[0] = 0x06;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Modify ctrl register.
			 */
			contr_reg[0] = ctrl_reg_v;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* The write (above) is an operation on NV memory.
			 * These can take some time (~5ms), and the device
			 * will not respond to further I2C messages till
			 * it's completed the write.
			 * So poll device for an I2C acknowledge.
			 * When we get one we know we can continue with other
			 * operations.
			 */
			contr_reg[0] = 0;
			for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
					break;	/* got ack */
#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
			}
			if (i == MAX_ACKNOWLEDGE_POLLS) {
				puts ("EEPROM poll acknowledge failed\n");
				rcode = 1;
			}
		}

		/* Is the write enable latch on?.
		 */
		else if (!(ctrl_reg_v & 0x02)) {
			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
			       rcode = 1;
			}
		}
		/* Write is enabled ... now write eeprom value.
		 */
#endif
		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;

#endif
		buffer += len;
		offset += len;

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
	}
#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,0);
#endif
	return rcode;
}

#ifndef CONFIG_SPI
int
eeprom_probe (unsigned dev_addr, unsigned offset)
{
	unsigned char chip;

	/* Probe the chip address
	 */
#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
	chip = offset >> 8;		/* block number */
#else
	chip = offset >> 16;		/* block number */
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

	chip |= dev_addr;		/* insert device address */

	return (i2c_probe (chip));
}
#endif

/*-----------------------------------------------------------------------
 * Set default values
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif

void eeprom_init  (void)
{
#if defined(CONFIG_SPI)
	spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || \
    defined(CONFIG_SOFT_I2C)
	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
/*-----------------------------------------------------------------------
 */

/***************************************************/

#if defined(CONFIG_CMD_EEPROM)

#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
	eeprom,	6,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  devaddr addr off cnt\n"
	"eeprom write devaddr addr off cnt\n"
	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
);
#else /* One EEPROM */
U_BOOT_CMD(
	eeprom,	5,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  addr off cnt\n"
	"eeprom write addr off cnt\n"
	"       - read/write `cnt' bytes at EEPROM offset `off'"
);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

#endif
Commit	Line	Data
3863585b WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
d4f5c728	25	/*
	26	* Support for read and write access to EEPROM like memory devices. This
	27	* includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
	28	* FRAM devices read and write data at bus speed. In particular, there is no
	29	* write delay. Also, there is no limit imposed on the numer of bytes that can
	30	* be transferred with a single read or write.
6617aae9	31	*
d4f5c728	32	* Use the following configuration options to ensure no unneeded performance
d4f5c728	33	* degradation (typical for EEPROM) is incured for FRAM memory:
6617aae9	34	*
6d0f6bcf JCPV	35	* #define CONFIG_SYS_I2C_FRAM
6d0f6bcf JCPV	36	* #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
d4f5c728	37	*
	38	*/
	39
3863585b WD	40	#include <common.h>
	41	#include <config.h>
	42	#include <command.h>
	43	#include <i2c.h>
	44
3863585b WD	45	extern void eeprom_init (void);
	46	extern int eeprom_read (unsigned dev_addr, unsigned offset,
	47	uchar *buffer, unsigned cnt);
	48	extern int eeprom_write (unsigned dev_addr, unsigned offset,
	49	uchar *buffer, unsigned cnt);
6d0f6bcf	50	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	51	extern int eeprom_write_enable (unsigned dev_addr, int state);
98f4a3df SR	52	#endif
3863585b WD	53
3863585b WD	54
6d0f6bcf	55	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	56	/* Maximum number of times to poll for acknowledge after write */
	57	#define MAX_ACKNOWLEDGE_POLLS 10
	58	#endif
	59
	60	/* ------------------------------------------------------------------------- */
	61
baa26db4	62	#if defined(CONFIG_CMD_EEPROM)
3863585b WD	63	int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	64	{
	65	const char *const fmt =
	66	"\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
	67
6d0f6bcf	68	#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
3863585b WD	69	if (argc == 6) {
	70	ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
	71	ulong addr = simple_strtoul (argv[3], NULL, 16);
	72	ulong off = simple_strtoul (argv[4], NULL, 16);
	73	ulong cnt = simple_strtoul (argv[5], NULL, 16);
	74	#else
	75	if (argc == 5) {
6d0f6bcf	76	ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
3863585b WD	77	ulong addr = simple_strtoul (argv[2], NULL, 16);
	78	ulong off = simple_strtoul (argv[3], NULL, 16);
	79	ulong cnt = simple_strtoul (argv[4], NULL, 16);
6d0f6bcf	80	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
3863585b WD	81
	82	# ifndef CONFIG_SPI
	83	eeprom_init ();
	84	# endif /* !CONFIG_SPI */
	85
	86	if (strcmp (argv[1], "read") == 0) {
	87	int rcode;
	88
	89	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	90
	91	rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
	92
4b9206ed	93	puts ("done\n");
3863585b WD	94	return rcode;
	95	} else if (strcmp (argv[1], "write") == 0) {
	96	int rcode;
	97
	98	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	99
	100	rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
	101
4b9206ed	102	puts ("done\n");
3863585b WD	103	return rcode;
	104	}
	105	}
	106
62c3ae7c	107	cmd_usage(cmdtp);
3863585b WD	108	return 1;
3863585b WD	109	}
90253178	110	#endif
3863585b WD	111
	112	/*-----------------------------------------------------------------------
	113	*
6d0f6bcf	114	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	115	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	116	*
6d0f6bcf	117	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	118	* 0x00000nxx for EEPROM address selectors and page number at n.
	119	*/
	120
3863585b	121	#ifndef CONFIG_SPI
6d0f6bcf JCPV	122	#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
6d0f6bcf JCPV	123	#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
3863585b WD	124	#endif
	125	#endif
	126
	127	int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	128	{
	129	unsigned end = offset + cnt;
	130	unsigned blk_off;
	131	int rcode = 0;
	132
	133	/* Read data until done or would cross a page boundary.
	134	* We must write the address again when changing pages
	135	* because the next page may be in a different device.
	136	*/
	137	while (offset < end) {
d4f5c728	138	unsigned alen, len;
6d0f6bcf	139	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	140	unsigned maxlen;
	141	#endif
	142
6d0f6bcf	143	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	144	uchar addr[2];
	145
	146	blk_off = offset & 0xFF; /* block offset */
	147
	148	addr[0] = offset >> 8; /* block number */
	149	addr[1] = blk_off; /* block offset */
	150	alen = 2;
	151	#else
	152	uchar addr[3];
	153
	154	blk_off = offset & 0xFF; /* block offset */
	155
	156	addr[0] = offset >> 16; /* block number */
	157	addr[1] = offset >> 8; /* upper address octet */
	158	addr[2] = blk_off; /* lower address octet */
	159	alen = 3;
6d0f6bcf	160	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	161
	162	addr[0] \|= dev_addr; /* insert device address */
	163
d4f5c728	164	len = end - offset;
	165
	166	/*
	167	* For a FRAM device there is no limit on the number of the
	168	* bytes that can be ccessed with the single read or write
	169	* operation.
	170	*/
6d0f6bcf	171	#if !defined(CONFIG_SYS_I2C_FRAM)
3863585b WD	172	maxlen = 0x100 - blk_off;
	173	if (maxlen > I2C_RXTX_LEN)
	174	maxlen = I2C_RXTX_LEN;
3863585b WD	175	if (len > maxlen)
3863585b WD	176	len = maxlen;
d4f5c728	177	#endif
d4f5c728	178
3863585b WD	179	#ifdef CONFIG_SPI
	180	spi_read (addr, alen, buffer, len);
	181	#else
	182	if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
	183	rcode = 1;
	184	#endif
	185	buffer += len;
	186	offset += len;
	187	}
d4f5c728	188
3863585b WD	189	return rcode;
	190	}
	191
	192	/*-----------------------------------------------------------------------
	193	*
6d0f6bcf	194	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	195	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	196	*
6d0f6bcf	197	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	198	* 0x00000nxx for EEPROM address selectors and page number at n.
	199	*/
	200
	201	int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	202	{
	203	unsigned end = offset + cnt;
	204	unsigned blk_off;
	205	int rcode = 0;
	206
6d0f6bcf	207	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	208	uchar contr_r_addr[2];
	209	uchar addr_void[2];
	210	uchar contr_reg[2];
	211	uchar ctrl_reg_v;
	212	int i;
	213	#endif
	214
6d0f6bcf	215	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	216	eeprom_write_enable (dev_addr,1);
98f4a3df SR	217	#endif
3863585b WD	218	/* Write data until done or would cross a write page boundary.
	219	* We must write the address again when changing pages
	220	* because the address counter only increments within a page.
	221	*/
	222
	223	while (offset < end) {
d4f5c728	224	unsigned alen, len;
6d0f6bcf	225	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	226	unsigned maxlen;
	227	#endif
	228
6d0f6bcf	229	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	230	uchar addr[2];
	231
	232	blk_off = offset & 0xFF; /* block offset */
	233
	234	addr[0] = offset >> 8; /* block number */
	235	addr[1] = blk_off; /* block offset */
	236	alen = 2;
	237	#else
	238	uchar addr[3];
	239
	240	blk_off = offset & 0xFF; /* block offset */
	241
	242	addr[0] = offset >> 16; /* block number */
	243	addr[1] = offset >> 8; /* upper address octet */
	244	addr[2] = blk_off; /* lower address octet */
	245	alen = 3;
6d0f6bcf	246	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	247
	248	addr[0] \|= dev_addr; /* insert device address */
	249
d4f5c728	250	len = end - offset;
	251
	252	/*
	253	* For a FRAM device there is no limit on the number of the
	254	* bytes that can be ccessed with the single read or write
	255	* operation.
	256	*/
6d0f6bcf	257	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	258
6d0f6bcf	259	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b	260
6d0f6bcf	261	#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b WD	262	#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
	263
	264	maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
	265	#else
	266	maxlen = 0x100 - blk_off;
	267	#endif
	268	if (maxlen > I2C_RXTX_LEN)
	269	maxlen = I2C_RXTX_LEN;
	270
3863585b WD	271	if (len > maxlen)
3863585b WD	272	len = maxlen;
d4f5c728	273	#endif
d4f5c728	274
3863585b WD	275	#ifdef CONFIG_SPI
	276	spi_write (addr, alen, buffer, len);
	277	#else
6d0f6bcf	278	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	279	/* Get the value of the control register.
	280	* Set current address (internal pointer in the x40430)
	281	* to 0x1ff.
	282	*/
	283	contr_r_addr[0] = 9;
	284	contr_r_addr[1] = 0xff;
	285	addr_void[0] = 0;
	286	addr_void[1] = addr[1];
6d0f6bcf JCPV	287	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
	288	contr_r_addr[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
	289	addr_void[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
3863585b WD	290	#endif
	291	contr_reg[0] = 0xff;
	292	if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
	293	rcode = 1;
	294	}
	295	ctrl_reg_v = contr_reg[0];
	296
	297	/* Are any of the eeprom blocks write protected?
	298	*/
	299	if (ctrl_reg_v & 0x18) {
	300	ctrl_reg_v &= ~0x18; /* reset block protect bits */
	301	ctrl_reg_v \|= 0x02; /* set write enable latch */
	302	ctrl_reg_v &= ~0x04; /* clear RWEL */
	303
	304	/* Set write enable latch.
	305	*/
	306	contr_reg[0] = 0x02;
	307	if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
	308	rcode = 1;
	309	}
	310
	311	/* Set register write enable latch.
	312	*/
	313	contr_reg[0] = 0x06;
	314	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	315	rcode = 1;
	316	}
	317
	318	/* Modify ctrl register.
	319	*/
	320	contr_reg[0] = ctrl_reg_v;
	321	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	322	rcode = 1;
	323	}
	324
	325	/* The write (above) is an operation on NV memory.
	326	* These can take some time (~5ms), and the device
	327	* will not respond to further I2C messages till
	328	* it's completed the write.
	329	* So poll device for an I2C acknowledge.
	330	* When we get one we know we can continue with other
	331	* operations.
	332	*/
	333	contr_reg[0] = 0;
	334	for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
aacf9a49	335	if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
3863585b	336	break; /* got ack */
6d0f6bcf JCPV	337	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	338	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	339	#endif
	340	}
	341	if (i == MAX_ACKNOWLEDGE_POLLS) {
4b9206ed	342	puts ("EEPROM poll acknowledge failed\n");
3863585b WD	343	rcode = 1;
	344	}
	345	}
	346
	347	/* Is the write enable latch on?.
	348	*/
	349	else if (!(ctrl_reg_v & 0x02)) {
	350	/* Set write enable latch.
	351	*/
	352	contr_reg[0] = 0x02;
	353	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	354	rcode = 1;
	355	}
	356	}
	357	/* Write is enabled ... now write eeprom value.
	358	*/
	359	#endif
	360	if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
	361	rcode = 1;
	362
	363	#endif
	364	buffer += len;
	365	offset += len;
	366
6d0f6bcf JCPV	367	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	368	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	369	#endif
3863585b WD	370	}
6d0f6bcf	371	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	372	eeprom_write_enable (dev_addr,0);
98f4a3df SR	373	#endif
3863585b WD	374	return rcode;
	375	}
	376
6dd652fa WD	377	#ifndef CONFIG_SPI
	378	int
	379	eeprom_probe (unsigned dev_addr, unsigned offset)
	380	{
	381	unsigned char chip;
	382
	383	/* Probe the chip address
	384	*/
6d0f6bcf	385	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
6dd652fa WD	386	chip = offset >> 8; /* block number */
	387	#else
	388	chip = offset >> 16; /* block number */
6d0f6bcf	389	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
6dd652fa WD	390
	391	chip \|= dev_addr; /* insert device address */
	392
	393	return (i2c_probe (chip));
	394	}
	395	#endif
	396
3863585b WD	397	/*-----------------------------------------------------------------------
	398	* Set default values
	399	*/
6d0f6bcf JCPV	400	#ifndef CONFIG_SYS_I2C_SPEED
6d0f6bcf JCPV	401	#define CONFIG_SYS_I2C_SPEED 50000
3863585b WD	402	#endif
3863585b WD	403
3863585b WD	404	void eeprom_init (void)
	405	{
	406	#if defined(CONFIG_SPI)
	407	spi_init_f ();
	408	#endif
	409	#if defined(CONFIG_HARD_I2C) \|\| \
	410	defined(CONFIG_SOFT_I2C)
6d0f6bcf	411	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3863585b WD	412	#endif
	413	}
	414	/*-----------------------------------------------------------------------
	415	*/
90253178	416
8bde7f77 WD	417	/***************************************************/
8bde7f77 WD	418
baa26db4	419	#if defined(CONFIG_CMD_EEPROM)
8bde7f77	420
6d0f6bcf	421	#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
0d498393 WD	422	U_BOOT_CMD(
0d498393 WD	423	eeprom, 6, 1, do_eeprom,
2fb2604d	424	"EEPROM sub-system",
8bde7f77 WD	425	"read devaddr addr off cnt\n"
8bde7f77 WD	426	"eeprom write devaddr addr off cnt\n"
a89c33db	427	" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
8bde7f77 WD	428	);
8bde7f77 WD	429	#else /* One EEPROM */
0d498393 WD	430	U_BOOT_CMD(
0d498393 WD	431	eeprom, 5, 1, do_eeprom,
2fb2604d	432	"EEPROM sub-system",
8bde7f77 WD	433	"read addr off cnt\n"
8bde7f77 WD	434	"eeprom write addr off cnt\n"
a89c33db	435	" - read/write `cnt' bytes at EEPROM offset `off'"
8bde7f77	436	);
6d0f6bcf	437	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
8bde7f77	438
90253178	439	#endif