[people/ms/u-boot.git] / common / cmd_fpga.c

/*
 * (C) Copyright 2000, 2001
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 *  FPGA support
 */
#include <common.h>
#include <command.h>
#if defined(CONFIG_CMD_NET)
#include <net.h>
#endif
#include <fpga.h>
#include <malloc.h>

/* Local functions */
static int fpga_get_op (char *opstr);

/* Local defines */
#define FPGA_NONE   -1
#define FPGA_INFO   0
#define FPGA_LOAD   1
#define FPGA_LOADB  2
#define FPGA_DUMP   3
#define FPGA_LOADMK 4

/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
	unsigned int length;
	unsigned int swapsize;
	char buffer[80];
	unsigned char *dataptr;
	unsigned int i;
	int rc;

	dataptr = (unsigned char *)fpgadata;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	dataptr+=length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	if (*dataptr++ != 0x61) {
		debug("%s: Design name identifier not recognized "
			"in bitstream\n",
			__func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;

	printf("  design filename = \"%s\"\n", buffer);

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number identifier not recognized "
			"in bitstream\n",
			__func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  part number = \"%s\"\n", buffer);

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  date = \"%s\"\n", buffer);

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",
			__func__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  time = \"%s\"\n", buffer);

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length identifier not recognized in bitstream\n",
			__func__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr     <<24) +
	           ((unsigned int) *(dataptr+1) <<16) +
	           ((unsigned int) *(dataptr+2) <<8 ) +
	           ((unsigned int) *(dataptr+3)     ) ;
	dataptr+=4;
	printf("  bytes in bitstream = %d\n", swapsize);

	rc = fpga_load(dev, dataptr, swapsize);
	return rc;
#else
	printf("Bitstream support only for Xilinx devices\n");
	return FPGA_FAIL;
#endif
}

/* ------------------------------------------------------------------------- */
/* command form:
 *   fpga <op> <device number> <data addr> <datasize>
 * where op is 'load', 'dump', or 'info'
 * If there is no device number field, the fpga environment variable is used.
 * If there is no data addr field, the fpgadata environment variable is used.
 * The info command requires no data address field.
 */
int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int op, dev = FPGA_INVALID_DEVICE;
	size_t data_size = 0;
	void *fpga_data = NULL;
	char *devstr = getenv ("fpga");
	char *datastr = getenv ("fpgadata");
	int rc = FPGA_FAIL;
	int wrong_parms = 0;
#if defined (CONFIG_FIT)
	const char *fit_uname = NULL;
	ulong fit_addr;
#endif

	if (devstr)
		dev = (int) simple_strtoul (devstr, NULL, 16);
	if (datastr)
		fpga_data = (void *) simple_strtoul (datastr, NULL, 16);

	switch (argc) {
	case 5:		/* fpga <op> <dev> <data> <datasize> */
		data_size = simple_strtoul (argv[4], NULL, 16);

	case 4:		/* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
		if (fit_parse_subimage (argv[3], (ulong)fpga_data,
					&fit_addr, &fit_uname)) {
			fpga_data = (void *)fit_addr;
			debug("*  fpga: subimage '%s' from FIT image "
				"at 0x%08lx\n",
				fit_uname, fit_addr);
		} else
#endif
		{
			fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
			debug("*  fpga: cmdline image address = 0x%08lx\n",
				(ulong)fpga_data);
		}
		debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);

	case 3:		/* fpga <op> <dev | data addr> */
		dev = (int) simple_strtoul (argv[2], NULL, 16);
		debug("%s: device = %d\n", __func__, dev);
		/* FIXME - this is a really weak test */
		if ((argc == 3) && (dev > fpga_count ())) {	/* must be buffer ptr */
			debug("%s: Assuming buffer pointer in arg 3\n",
				__func__);

#if defined(CONFIG_FIT)
			if (fit_parse_subimage (argv[2], (ulong)fpga_data,
						&fit_addr, &fit_uname)) {
				fpga_data = (void *)fit_addr;
				debug("*  fpga: subimage '%s' from FIT image "
					"at 0x%08lx\n",
					fit_uname, fit_addr);
			} else
#endif
			{
				fpga_data = (void *) dev;
				debug("*  fpga: cmdline image address = "
					"0x%08lx\n", (ulong)fpga_data);
			}

			debug("%s: fpga_data = 0x%x\n",
				__func__, (uint) fpga_data);
			dev = FPGA_INVALID_DEVICE;	/* reset device num */
		}

	case 2:		/* fpga <op> */
		op = (int) fpga_get_op (argv[1]);
		break;

	default:
		debug("%s: Too many or too few args (%d)\n",
			__func__, argc);
		op = FPGA_NONE;	/* force usage display */
		break;
	}

	if (dev == FPGA_INVALID_DEVICE) {
		puts("FPGA device not specified\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
	case FPGA_INFO:
		break;
	case FPGA_LOAD:
	case FPGA_LOADB:
	case FPGA_DUMP:
		if (!fpga_data || !data_size)
			wrong_parms = 1;
		break;
	case FPGA_LOADMK:
		if (!fpga_data)
			wrong_parms = 1;
		break;
	}

	if (wrong_parms) {
		puts("Wrong parameters for FPGA request\n");
		op = FPGA_NONE;
	}

	switch (op) {
	case FPGA_NONE:
		return CMD_RET_USAGE;

	case FPGA_INFO:
		rc = fpga_info (dev);
		break;

	case FPGA_LOAD:
		rc = fpga_load (dev, fpga_data, data_size);
		break;

	case FPGA_LOADB:
		rc = fpga_loadbitstream(dev, fpga_data, data_size);
		break;

	case FPGA_LOADMK:
		switch (genimg_get_format (fpga_data)) {
		case IMAGE_FORMAT_LEGACY:
			{
				image_header_t *hdr = (image_header_t *)fpga_data;
				ulong	data;

				data = (ulong)image_get_data (hdr);
				data_size = image_get_data_size (hdr);
				rc = fpga_load (dev, (void *)data, data_size);
			}
			break;
#if defined(CONFIG_FIT)
		case IMAGE_FORMAT_FIT:
			{
				const void *fit_hdr = (const void *)fpga_data;
				int noffset;
				const void *fit_data;

				if (fit_uname == NULL) {
					puts ("No FIT subimage unit name\n");
					return 1;
				}

				if (!fit_check_format (fit_hdr)) {
					puts ("Bad FIT image format\n");
					return 1;
				}

				/* get fpga component image node offset */
				noffset = fit_image_get_node (fit_hdr, fit_uname);
				if (noffset < 0) {
					printf ("Can't find '%s' FIT subimage\n", fit_uname);
					return 1;
				}

				/* verify integrity */
				if (!fit_image_check_hashes (fit_hdr, noffset)) {
					puts ("Bad Data Hash\n");
					return 1;
				}

				/* get fpga subimage data address and length */
				if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
					puts ("Could not find fpga subimage data\n");
					return 1;
				}

				rc = fpga_load (dev, fit_data, data_size);
			}
			break;
#endif
		default:
			puts ("** Unknown image type\n");
			rc = FPGA_FAIL;
			break;
		}
		break;

	case FPGA_DUMP:
		rc = fpga_dump (dev, fpga_data, data_size);
		break;

	default:
		printf ("Unknown operation\n");
		return CMD_RET_USAGE;
	}
	return (rc);
}

/*
 * Map op to supported operations.  We don't use a table since we
 * would just have to relocate it from flash anyway.
 */
static int fpga_get_op (char *opstr)
{
	int op = FPGA_NONE;

	if (!strcmp ("info", opstr)) {
		op = FPGA_INFO;
	} else if (!strcmp ("loadb", opstr)) {
		op = FPGA_LOADB;
	} else if (!strcmp ("load", opstr)) {
		op = FPGA_LOAD;
	} else if (!strcmp ("loadmk", opstr)) {
		op = FPGA_LOADMK;
	} else if (!strcmp ("dump", opstr)) {
		op = FPGA_DUMP;
	}

	if (op == FPGA_NONE) {
		printf ("Unknown fpga operation \"%s\"\n", opstr);
	}
	return op;
}

U_BOOT_CMD (fpga, 6, 1, do_fpga,
	"loadable FPGA image support",
	"[operation type] [device number] [image address] [image size]\n"
	"fpga operations:\n"
	"  dump\t[dev]\t\t\tLoad device to memory buffer\n"
	"  info\t[dev]\t\t\tlist known device information\n"
	"  load\t[dev] [address] [size]\tLoad device from memory buffer\n"
	"  loadb\t[dev] [address] [size]\t"
	"Load device from bitstream buffer (Xilinx only)\n"
	"  loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
	"\n"
	"\tFor loadmk operating on FIT format uImage address must include\n"
	"\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
);
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	/*
	26	* FPGA support
	27	*/
	28	#include <common.h>
	29	#include <command.h>
baa26db4	30	#if defined(CONFIG_CMD_NET)
4a9cbbe8 WD	31	#include <net.h>
4a9cbbe8 WD	32	#endif
8bde7f77	33	#include <fpga.h>
c3d2b4b4	34	#include <malloc.h>
4a9cbbe8	35
4a9cbbe8	36	/* Local functions */
d4ca31c4	37	static int fpga_get_op (char *opstr);
4a9cbbe8 WD	38
	39	/* Local defines */
	40	#define FPGA_NONE -1
	41	#define FPGA_INFO 0
	42	#define FPGA_LOAD 1
30ce5ab0	43	#define FPGA_LOADB 2
4a9cbbe8	44	#define FPGA_DUMP 3
f0ff4692	45	#define FPGA_LOADMK 4
4a9cbbe8	46
30ce5ab0 WD	47	/* Convert bitstream data and load into the fpga */
	48	int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
	49	{
0133502e	50	#if defined(CONFIG_FPGA_XILINX)
8b019da6	51	unsigned int length;
8b019da6	52	unsigned int swapsize;
30ce5ab0	53	char buffer[80];
8b019da6	54	unsigned char *dataptr;
8b019da6	55	unsigned int i;
30ce5ab0 WD	56	int rc;
30ce5ab0 WD	57
77ddac94	58	dataptr = (unsigned char *)fpgadata;
30ce5ab0	59
8b019da6 WD	60	/* skip the first bytes of the bitsteam, their meaning is unknown */
	61	length = (dataptr << 8) + (dataptr+1);
	62	dataptr+=2;
	63	dataptr+=length;
30ce5ab0 WD	64
30ce5ab0 WD	65	/* get design name (identifier, length, string) */
8b019da6 WD	66	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	67	dataptr+=2;
30ce5ab0	68	if (*dataptr++ != 0x61) {
06297db0 SB	69	debug("%s: Design name identifier not recognized "
	70	"in bitstream\n",
	71	__func__);
30ce5ab0 WD	72	return FPGA_FAIL;
	73	}
	74
a562e1bd	75	length = (dataptr << 8) + (dataptr+1);
30ce5ab0 WD	76	dataptr+=2;
30ce5ab0 WD	77	for(i=0;i<length;i++)
d0ff51ba	78	buffer[i] = *dataptr++;
a562e1bd	79
8b019da6	80	printf(" design filename = \"%s\"\n", buffer);
30ce5ab0 WD	81
	82	/* get part number (identifier, length, string) */
	83	if (*dataptr++ != 0x62) {
06297db0 SB	84	printf("%s: Part number identifier not recognized "
	85	"in bitstream\n",
	86	__func__);
30ce5ab0 WD	87	return FPGA_FAIL;
30ce5ab0 WD	88	}
a562e1bd	89
8b019da6 WD	90	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	91	dataptr+=2;
a562e1bd	92	for(i=0;i<length;i++)
d0ff51ba	93	buffer[i] = *dataptr++;
8b019da6	94	printf(" part number = \"%s\"\n", buffer);
a562e1bd	95
30ce5ab0 WD	96	/* get date (identifier, length, string) */
30ce5ab0 WD	97	if (*dataptr++ != 0x63) {
8b019da6	98	printf("%s: Date identifier not recognized in bitstream\n",
06297db0	99	__func__);
30ce5ab0 WD	100	return FPGA_FAIL;
30ce5ab0 WD	101	}
a562e1bd	102
8b019da6 WD	103	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	104	dataptr+=2;
30ce5ab0	105	for(i=0;i<length;i++)
d0ff51ba	106	buffer[i] = *dataptr++;
8b019da6	107	printf(" date = \"%s\"\n", buffer);
30ce5ab0 WD	108
	109	/* get time (identifier, length, string) */
	110	if (*dataptr++ != 0x64) {
06297db0 SB	111	printf("%s: Time identifier not recognized in bitstream\n",
06297db0 SB	112	__func__);
30ce5ab0 WD	113	return FPGA_FAIL;
30ce5ab0 WD	114	}
a562e1bd	115
8b019da6 WD	116	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	117	dataptr+=2;
30ce5ab0	118	for(i=0;i<length;i++)
d0ff51ba	119	buffer[i] = *dataptr++;
8b019da6	120	printf(" time = \"%s\"\n", buffer);
a562e1bd	121
30ce5ab0 WD	122	/* get fpga data length (identifier, length) */
30ce5ab0 WD	123	if (*dataptr++ != 0x65) {
8b019da6	124	printf("%s: Data length identifier not recognized in bitstream\n",
06297db0	125	__func__);
30ce5ab0 WD	126	return FPGA_FAIL;
30ce5ab0 WD	127	}
8f79e4c2 WD	128	swapsize = ((unsigned int) *dataptr <<24) +
	129	((unsigned int) *(dataptr+1) <<16) +
	130	((unsigned int) *(dataptr+2) <<8 ) +
8b019da6	131	((unsigned int) *(dataptr+3) ) ;
30ce5ab0	132	dataptr+=4;
8b019da6	133	printf(" bytes in bitstream = %d\n", swapsize);
a562e1bd	134
c26acc1a	135	rc = fpga_load(dev, dataptr, swapsize);
30ce5ab0 WD	136	return rc;
30ce5ab0 WD	137	#else
8b019da6	138	printf("Bitstream support only for Xilinx devices\n");
30ce5ab0 WD	139	return FPGA_FAIL;
	140	#endif
	141	}
	142
4a9cbbe8 WD	143	/* ------------------------------------------------------------------------- */
	144	/* command form:
	145	* fpga <op> <device number> <data addr> <datasize>
	146	* where op is 'load', 'dump', or 'info'
	147	* If there is no device number field, the fpga environment variable is used.
	148	* If there is no data addr field, the fpgadata environment variable is used.
	149	* The info command requires no data address field.
	150	*/
54841ab5	151	int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
4a9cbbe8	152	{
d4ca31c4 WD	153	int op, dev = FPGA_INVALID_DEVICE;
	154	size_t data_size = 0;
	155	void *fpga_data = NULL;
	156	char *devstr = getenv ("fpga");
	157	char *datastr = getenv ("fpgadata");
	158	int rc = FPGA_FAIL;
a790b5b2	159	int wrong_parms = 0;
c28c4d19 MB	160	#if defined (CONFIG_FIT)
	161	const char *fit_uname = NULL;
	162	ulong fit_addr;
	163	#endif
d4ca31c4 WD	164
	165	if (devstr)
	166	dev = (int) simple_strtoul (devstr, NULL, 16);
	167	if (datastr)
	168	fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
	169
	170	switch (argc) {
	171	case 5: /* fpga <op> <dev> <data> <datasize> */
	172	data_size = simple_strtoul (argv[4], NULL, 16);
c28c4d19	173
d4ca31c4	174	case 4: /* fpga <op> <dev> <data> */
c28c4d19 MB	175	#if defined(CONFIG_FIT)
	176	if (fit_parse_subimage (argv[3], (ulong)fpga_data,
	177	&fit_addr, &fit_uname)) {
	178	fpga_data = (void *)fit_addr;
06297db0 SB	179	debug("* fpga: subimage '%s' from FIT image "
	180	"at 0x%08lx\n",
	181	fit_uname, fit_addr);
c28c4d19 MB	182	} else
	183	#endif
	184	{
	185	fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
06297db0 SB	186	debug("* fpga: cmdline image address = 0x%08lx\n",
06297db0 SB	187	(ulong)fpga_data);
c28c4d19	188	}
06297db0	189	debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
c28c4d19	190
d4ca31c4 WD	191	case 3: /* fpga <op> <dev \| data addr> */
d4ca31c4 WD	192	dev = (int) simple_strtoul (argv[2], NULL, 16);
06297db0	193	debug("%s: device = %d\n", __func__, dev);
d4ca31c4 WD	194	/* FIXME - this is a really weak test */
d4ca31c4 WD	195	if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
06297db0 SB	196	debug("%s: Assuming buffer pointer in arg 3\n",
06297db0 SB	197	__func__);
c28c4d19 MB	198
	199	#if defined(CONFIG_FIT)
	200	if (fit_parse_subimage (argv[2], (ulong)fpga_data,
	201	&fit_addr, &fit_uname)) {
	202	fpga_data = (void *)fit_addr;
06297db0 SB	203	debug("* fpga: subimage '%s' from FIT image "
	204	"at 0x%08lx\n",
	205	fit_uname, fit_addr);
c28c4d19 MB	206	} else
	207	#endif
	208	{
	209	fpga_data = (void *) dev;
06297db0 SB	210	debug("* fpga: cmdline image address = "
06297db0 SB	211	"0x%08lx\n", (ulong)fpga_data);
c28c4d19 MB	212	}
c28c4d19 MB	213
06297db0 SB	214	debug("%s: fpga_data = 0x%x\n",
06297db0 SB	215	__func__, (uint) fpga_data);
d4ca31c4 WD	216	dev = FPGA_INVALID_DEVICE; /* reset device num */
d4ca31c4 WD	217	}
c28c4d19	218
d4ca31c4 WD	219	case 2: /* fpga <op> */
	220	op = (int) fpga_get_op (argv[1]);
	221	break;
c28c4d19	222
d4ca31c4	223	default:
06297db0 SB	224	debug("%s: Too many or too few args (%d)\n",
06297db0 SB	225	__func__, argc);
d4ca31c4 WD	226	op = FPGA_NONE; /* force usage display */
	227	break;
	228	}
	229
a790b5b2 SB	230	if (dev == FPGA_INVALID_DEVICE) {
	231	puts("FPGA device not specified\n");
	232	op = FPGA_NONE;
	233	}
	234
	235	switch (op) {
	236	case FPGA_NONE:
	237	case FPGA_INFO:
	238	break;
	239	case FPGA_LOAD:
	240	case FPGA_LOADB:
	241	case FPGA_DUMP:
	242	if (!fpga_data \|\| !data_size)
	243	wrong_parms = 1;
	244	break;
	245	case FPGA_LOADMK:
	246	if (!fpga_data)
	247	wrong_parms = 1;
	248	break;
	249	}
	250
	251	if (wrong_parms) {
	252	puts("Wrong parameters for FPGA request\n");
	253	op = FPGA_NONE;
	254	}
	255
d4ca31c4 WD	256	switch (op) {
d4ca31c4 WD	257	case FPGA_NONE:
4c12eeb8	258	return CMD_RET_USAGE;
d4ca31c4 WD	259
	260	case FPGA_INFO:
	261	rc = fpga_info (dev);
	262	break;
	263
	264	case FPGA_LOAD:
	265	rc = fpga_load (dev, fpga_data, data_size);
	266	break;
	267
30ce5ab0 WD	268	case FPGA_LOADB:
	269	rc = fpga_loadbitstream(dev, fpga_data, data_size);
	270	break;
	271
f0ff4692	272	case FPGA_LOADMK:
9a4daad0	273	switch (genimg_get_format (fpga_data)) {
d5934ad7 MB	274	case IMAGE_FORMAT_LEGACY:
	275	{
	276	image_header_t hdr = (image_header_t )fpga_data;
	277	ulong data;
	278
d5934ad7 MB	279	data = (ulong)image_get_data (hdr);
	280	data_size = image_get_data_size (hdr);
	281	rc = fpga_load (dev, (void *)data, data_size);
f0ff4692	282	}
d5934ad7 MB	283	break;
	284	#if defined(CONFIG_FIT)
	285	case IMAGE_FORMAT_FIT:
c28c4d19 MB	286	{
	287	const void fit_hdr = (const void )fpga_data;
	288	int noffset;
e6a857da	289	const void *fit_data;
c28c4d19 MB	290
	291	if (fit_uname == NULL) {
	292	puts ("No FIT subimage unit name\n");
	293	return 1;
	294	}
	295
	296	if (!fit_check_format (fit_hdr)) {
	297	puts ("Bad FIT image format\n");
	298	return 1;
	299	}
	300
	301	/* get fpga component image node offset */
	302	noffset = fit_image_get_node (fit_hdr, fit_uname);
	303	if (noffset < 0) {
	304	printf ("Can't find '%s' FIT subimage\n", fit_uname);
	305	return 1;
	306	}
	307
	308	/* verify integrity */
	309	if (!fit_image_check_hashes (fit_hdr, noffset)) {
	310	puts ("Bad Data Hash\n");
	311	return 1;
	312	}
	313
	314	/* get fpga subimage data address and length */
	315	if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
	316	puts ("Could not find fpga subimage data\n");
	317	return 1;
	318	}
	319
	320	rc = fpga_load (dev, fit_data, data_size);
	321	}
d5934ad7 MB	322	break;
	323	#endif
	324	default:
	325	puts ("** Unknown image type\n");
	326	rc = FPGA_FAIL;
	327	break;
f0ff4692 SR	328	}
	329	break;
	330
d4ca31c4 WD	331	case FPGA_DUMP:
	332	rc = fpga_dump (dev, fpga_data, data_size);
	333	break;
	334
	335	default:
8b019da6	336	printf ("Unknown operation\n");
4c12eeb8	337	return CMD_RET_USAGE;
d4ca31c4 WD	338	}
d4ca31c4 WD	339	return (rc);
4a9cbbe8 WD	340	}
4a9cbbe8 WD	341
4a9cbbe8 WD	342	/*
	343	* Map op to supported operations. We don't use a table since we
	344	* would just have to relocate it from flash anyway.
	345	*/
d4ca31c4	346	static int fpga_get_op (char *opstr)
4a9cbbe8 WD	347	{
	348	int op = FPGA_NONE;
	349
	350	if (!strcmp ("info", opstr)) {
	351	op = FPGA_INFO;
30ce5ab0 WD	352	} else if (!strcmp ("loadb", opstr)) {
30ce5ab0 WD	353	op = FPGA_LOADB;
d4ca31c4	354	} else if (!strcmp ("load", opstr)) {
4a9cbbe8	355	op = FPGA_LOAD;
f0ff4692 SR	356	} else if (!strcmp ("loadmk", opstr)) {
f0ff4692 SR	357	op = FPGA_LOADMK;
d4ca31c4	358	} else if (!strcmp ("dump", opstr)) {
4a9cbbe8 WD	359	op = FPGA_DUMP;
	360	}
	361
d4ca31c4	362	if (op == FPGA_NONE) {
4a9cbbe8 WD	363	printf ("Unknown fpga operation \"%s\"\n", opstr);
	364	}
	365	return op;
	366	}
	367
d4ca31c4	368	U_BOOT_CMD (fpga, 6, 1, do_fpga,
a790b5b2 SB	369	"loadable FPGA image support",
	370	"[operation type] [device number] [image address] [image size]\n"
	371	"fpga operations:\n"
	372	" dump\t[dev]\t\t\tLoad device to memory buffer\n"
	373	" info\t[dev]\t\t\tlist known device information\n"
	374	" load\t[dev] [address] [size]\tLoad device from memory buffer\n"
	375	" loadb\t[dev] [address] [size]\t"
	376	"Load device from bitstream buffer (Xilinx only)\n"
	377	" loadmk [dev] [address]\tLoad device generated with mkimage"
c28c4d19	378	#if defined(CONFIG_FIT)
a790b5b2 SB	379	"\n"
	380	"\tFor loadmk operating on FIT format uImage address must include\n"
	381	"\tsubimage unit name in the form of addr:<subimg_uname>"
c28c4d19 MB	382	#endif
c28c4d19 MB	383	);