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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4a9cbbe8 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * FPGA support | |
10 | */ | |
11 | #include <common.h> | |
12 | #include <command.h> | |
8bde7f77 | 13 | #include <fpga.h> |
c3d2b4b4 | 14 | #include <malloc.h> |
4a9cbbe8 | 15 | |
4a9cbbe8 | 16 | /* Local functions */ |
fc598412 | 17 | static int fpga_get_op(char *opstr); |
4a9cbbe8 WD |
18 | |
19 | /* Local defines */ | |
20 | #define FPGA_NONE -1 | |
21 | #define FPGA_INFO 0 | |
22 | #define FPGA_LOAD 1 | |
30ce5ab0 | 23 | #define FPGA_LOADB 2 |
4a9cbbe8 | 24 | #define FPGA_DUMP 3 |
f0ff4692 | 25 | #define FPGA_LOADMK 4 |
4a9cbbe8 WD |
26 | |
27 | /* ------------------------------------------------------------------------- */ | |
28 | /* command form: | |
29 | * fpga <op> <device number> <data addr> <datasize> | |
30 | * where op is 'load', 'dump', or 'info' | |
31 | * If there is no device number field, the fpga environment variable is used. | |
32 | * If there is no data addr field, the fpgadata environment variable is used. | |
33 | * The info command requires no data address field. | |
34 | */ | |
fc598412 | 35 | int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
4a9cbbe8 | 36 | { |
d4ca31c4 WD |
37 | int op, dev = FPGA_INVALID_DEVICE; |
38 | size_t data_size = 0; | |
39 | void *fpga_data = NULL; | |
fc598412 MS |
40 | char *devstr = getenv("fpga"); |
41 | char *datastr = getenv("fpgadata"); | |
d4ca31c4 | 42 | int rc = FPGA_FAIL; |
a790b5b2 | 43 | int wrong_parms = 0; |
fc598412 | 44 | #if defined(CONFIG_FIT) |
c28c4d19 MB |
45 | const char *fit_uname = NULL; |
46 | ulong fit_addr; | |
47 | #endif | |
d4ca31c4 WD |
48 | |
49 | if (devstr) | |
fc598412 | 50 | dev = (int) simple_strtoul(devstr, NULL, 16); |
d4ca31c4 | 51 | if (datastr) |
fc598412 | 52 | fpga_data = (void *)simple_strtoul(datastr, NULL, 16); |
d4ca31c4 WD |
53 | |
54 | switch (argc) { | |
55 | case 5: /* fpga <op> <dev> <data> <datasize> */ | |
fc598412 | 56 | data_size = simple_strtoul(argv[4], NULL, 16); |
c28c4d19 | 57 | |
d4ca31c4 | 58 | case 4: /* fpga <op> <dev> <data> */ |
c28c4d19 | 59 | #if defined(CONFIG_FIT) |
fc598412 MS |
60 | if (fit_parse_subimage(argv[3], (ulong)fpga_data, |
61 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 62 | fpga_data = (void *)fit_addr; |
fc598412 MS |
63 | debug("* fpga: subimage '%s' from FIT image ", |
64 | fit_uname); | |
65 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
66 | } else |
67 | #endif | |
68 | { | |
fc598412 | 69 | fpga_data = (void *)simple_strtoul(argv[3], NULL, 16); |
06297db0 | 70 | debug("* fpga: cmdline image address = 0x%08lx\n", |
fc598412 | 71 | (ulong)fpga_data); |
c28c4d19 | 72 | } |
fc598412 | 73 | debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data); |
c28c4d19 | 74 | |
d4ca31c4 | 75 | case 3: /* fpga <op> <dev | data addr> */ |
fc598412 | 76 | dev = (int)simple_strtoul(argv[2], NULL, 16); |
06297db0 | 77 | debug("%s: device = %d\n", __func__, dev); |
d4ca31c4 | 78 | /* FIXME - this is a really weak test */ |
fc598412 MS |
79 | if ((argc == 3) && (dev > fpga_count())) { |
80 | /* must be buffer ptr */ | |
06297db0 | 81 | debug("%s: Assuming buffer pointer in arg 3\n", |
fc598412 | 82 | __func__); |
c28c4d19 MB |
83 | |
84 | #if defined(CONFIG_FIT) | |
fc598412 MS |
85 | if (fit_parse_subimage(argv[2], (ulong)fpga_data, |
86 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 87 | fpga_data = (void *)fit_addr; |
fc598412 MS |
88 | debug("* fpga: subimage '%s' from FIT image ", |
89 | fit_uname); | |
90 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
91 | } else |
92 | #endif | |
93 | { | |
fc598412 MS |
94 | fpga_data = (void *)dev; |
95 | debug("* fpga: cmdline image addr = 0x%08lx\n", | |
96 | (ulong)fpga_data); | |
c28c4d19 MB |
97 | } |
98 | ||
06297db0 | 99 | debug("%s: fpga_data = 0x%x\n", |
fc598412 | 100 | __func__, (uint)fpga_data); |
d4ca31c4 WD |
101 | dev = FPGA_INVALID_DEVICE; /* reset device num */ |
102 | } | |
c28c4d19 | 103 | |
d4ca31c4 | 104 | case 2: /* fpga <op> */ |
fc598412 | 105 | op = (int)fpga_get_op(argv[1]); |
d4ca31c4 | 106 | break; |
c28c4d19 | 107 | |
d4ca31c4 | 108 | default: |
fc598412 | 109 | debug("%s: Too many or too few args (%d)\n", __func__, argc); |
d4ca31c4 WD |
110 | op = FPGA_NONE; /* force usage display */ |
111 | break; | |
112 | } | |
113 | ||
a790b5b2 SB |
114 | if (dev == FPGA_INVALID_DEVICE) { |
115 | puts("FPGA device not specified\n"); | |
116 | op = FPGA_NONE; | |
117 | } | |
118 | ||
119 | switch (op) { | |
120 | case FPGA_NONE: | |
121 | case FPGA_INFO: | |
122 | break; | |
123 | case FPGA_LOAD: | |
124 | case FPGA_LOADB: | |
125 | case FPGA_DUMP: | |
126 | if (!fpga_data || !data_size) | |
127 | wrong_parms = 1; | |
128 | break; | |
129 | case FPGA_LOADMK: | |
130 | if (!fpga_data) | |
131 | wrong_parms = 1; | |
132 | break; | |
133 | } | |
134 | ||
135 | if (wrong_parms) { | |
136 | puts("Wrong parameters for FPGA request\n"); | |
137 | op = FPGA_NONE; | |
138 | } | |
139 | ||
d4ca31c4 WD |
140 | switch (op) { |
141 | case FPGA_NONE: | |
4c12eeb8 | 142 | return CMD_RET_USAGE; |
d4ca31c4 WD |
143 | |
144 | case FPGA_INFO: | |
fc598412 | 145 | rc = fpga_info(dev); |
d4ca31c4 WD |
146 | break; |
147 | ||
148 | case FPGA_LOAD: | |
fc598412 | 149 | rc = fpga_load(dev, fpga_data, data_size); |
d4ca31c4 WD |
150 | break; |
151 | ||
30ce5ab0 WD |
152 | case FPGA_LOADB: |
153 | rc = fpga_loadbitstream(dev, fpga_data, data_size); | |
154 | break; | |
155 | ||
f0ff4692 | 156 | case FPGA_LOADMK: |
fc598412 | 157 | switch (genimg_get_format(fpga_data)) { |
d5934ad7 MB |
158 | case IMAGE_FORMAT_LEGACY: |
159 | { | |
fc598412 MS |
160 | image_header_t *hdr = |
161 | (image_header_t *)fpga_data; | |
162 | ulong data; | |
d5934ad7 | 163 | |
fc598412 MS |
164 | data = (ulong)image_get_data(hdr); |
165 | data_size = image_get_data_size(hdr); | |
166 | rc = fpga_load(dev, (void *)data, data_size); | |
f0ff4692 | 167 | } |
d5934ad7 MB |
168 | break; |
169 | #if defined(CONFIG_FIT) | |
170 | case IMAGE_FORMAT_FIT: | |
c28c4d19 MB |
171 | { |
172 | const void *fit_hdr = (const void *)fpga_data; | |
173 | int noffset; | |
e6a857da | 174 | const void *fit_data; |
c28c4d19 MB |
175 | |
176 | if (fit_uname == NULL) { | |
fc598412 | 177 | puts("No FIT subimage unit name\n"); |
c28c4d19 MB |
178 | return 1; |
179 | } | |
180 | ||
fc598412 MS |
181 | if (!fit_check_format(fit_hdr)) { |
182 | puts("Bad FIT image format\n"); | |
c28c4d19 MB |
183 | return 1; |
184 | } | |
185 | ||
186 | /* get fpga component image node offset */ | |
fc598412 MS |
187 | noffset = fit_image_get_node(fit_hdr, |
188 | fit_uname); | |
c28c4d19 | 189 | if (noffset < 0) { |
fc598412 MS |
190 | printf("Can't find '%s' FIT subimage\n", |
191 | fit_uname); | |
c28c4d19 MB |
192 | return 1; |
193 | } | |
194 | ||
195 | /* verify integrity */ | |
b8da8366 | 196 | if (!fit_image_verify(fit_hdr, noffset)) { |
c28c4d19 MB |
197 | puts ("Bad Data Hash\n"); |
198 | return 1; | |
199 | } | |
200 | ||
201 | /* get fpga subimage data address and length */ | |
fc598412 MS |
202 | if (fit_image_get_data(fit_hdr, noffset, |
203 | &fit_data, &data_size)) { | |
204 | puts("Fpga subimage data not found\n"); | |
c28c4d19 MB |
205 | return 1; |
206 | } | |
207 | ||
fc598412 | 208 | rc = fpga_load(dev, fit_data, data_size); |
c28c4d19 | 209 | } |
d5934ad7 MB |
210 | break; |
211 | #endif | |
212 | default: | |
fc598412 | 213 | puts("** Unknown image type\n"); |
d5934ad7 MB |
214 | rc = FPGA_FAIL; |
215 | break; | |
f0ff4692 SR |
216 | } |
217 | break; | |
218 | ||
d4ca31c4 | 219 | case FPGA_DUMP: |
fc598412 | 220 | rc = fpga_dump(dev, fpga_data, data_size); |
d4ca31c4 WD |
221 | break; |
222 | ||
223 | default: | |
fc598412 | 224 | printf("Unknown operation\n"); |
4c12eeb8 | 225 | return CMD_RET_USAGE; |
d4ca31c4 | 226 | } |
fc598412 | 227 | return rc; |
4a9cbbe8 WD |
228 | } |
229 | ||
4a9cbbe8 WD |
230 | /* |
231 | * Map op to supported operations. We don't use a table since we | |
232 | * would just have to relocate it from flash anyway. | |
233 | */ | |
fc598412 | 234 | static int fpga_get_op(char *opstr) |
4a9cbbe8 WD |
235 | { |
236 | int op = FPGA_NONE; | |
237 | ||
fc598412 | 238 | if (!strcmp("info", opstr)) |
4a9cbbe8 | 239 | op = FPGA_INFO; |
fc598412 | 240 | else if (!strcmp("loadb", opstr)) |
30ce5ab0 | 241 | op = FPGA_LOADB; |
fc598412 | 242 | else if (!strcmp("load", opstr)) |
4a9cbbe8 | 243 | op = FPGA_LOAD; |
fc598412 | 244 | else if (!strcmp("loadmk", opstr)) |
f0ff4692 | 245 | op = FPGA_LOADMK; |
fc598412 | 246 | else if (!strcmp("dump", opstr)) |
4a9cbbe8 | 247 | op = FPGA_DUMP; |
4a9cbbe8 | 248 | |
fc598412 MS |
249 | if (op == FPGA_NONE) |
250 | printf("Unknown fpga operation \"%s\"\n", opstr); | |
251 | ||
4a9cbbe8 WD |
252 | return op; |
253 | } | |
254 | ||
fc598412 MS |
255 | U_BOOT_CMD(fpga, 6, 1, do_fpga, |
256 | "loadable FPGA image support", | |
257 | "[operation type] [device number] [image address] [image size]\n" | |
258 | "fpga operations:\n" | |
259 | " dump\t[dev]\t\t\tLoad device to memory buffer\n" | |
260 | " info\t[dev]\t\t\tlist known device information\n" | |
261 | " load\t[dev] [address] [size]\tLoad device from memory buffer\n" | |
262 | " loadb\t[dev] [address] [size]\t" | |
263 | "Load device from bitstream buffer (Xilinx only)\n" | |
264 | " loadmk [dev] [address]\tLoad device generated with mkimage" | |
c28c4d19 | 265 | #if defined(CONFIG_FIT) |
fc598412 MS |
266 | "\n" |
267 | "\tFor loadmk operating on FIT format uImage address must include\n" | |
268 | "\tsubimage unit name in the form of addr:<subimg_uname>" | |
c28c4d19 MB |
269 | #endif |
270 | ); |