[people/ms/u-boot.git] / common / cmd_fpga.c

/*
 * (C) Copyright 2000, 2001
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 *  FPGA support
 */
#include <common.h>
#include <command.h>
#if defined(CONFIG_CMD_NET)
#include <net.h>
#endif
#include <fpga.h>
#include <malloc.h>

#if 0
#define	FPGA_DEBUG
#endif

#ifdef	FPGA_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

/* Local functions */
static void fpga_usage (cmd_tbl_t * cmdtp);
static int fpga_get_op (char *opstr);

/* Local defines */
#define FPGA_NONE   -1
#define FPGA_INFO   0
#define FPGA_LOAD   1
#define FPGA_LOADB  2
#define FPGA_DUMP   3
#define FPGA_LOADMK 4

/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
#if defined(CONFIG_FPGA_XILINX)
	unsigned int length;
	unsigned int swapsize;
	char buffer[80];
	unsigned char *dataptr;
	unsigned int i;
	int rc;

	dataptr = (unsigned char *)fpgadata;

	/* skip the first bytes of the bitsteam, their meaning is unknown */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	dataptr+=length;

	/* get design name (identifier, length, string) */
	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	if (*dataptr++ != 0x61) {
		PRINTF ("%s: Design name identifier not recognized in bitstream\n",
			__FUNCTION__ );
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;

	printf("  design filename = \"%s\"\n", buffer);

	/* get part number (identifier, length, string) */
	if (*dataptr++ != 0x62) {
		printf("%s: Part number identifier not recognized in bitstream\n",
			__FUNCTION__ );
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  part number = \"%s\"\n", buffer);

	/* get date (identifier, length, string) */
	if (*dataptr++ != 0x63) {
		printf("%s: Date identifier not recognized in bitstream\n",
		       __FUNCTION__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  date = \"%s\"\n", buffer);

	/* get time (identifier, length, string) */
	if (*dataptr++ != 0x64) {
		printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
		return FPGA_FAIL;
	}

	length = (*dataptr << 8) + *(dataptr+1);
	dataptr+=2;
	for(i=0;i<length;i++)
		buffer[i] = *dataptr++;
	printf("  time = \"%s\"\n", buffer);

	/* get fpga data length (identifier, length) */
	if (*dataptr++ != 0x65) {
		printf("%s: Data length identifier not recognized in bitstream\n",
			__FUNCTION__);
		return FPGA_FAIL;
	}
	swapsize = ((unsigned int) *dataptr     <<24) +
	           ((unsigned int) *(dataptr+1) <<16) +
	           ((unsigned int) *(dataptr+2) <<8 ) +
	           ((unsigned int) *(dataptr+3)     ) ;
	dataptr+=4;
	printf("  bytes in bitstream = %d\n", swapsize);

	rc = fpga_load(dev, dataptr, swapsize);
	return rc;
#else
	printf("Bitstream support only for Xilinx devices\n");
	return FPGA_FAIL;
#endif
}

/* ------------------------------------------------------------------------- */
/* command form:
 *   fpga <op> <device number> <data addr> <datasize>
 * where op is 'load', 'dump', or 'info'
 * If there is no device number field, the fpga environment variable is used.
 * If there is no data addr field, the fpgadata environment variable is used.
 * The info command requires no data address field.
 */
int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	int op, dev = FPGA_INVALID_DEVICE;
	size_t data_size = 0;
	void *fpga_data = NULL;
	char *devstr = getenv ("fpga");
	char *datastr = getenv ("fpgadata");
	int rc = FPGA_FAIL;
#if defined (CONFIG_FIT)
	const char *fit_uname = NULL;
	ulong fit_addr;
#endif

	if (devstr)
		dev = (int) simple_strtoul (devstr, NULL, 16);
	if (datastr)
		fpga_data = (void *) simple_strtoul (datastr, NULL, 16);

	switch (argc) {
	case 5:		/* fpga <op> <dev> <data> <datasize> */
		data_size = simple_strtoul (argv[4], NULL, 16);

	case 4:		/* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
		if (fit_parse_subimage (argv[3], (ulong)fpga_data,
					&fit_addr, &fit_uname)) {
			fpga_data = (void *)fit_addr;
			debug ("*  fpga: subimage '%s' from FIT image at 0x%08lx\n",
					fit_uname, fit_addr);
		} else
#endif
		{
			fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
			debug ("*  fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
		}
		PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);

	case 3:		/* fpga <op> <dev | data addr> */
		dev = (int) simple_strtoul (argv[2], NULL, 16);
		PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
		/* FIXME - this is a really weak test */
		if ((argc == 3) && (dev > fpga_count ())) {	/* must be buffer ptr */
			PRINTF ("%s: Assuming buffer pointer in arg 3\n",
				__FUNCTION__);

#if defined(CONFIG_FIT)
			if (fit_parse_subimage (argv[2], (ulong)fpga_data,
						&fit_addr, &fit_uname)) {
				fpga_data = (void *)fit_addr;
				debug ("*  fpga: subimage '%s' from FIT image at 0x%08lx\n",
						fit_uname, fit_addr);
			} else
#endif
			{
				fpga_data = (void *) dev;
				debug ("*  fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
			}

			PRINTF ("%s: fpga_data = 0x%x\n",
				__FUNCTION__, (uint) fpga_data);
			dev = FPGA_INVALID_DEVICE;	/* reset device num */
		}

	case 2:		/* fpga <op> */
		op = (int) fpga_get_op (argv[1]);
		break;

	default:
		PRINTF ("%s: Too many or too few args (%d)\n",
			__FUNCTION__, argc);
		op = FPGA_NONE;	/* force usage display */
		break;
	}

	switch (op) {
	case FPGA_NONE:
		fpga_usage (cmdtp);
		break;

	case FPGA_INFO:
		rc = fpga_info (dev);
		break;

	case FPGA_LOAD:
		rc = fpga_load (dev, fpga_data, data_size);
		break;

	case FPGA_LOADB:
		rc = fpga_loadbitstream(dev, fpga_data, data_size);
		break;

	case FPGA_LOADMK:
		switch (genimg_get_format (fpga_data)) {
		case IMAGE_FORMAT_LEGACY:
			{
				image_header_t *hdr = (image_header_t *)fpga_data;
				ulong	data;

				data = (ulong)image_get_data (hdr);
				data_size = image_get_data_size (hdr);
				rc = fpga_load (dev, (void *)data, data_size);
			}
			break;
#if defined(CONFIG_FIT)
		case IMAGE_FORMAT_FIT:
			{
				const void *fit_hdr = (const void *)fpga_data;
				int noffset;
				void *fit_data;

				if (fit_uname == NULL) {
					puts ("No FIT subimage unit name\n");
					return 1;
				}

				if (!fit_check_format (fit_hdr)) {
					puts ("Bad FIT image format\n");
					return 1;
				}

				/* get fpga component image node offset */
				noffset = fit_image_get_node (fit_hdr, fit_uname);
				if (noffset < 0) {
					printf ("Can't find '%s' FIT subimage\n", fit_uname);
					return 1;
				}

				/* verify integrity */
				if (!fit_image_check_hashes (fit_hdr, noffset)) {
					puts ("Bad Data Hash\n");
					return 1;
				}

				/* get fpga subimage data address and length */
				if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
					puts ("Could not find fpga subimage data\n");
					return 1;
				}

				rc = fpga_load (dev, fit_data, data_size);
			}
			break;
#endif
		default:
			puts ("** Unknown image type\n");
			rc = FPGA_FAIL;
			break;
		}
		break;

	case FPGA_DUMP:
		rc = fpga_dump (dev, fpga_data, data_size);
		break;

	default:
		printf ("Unknown operation\n");
		fpga_usage (cmdtp);
		break;
	}
	return (rc);
}

static void fpga_usage (cmd_tbl_t * cmdtp)
{
	cmd_usage(cmdtp);
}

/*
 * Map op to supported operations.  We don't use a table since we
 * would just have to relocate it from flash anyway.
 */
static int fpga_get_op (char *opstr)
{
	int op = FPGA_NONE;

	if (!strcmp ("info", opstr)) {
		op = FPGA_INFO;
	} else if (!strcmp ("loadb", opstr)) {
		op = FPGA_LOADB;
	} else if (!strcmp ("load", opstr)) {
		op = FPGA_LOAD;
	} else if (!strcmp ("loadmk", opstr)) {
		op = FPGA_LOADMK;
	} else if (!strcmp ("dump", opstr)) {
		op = FPGA_DUMP;
	}

	if (op == FPGA_NONE) {
		printf ("Unknown fpga operation \"%s\"\n", opstr);
	}
	return op;
}

U_BOOT_CMD (fpga, 6, 1, do_fpga,
	    "fpga    - loadable FPGA image support\n",
	    "fpga [operation type] [device number] [image address] [image size]\n"
	    "fpga operations:\n"
	    "\tinfo\tlist known device information\n"
	    "\tload\tLoad device from memory buffer\n"
	    "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
	    "\tloadmk\tLoad device generated with mkimage\n"
	    "\tdump\tLoad device to memory buffer\n"
#if defined(CONFIG_FIT)
	    "\tFor loadmk operating on FIT format uImage address must include\n"
	    "\tsubimage unit name in the form of addr:<subimg_uname>\n"
#endif
);
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	/*
	26	* FPGA support
	27	*/
	28	#include <common.h>
	29	#include <command.h>
baa26db4	30	#if defined(CONFIG_CMD_NET)
4a9cbbe8 WD	31	#include <net.h>
4a9cbbe8 WD	32	#endif
8bde7f77	33	#include <fpga.h>
c3d2b4b4	34	#include <malloc.h>
4a9cbbe8 WD	35
	36	#if 0
	37	#define FPGA_DEBUG
	38	#endif
	39
	40	#ifdef FPGA_DEBUG
	41	#define PRINTF(fmt,args...) printf (fmt ,##args)
	42	#else
	43	#define PRINTF(fmt,args...)
	44	#endif
	45
4a9cbbe8	46	/* Local functions */
d4ca31c4 WD	47	static void fpga_usage (cmd_tbl_t * cmdtp);
d4ca31c4 WD	48	static int fpga_get_op (char *opstr);
4a9cbbe8 WD	49
	50	/* Local defines */
	51	#define FPGA_NONE -1
	52	#define FPGA_INFO 0
	53	#define FPGA_LOAD 1
30ce5ab0	54	#define FPGA_LOADB 2
4a9cbbe8	55	#define FPGA_DUMP 3
f0ff4692	56	#define FPGA_LOADMK 4
4a9cbbe8	57
30ce5ab0 WD	58	/* Convert bitstream data and load into the fpga */
	59	int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
	60	{
0133502e	61	#if defined(CONFIG_FPGA_XILINX)
8b019da6	62	unsigned int length;
8b019da6	63	unsigned int swapsize;
30ce5ab0	64	char buffer[80];
8b019da6	65	unsigned char *dataptr;
8b019da6	66	unsigned int i;
30ce5ab0 WD	67	int rc;
30ce5ab0 WD	68
77ddac94	69	dataptr = (unsigned char *)fpgadata;
30ce5ab0	70
8b019da6 WD	71	/* skip the first bytes of the bitsteam, their meaning is unknown */
	72	length = (dataptr << 8) + (dataptr+1);
	73	dataptr+=2;
	74	dataptr+=length;
30ce5ab0 WD	75
30ce5ab0 WD	76	/* get design name (identifier, length, string) */
8b019da6 WD	77	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	78	dataptr+=2;
30ce5ab0	79	if (*dataptr++ != 0x61) {
8b019da6 WD	80	PRINTF ("%s: Design name identifier not recognized in bitstream\n",
8b019da6 WD	81	__FUNCTION__ );
30ce5ab0 WD	82	return FPGA_FAIL;
	83	}
	84
a562e1bd	85	length = (dataptr << 8) + (dataptr+1);
30ce5ab0 WD	86	dataptr+=2;
30ce5ab0 WD	87	for(i=0;i<length;i++)
d0ff51ba	88	buffer[i] = *dataptr++;
a562e1bd	89
8b019da6	90	printf(" design filename = \"%s\"\n", buffer);
30ce5ab0 WD	91
	92	/* get part number (identifier, length, string) */
	93	if (*dataptr++ != 0x62) {
8b019da6 WD	94	printf("%s: Part number identifier not recognized in bitstream\n",
8b019da6 WD	95	__FUNCTION__ );
30ce5ab0 WD	96	return FPGA_FAIL;
30ce5ab0 WD	97	}
a562e1bd	98
8b019da6 WD	99	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	100	dataptr+=2;
a562e1bd	101	for(i=0;i<length;i++)
d0ff51ba	102	buffer[i] = *dataptr++;
8b019da6	103	printf(" part number = \"%s\"\n", buffer);
a562e1bd	104
30ce5ab0 WD	105	/* get date (identifier, length, string) */
30ce5ab0 WD	106	if (*dataptr++ != 0x63) {
8b019da6 WD	107	printf("%s: Date identifier not recognized in bitstream\n",
8b019da6 WD	108	__FUNCTION__);
30ce5ab0 WD	109	return FPGA_FAIL;
30ce5ab0 WD	110	}
a562e1bd	111
8b019da6 WD	112	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	113	dataptr+=2;
30ce5ab0	114	for(i=0;i<length;i++)
d0ff51ba	115	buffer[i] = *dataptr++;
8b019da6	116	printf(" date = \"%s\"\n", buffer);
30ce5ab0 WD	117
	118	/* get time (identifier, length, string) */
	119	if (*dataptr++ != 0x64) {
8b019da6	120	printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
30ce5ab0 WD	121	return FPGA_FAIL;
30ce5ab0 WD	122	}
a562e1bd	123
8b019da6 WD	124	length = (dataptr << 8) + (dataptr+1);
8b019da6 WD	125	dataptr+=2;
30ce5ab0	126	for(i=0;i<length;i++)
d0ff51ba	127	buffer[i] = *dataptr++;
8b019da6	128	printf(" time = \"%s\"\n", buffer);
a562e1bd	129
30ce5ab0 WD	130	/* get fpga data length (identifier, length) */
30ce5ab0 WD	131	if (*dataptr++ != 0x65) {
8b019da6 WD	132	printf("%s: Data length identifier not recognized in bitstream\n",
8b019da6 WD	133	__FUNCTION__);
30ce5ab0 WD	134	return FPGA_FAIL;
30ce5ab0 WD	135	}
8f79e4c2 WD	136	swapsize = ((unsigned int) *dataptr <<24) +
	137	((unsigned int) *(dataptr+1) <<16) +
	138	((unsigned int) *(dataptr+2) <<8 ) +
8b019da6	139	((unsigned int) *(dataptr+3) ) ;
30ce5ab0	140	dataptr+=4;
8b019da6	141	printf(" bytes in bitstream = %d\n", swapsize);
a562e1bd	142
c26acc1a	143	rc = fpga_load(dev, dataptr, swapsize);
30ce5ab0 WD	144	return rc;
30ce5ab0 WD	145	#else
8b019da6	146	printf("Bitstream support only for Xilinx devices\n");
30ce5ab0 WD	147	return FPGA_FAIL;
	148	#endif
	149	}
	150
4a9cbbe8 WD	151	/* ------------------------------------------------------------------------- */
	152	/* command form:
	153	* fpga <op> <device number> <data addr> <datasize>
	154	* where op is 'load', 'dump', or 'info'
	155	* If there is no device number field, the fpga environment variable is used.
	156	* If there is no data addr field, the fpgadata environment variable is used.
	157	* The info command requires no data address field.
	158	*/
d4ca31c4	159	int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
4a9cbbe8	160	{
d4ca31c4 WD	161	int op, dev = FPGA_INVALID_DEVICE;
	162	size_t data_size = 0;
	163	void *fpga_data = NULL;
	164	char *devstr = getenv ("fpga");
	165	char *datastr = getenv ("fpgadata");
	166	int rc = FPGA_FAIL;
c28c4d19 MB	167	#if defined (CONFIG_FIT)
	168	const char *fit_uname = NULL;
	169	ulong fit_addr;
	170	#endif
d4ca31c4 WD	171
	172	if (devstr)
	173	dev = (int) simple_strtoul (devstr, NULL, 16);
	174	if (datastr)
	175	fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
	176
	177	switch (argc) {
	178	case 5: /* fpga <op> <dev> <data> <datasize> */
	179	data_size = simple_strtoul (argv[4], NULL, 16);
c28c4d19	180
d4ca31c4	181	case 4: /* fpga <op> <dev> <data> */
c28c4d19 MB	182	#if defined(CONFIG_FIT)
	183	if (fit_parse_subimage (argv[3], (ulong)fpga_data,
	184	&fit_addr, &fit_uname)) {
	185	fpga_data = (void *)fit_addr;
	186	debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
	187	fit_uname, fit_addr);
	188	} else
	189	#endif
	190	{
	191	fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
	192	debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
	193	}
8b019da6	194	PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
c28c4d19	195
d4ca31c4 WD	196	case 3: /* fpga <op> <dev \| data addr> */
d4ca31c4 WD	197	dev = (int) simple_strtoul (argv[2], NULL, 16);
8b019da6	198	PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
d4ca31c4 WD	199	/* FIXME - this is a really weak test */
d4ca31c4 WD	200	if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
8f79e4c2	201	PRINTF ("%s: Assuming buffer pointer in arg 3\n",
8b019da6	202	__FUNCTION__);
c28c4d19 MB	203
	204	#if defined(CONFIG_FIT)
	205	if (fit_parse_subimage (argv[2], (ulong)fpga_data,
	206	&fit_addr, &fit_uname)) {
	207	fpga_data = (void *)fit_addr;
	208	debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
	209	fit_uname, fit_addr);
	210	} else
	211	#endif
	212	{
	213	fpga_data = (void *) dev;
	214	debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
	215	}
	216
8b019da6 WD	217	PRINTF ("%s: fpga_data = 0x%x\n",
8b019da6 WD	218	__FUNCTION__, (uint) fpga_data);
d4ca31c4 WD	219	dev = FPGA_INVALID_DEVICE; /* reset device num */
d4ca31c4 WD	220	}
c28c4d19	221
d4ca31c4 WD	222	case 2: /* fpga <op> */
	223	op = (int) fpga_get_op (argv[1]);
	224	break;
c28c4d19	225
d4ca31c4	226	default:
8b019da6 WD	227	PRINTF ("%s: Too many or too few args (%d)\n",
8b019da6 WD	228	__FUNCTION__, argc);
d4ca31c4 WD	229	op = FPGA_NONE; /* force usage display */
	230	break;
	231	}
	232
	233	switch (op) {
	234	case FPGA_NONE:
	235	fpga_usage (cmdtp);
	236	break;
	237
	238	case FPGA_INFO:
	239	rc = fpga_info (dev);
	240	break;
	241
	242	case FPGA_LOAD:
	243	rc = fpga_load (dev, fpga_data, data_size);
	244	break;
	245
30ce5ab0 WD	246	case FPGA_LOADB:
	247	rc = fpga_loadbitstream(dev, fpga_data, data_size);
	248	break;
	249
f0ff4692	250	case FPGA_LOADMK:
9a4daad0	251	switch (genimg_get_format (fpga_data)) {
d5934ad7 MB	252	case IMAGE_FORMAT_LEGACY:
	253	{
	254	image_header_t hdr = (image_header_t )fpga_data;
	255	ulong data;
	256
d5934ad7 MB	257	data = (ulong)image_get_data (hdr);
	258	data_size = image_get_data_size (hdr);
	259	rc = fpga_load (dev, (void *)data, data_size);
f0ff4692	260	}
d5934ad7 MB	261	break;
	262	#if defined(CONFIG_FIT)
	263	case IMAGE_FORMAT_FIT:
c28c4d19 MB	264	{
	265	const void fit_hdr = (const void )fpga_data;
	266	int noffset;
	267	void *fit_data;
	268
	269	if (fit_uname == NULL) {
	270	puts ("No FIT subimage unit name\n");
	271	return 1;
	272	}
	273
	274	if (!fit_check_format (fit_hdr)) {
	275	puts ("Bad FIT image format\n");
	276	return 1;
	277	}
	278
	279	/* get fpga component image node offset */
	280	noffset = fit_image_get_node (fit_hdr, fit_uname);
	281	if (noffset < 0) {
	282	printf ("Can't find '%s' FIT subimage\n", fit_uname);
	283	return 1;
	284	}
	285
	286	/* verify integrity */
	287	if (!fit_image_check_hashes (fit_hdr, noffset)) {
	288	puts ("Bad Data Hash\n");
	289	return 1;
	290	}
	291
	292	/* get fpga subimage data address and length */
	293	if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
	294	puts ("Could not find fpga subimage data\n");
	295	return 1;
	296	}
	297
	298	rc = fpga_load (dev, fit_data, data_size);
	299	}
d5934ad7 MB	300	break;
	301	#endif
	302	default:
	303	puts ("** Unknown image type\n");
	304	rc = FPGA_FAIL;
	305	break;
f0ff4692 SR	306	}
	307	break;
	308
d4ca31c4 WD	309	case FPGA_DUMP:
	310	rc = fpga_dump (dev, fpga_data, data_size);
	311	break;
	312
	313	default:
8b019da6	314	printf ("Unknown operation\n");
d4ca31c4 WD	315	fpga_usage (cmdtp);
	316	break;
	317	}
	318	return (rc);
4a9cbbe8 WD	319	}
4a9cbbe8 WD	320
d4ca31c4	321	static void fpga_usage (cmd_tbl_t * cmdtp)
4a9cbbe8	322	{
62c3ae7c	323	cmd_usage(cmdtp);
4a9cbbe8 WD	324	}
	325
	326	/*
	327	* Map op to supported operations. We don't use a table since we
	328	* would just have to relocate it from flash anyway.
	329	*/
d4ca31c4	330	static int fpga_get_op (char *opstr)
4a9cbbe8 WD	331	{
	332	int op = FPGA_NONE;
	333
	334	if (!strcmp ("info", opstr)) {
	335	op = FPGA_INFO;
30ce5ab0 WD	336	} else if (!strcmp ("loadb", opstr)) {
30ce5ab0 WD	337	op = FPGA_LOADB;
d4ca31c4	338	} else if (!strcmp ("load", opstr)) {
4a9cbbe8	339	op = FPGA_LOAD;
f0ff4692 SR	340	} else if (!strcmp ("loadmk", opstr)) {
f0ff4692 SR	341	op = FPGA_LOADMK;
d4ca31c4	342	} else if (!strcmp ("dump", opstr)) {
4a9cbbe8 WD	343	op = FPGA_DUMP;
	344	}
	345
d4ca31c4	346	if (op == FPGA_NONE) {
4a9cbbe8 WD	347	printf ("Unknown fpga operation \"%s\"\n", opstr);
	348	}
	349	return op;
	350	}
	351
d4ca31c4	352	U_BOOT_CMD (fpga, 6, 1, do_fpga,
dd875c76	353	"fpga - loadable FPGA image support\n",
d4ca31c4 WD	354	"fpga [operation type] [device number] [image address] [image size]\n"
d4ca31c4 WD	355	"fpga operations:\n"
8b019da6 WD	356	"\tinfo\tlist known device information\n"
	357	"\tload\tLoad device from memory buffer\n"
	358	"\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
f0ff4692	359	"\tloadmk\tLoad device generated with mkimage\n"
c28c4d19 MB	360	"\tdump\tLoad device to memory buffer\n"
	361	#if defined(CONFIG_FIT)
	362	"\tFor loadmk operating on FIT format uImage address must include\n"
	363	"\tsubimage unit name in the form of addr:<subimg_uname>\n"
	364	#endif
	365	);