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81a8824f 1/*
3f4978c7
HS
2 * (C) Copyright 2009
3 * Sergey Kubushyn, himself, ksi@koi8.net
4 *
5 * Changes for unified multibus/multiadapter I2C support.
6 *
81a8824f
WD
7 * (C) Copyright 2001
8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
81a8824f
WD
11 */
12
13/*
14 * I2C Functions similar to the standard memory functions.
15 *
16 * There are several parameters in many of the commands that bear further
17 * explanations:
18 *
81a8824f
WD
19 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
20 * Each I2C chip on the bus has a unique address. On the I2C data bus,
21 * the address is the upper seven bits and the LSB is the "read/write"
22 * bit. Note that the {i2c_chip} address specified on the command
23 * line is not shifted up: e.g. a typical EEPROM memory chip may have
24 * an I2C address of 0x50, but the data put on the bus will be 0xA0
25 * for write and 0xA1 for read. This "non shifted" address notation
26 * matches at least half of the data sheets :-/.
27 *
28 * {addr} is the address (or offset) within the chip. Small memory
29 * chips have 8 bit addresses. Large memory chips have 16 bit
30 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
31 * Many non-memory chips have multiple registers and {addr} is used
32 * as the register index. Some non-memory chips have only one register
33 * and therefore don't need any {addr} parameter.
34 *
35 * The default {addr} parameter is one byte (.1) which works well for
36 * memories and registers with 8 bits of address space.
37 *
38 * You can specify the length of the {addr} field with the optional .0,
39 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
40 * manipulating a single register device which doesn't use an address
41 * field, use "0.0" for the address and the ".0" length field will
42 * suppress the address in the I2C data stream. This also works for
43 * successive reads using the I2C auto-incrementing memory pointer.
44 *
45 * If you are manipulating a large memory with 2-byte addresses, use
46 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
47 *
48 * Then there are the unfortunate memory chips that spill the most
49 * significant 1, 2, or 3 bits of address into the chip address byte.
50 * This effectively makes one chip (logically) look like 2, 4, or
51 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 52 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
53 * {addr} field (since .1 is the default, it doesn't actually have to
54 * be specified). Examples: given a memory chip at I2C chip address
55 * 0x50, the following would happen...
0f89c54b 56 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 57 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 58 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 59 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 60 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
61 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
62 * This is awfully ugly. It would be nice if someone would think up
63 * a better way of handling this.
64 *
65 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
66 */
67
68#include <common.h>
0098e179 69#include <bootretry.h>
18d66533 70#include <cli.h>
81a8824f 71#include <command.h>
63656b76 72#include <dm.h>
735987c5 73#include <edid.h>
67b23a32 74#include <environment.h>
63656b76 75#include <errno.h>
81a8824f 76#include <i2c.h>
67b23a32 77#include <malloc.h>
81a8824f 78#include <asm/byteorder.h>
2515d843 79#include <linux/compiler.h>
81a8824f 80
3f4978c7
HS
81DECLARE_GLOBAL_DATA_PTR;
82
81a8824f
WD
83/* Display values from last command.
84 * Memory modify remembered values are different from display memory.
85 */
5468461d 86static uint i2c_dp_last_chip;
81a8824f
WD
87static uint i2c_dp_last_addr;
88static uint i2c_dp_last_alen;
89static uint i2c_dp_last_length = 0x10;
90
5468461d 91static uint i2c_mm_last_chip;
81a8824f
WD
92static uint i2c_mm_last_addr;
93static uint i2c_mm_last_alen;
94
bb99ad6d
BW
95/* If only one I2C bus is present, the list of devices to ignore when
96 * the probe command is issued is represented by a 1D array of addresses.
97 * When multiple buses are present, the list is an array of bus-address
98 * pairs. The following macros take care of this */
99
6d0f6bcf 100#if defined(CONFIG_SYS_I2C_NOPROBES)
9a2accb4 101#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
bb99ad6d
BW
102static struct
103{
104 uchar bus;
105 uchar addr;
6d0f6bcf 106} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
107#define GET_BUS_NUM i2c_get_bus_num()
108#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
109#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
110#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
111#else /* single bus */
6d0f6bcf 112static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
113#define GET_BUS_NUM 0
114#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
115#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
116#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
3f4978c7 117#endif /* defined(CONFIG_SYS_I2C) */
67b23a32
HS
118#endif
119
a266fe95
FM
120#define DISP_LINE_LEN 16
121
63656b76
SG
122/*
123 * Default for driver model is to use the chip's existing address length.
124 * For legacy code, this is not stored, so we need to use a suitable
125 * default.
126 */
127#ifdef CONFIG_DM_I2C
128#define DEFAULT_ADDR_LEN (-1)
129#else
130#define DEFAULT_ADDR_LEN 1
131#endif
132
133#ifdef CONFIG_DM_I2C
134static struct udevice *i2c_cur_bus;
135
f9a4c2da 136static int cmd_i2c_set_bus_num(unsigned int busnum)
63656b76
SG
137{
138 struct udevice *bus;
139 int ret;
140
141 ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
142 if (ret) {
143 debug("%s: No bus %d\n", __func__, busnum);
144 return ret;
145 }
146 i2c_cur_bus = bus;
147
148 return 0;
149}
150
151static int i2c_get_cur_bus(struct udevice **busp)
152{
153 if (!i2c_cur_bus) {
154 puts("No I2C bus selected\n");
155 return -ENODEV;
156 }
157 *busp = i2c_cur_bus;
158
159 return 0;
160}
161
162static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
163{
164 struct udevice *bus;
165 int ret;
166
167 ret = i2c_get_cur_bus(&bus);
168 if (ret)
169 return ret;
170
25ab4b03 171 return i2c_get_chip(bus, chip_addr, 1, devp);
63656b76
SG
172}
173
174#endif
175
06afa388
MV
176/**
177 * i2c_init_board() - Board-specific I2C bus init
178 *
179 * This function is the default no-op implementation of I2C bus
180 * initialization. This function can be overriden by board-specific
181 * implementation if needed.
182 */
2515d843
MV
183__weak
184void i2c_init_board(void)
c649dda5 185{
c649dda5 186}
c649dda5 187
655b34a7 188/* TODO: Implement architecture-specific get/set functions */
06afa388
MV
189
190/**
191 * i2c_get_bus_speed() - Return I2C bus speed
192 *
193 * This function is the default implementation of function for retrieveing
194 * the current I2C bus speed in Hz.
195 *
196 * A driver implementing runtime switching of I2C bus speed must override
197 * this function to report the speed correctly. Simple or legacy drivers
198 * can use this fallback.
199 *
200 * Returns I2C bus speed in Hz.
201 */
63656b76 202#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
3f4978c7
HS
203/*
204 * TODO: Implement architecture-specific get/set functions
205 * Should go away, if we switched completely to new multibus support
206 */
2515d843
MV
207__weak
208unsigned int i2c_get_bus_speed(void)
655b34a7
PT
209{
210 return CONFIG_SYS_I2C_SPEED;
211}
655b34a7 212
06afa388
MV
213/**
214 * i2c_set_bus_speed() - Configure I2C bus speed
215 * @speed: Newly set speed of the I2C bus in Hz
216 *
217 * This function is the default implementation of function for setting
218 * the I2C bus speed in Hz.
219 *
220 * A driver implementing runtime switching of I2C bus speed must override
221 * this function to report the speed correctly. Simple or legacy drivers
222 * can use this fallback.
223 *
224 * Returns zero on success, negative value on error.
225 */
2515d843
MV
226__weak
227int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
228{
229 if (speed != CONFIG_SYS_I2C_SPEED)
230 return -1;
231
232 return 0;
233}
3f4978c7 234#endif
655b34a7 235
06afa388
MV
236/**
237 * get_alen() - Small parser helper function to get address length
238 *
239 * Returns the address length.
2c0dc990 240 */
63656b76 241static uint get_alen(char *arg, int default_len)
2c0dc990
FM
242{
243 int j;
244 int alen;
245
63656b76 246 alen = default_len;
2c0dc990
FM
247 for (j = 0; j < 8; j++) {
248 if (arg[j] == '.') {
249 alen = arg[j+1] - '0';
2c0dc990
FM
250 break;
251 } else if (arg[j] == '\0')
252 break;
253 }
254 return alen;
255}
256
c1a6f371
SG
257enum i2c_err_op {
258 I2C_ERR_READ,
259 I2C_ERR_WRITE,
260};
261
262static int i2c_report_err(int ret, enum i2c_err_op op)
263{
264 printf("Error %s the chip: %d\n",
265 op == I2C_ERR_READ ? "reading" : "writing", ret);
266
267 return CMD_RET_FAILURE;
268}
269
06afa388
MV
270/**
271 * do_i2c_read() - Handle the "i2c read" command-line command
272 * @cmdtp: Command data struct pointer
273 * @flag: Command flag
274 * @argc: Command-line argument count
275 * @argv: Array of command-line arguments
276 *
277 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
278 * on error.
279 *
652e5354
FM
280 * Syntax:
281 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
282 */
54841ab5 283static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
652e5354 284{
5468461d 285 uint chip;
63656b76
SG
286 uint devaddr, length;
287 int alen;
652e5354 288 u_char *memaddr;
63656b76
SG
289 int ret;
290#ifdef CONFIG_DM_I2C
291 struct udevice *dev;
292#endif
652e5354 293
47e26b1b 294 if (argc != 5)
4c12eeb8 295 return CMD_RET_USAGE;
652e5354
FM
296
297 /*
298 * I2C chip address
299 */
300 chip = simple_strtoul(argv[1], NULL, 16);
301
302 /*
303 * I2C data address within the chip. This can be 1 or
304 * 2 bytes long. Some day it might be 3 bytes long :-).
305 */
306 devaddr = simple_strtoul(argv[2], NULL, 16);
63656b76 307 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 308 if (alen > 3)
4c12eeb8 309 return CMD_RET_USAGE;
652e5354
FM
310
311 /*
312 * Length is the number of objects, not number of bytes.
313 */
314 length = simple_strtoul(argv[3], NULL, 16);
315
316 /*
317 * memaddr is the address where to store things in memory
318 */
319 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
320
63656b76
SG
321#ifdef CONFIG_DM_I2C
322 ret = i2c_get_cur_bus_chip(chip, &dev);
323 if (!ret && alen != -1)
324 ret = i2c_set_chip_offset_len(dev, alen);
325 if (!ret)
f9a4c2da 326 ret = dm_i2c_read(dev, devaddr, memaddr, length);
63656b76
SG
327#else
328 ret = i2c_read(chip, devaddr, alen, memaddr, length);
329#endif
330 if (ret)
331 return i2c_report_err(ret, I2C_ERR_READ);
332
652e5354
FM
333 return 0;
334}
335
ff5d2dce
YS
336static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
337{
5468461d 338 uint chip;
63656b76
SG
339 uint devaddr, length;
340 int alen;
ff5d2dce 341 u_char *memaddr;
63656b76
SG
342 int ret;
343#ifdef CONFIG_DM_I2C
344 struct udevice *dev;
ed16f146 345 struct dm_i2c_chip *i2c_chip;
63656b76 346#endif
ff5d2dce 347
ed16f146 348 if ((argc < 5) || (argc > 6))
ff5d2dce
YS
349 return cmd_usage(cmdtp);
350
351 /*
352 * memaddr is the address where to store things in memory
353 */
354 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
355
356 /*
357 * I2C chip address
358 */
359 chip = simple_strtoul(argv[2], NULL, 16);
360
361 /*
362 * I2C data address within the chip. This can be 1 or
363 * 2 bytes long. Some day it might be 3 bytes long :-).
364 */
365 devaddr = simple_strtoul(argv[3], NULL, 16);
63656b76 366 alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
ff5d2dce
YS
367 if (alen > 3)
368 return cmd_usage(cmdtp);
369
370 /*
ed16f146 371 * Length is the number of bytes.
ff5d2dce
YS
372 */
373 length = simple_strtoul(argv[4], NULL, 16);
374
63656b76
SG
375#ifdef CONFIG_DM_I2C
376 ret = i2c_get_cur_bus_chip(chip, &dev);
377 if (!ret && alen != -1)
378 ret = i2c_set_chip_offset_len(dev, alen);
379 if (ret)
380 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
381 i2c_chip = dev_get_parent_platdata(dev);
382 if (!i2c_chip)
383 return i2c_report_err(ret, I2C_ERR_WRITE);
63656b76
SG
384#endif
385
ed16f146
LP
386 if (argc == 6 && !strcmp(argv[5], "-s")) {
387 /*
388 * Write all bytes in a single I2C transaction. If the target
389 * device is an EEPROM, it is your responsibility to not cross
390 * a page boundary. No write delay upon completion, take this
391 * into account if linking commands.
392 */
63656b76 393#ifdef CONFIG_DM_I2C
ed16f146
LP
394 i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
395 ret = dm_i2c_write(dev, devaddr, memaddr, length);
63656b76 396#else
ed16f146 397 ret = i2c_write(chip, devaddr, alen, memaddr, length);
63656b76
SG
398#endif
399 if (ret)
400 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
401 } else {
402 /*
403 * Repeated addressing - perform <length> separate
404 * write transactions of one byte each
405 */
406 while (length-- > 0) {
407#ifdef CONFIG_DM_I2C
408 i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
409 ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
410#else
411 ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
412#endif
413 if (ret)
414 return i2c_report_err(ret, I2C_ERR_WRITE);
ff5d2dce
YS
415/*
416 * No write delay with FRAM devices.
417 */
418#if !defined(CONFIG_SYS_I2C_FRAM)
ed16f146 419 udelay(11000);
ff5d2dce 420#endif
ed16f146 421 }
ff5d2dce
YS
422 }
423 return 0;
424}
425
63656b76
SG
426#ifdef CONFIG_DM_I2C
427static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
428 char *const argv[])
429{
430 struct udevice *dev;
431 uint flags;
432 int chip;
433 int ret;
434
435 if (argc < 2)
436 return CMD_RET_USAGE;
437
438 chip = simple_strtoul(argv[1], NULL, 16);
439 ret = i2c_get_cur_bus_chip(chip, &dev);
440 if (ret)
441 return i2c_report_err(ret, I2C_ERR_READ);
442
443 if (argc > 2) {
444 flags = simple_strtoul(argv[2], NULL, 16);
445 ret = i2c_set_chip_flags(dev, flags);
446 } else {
447 ret = i2c_get_chip_flags(dev, &flags);
448 if (!ret)
449 printf("%x\n", flags);
450 }
451 if (ret)
452 return i2c_report_err(ret, I2C_ERR_READ);
453
454 return 0;
455}
456#endif
457
06afa388
MV
458/**
459 * do_i2c_md() - Handle the "i2c md" command-line command
460 * @cmdtp: Command data struct pointer
461 * @flag: Command flag
462 * @argc: Command-line argument count
463 * @argv: Array of command-line arguments
464 *
465 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
466 * on error.
467 *
4a8cf338
FM
468 * Syntax:
469 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
470 */
54841ab5 471static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 472{
5468461d 473 uint chip;
63656b76
SG
474 uint addr, length;
475 int alen;
81a8824f 476 int j, nbytes, linebytes;
63656b76
SG
477 int ret;
478#ifdef CONFIG_DM_I2C
479 struct udevice *dev;
480#endif
81a8824f
WD
481
482 /* We use the last specified parameters, unless new ones are
483 * entered.
484 */
485 chip = i2c_dp_last_chip;
486 addr = i2c_dp_last_addr;
487 alen = i2c_dp_last_alen;
488 length = i2c_dp_last_length;
489
47e26b1b 490 if (argc < 3)
4c12eeb8 491 return CMD_RET_USAGE;
81a8824f
WD
492
493 if ((flag & CMD_FLAG_REPEAT) == 0) {
494 /*
495 * New command specified.
496 */
81a8824f
WD
497
498 /*
499 * I2C chip address
500 */
501 chip = simple_strtoul(argv[1], NULL, 16);
502
503 /*
504 * I2C data address within the chip. This can be 1 or
505 * 2 bytes long. Some day it might be 3 bytes long :-).
506 */
507 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 508 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 509 if (alen > 3)
4c12eeb8 510 return CMD_RET_USAGE;
81a8824f
WD
511
512 /*
513 * If another parameter, it is the length to display.
514 * Length is the number of objects, not number of bytes.
515 */
516 if (argc > 3)
517 length = simple_strtoul(argv[3], NULL, 16);
518 }
519
63656b76
SG
520#ifdef CONFIG_DM_I2C
521 ret = i2c_get_cur_bus_chip(chip, &dev);
522 if (!ret && alen != -1)
523 ret = i2c_set_chip_offset_len(dev, alen);
524 if (ret)
525 return i2c_report_err(ret, I2C_ERR_READ);
526#endif
527
81a8824f
WD
528 /*
529 * Print the lines.
530 *
531 * We buffer all read data, so we can make sure data is read only
532 * once.
533 */
534 nbytes = length;
535 do {
536 unsigned char linebuf[DISP_LINE_LEN];
537 unsigned char *cp;
538
539 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
540
63656b76 541#ifdef CONFIG_DM_I2C
f9a4c2da 542 ret = dm_i2c_read(dev, addr, linebuf, linebytes);
63656b76
SG
543#else
544 ret = i2c_read(chip, addr, alen, linebuf, linebytes);
545#endif
546 if (ret)
9e533cb0 547 return i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 548 else {
81a8824f
WD
549 printf("%04x:", addr);
550 cp = linebuf;
551 for (j=0; j<linebytes; j++) {
552 printf(" %02x", *cp++);
553 addr++;
554 }
4b9206ed 555 puts (" ");
81a8824f
WD
556 cp = linebuf;
557 for (j=0; j<linebytes; j++) {
558 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 559 puts (".");
81a8824f
WD
560 else
561 printf("%c", *cp);
562 cp++;
563 }
4b9206ed 564 putc ('\n');
81a8824f
WD
565 }
566 nbytes -= linebytes;
567 } while (nbytes > 0);
568
569 i2c_dp_last_chip = chip;
570 i2c_dp_last_addr = addr;
571 i2c_dp_last_alen = alen;
572 i2c_dp_last_length = length;
573
574 return 0;
575}
576
06afa388
MV
577/**
578 * do_i2c_mw() - Handle the "i2c mw" command-line command
579 * @cmdtp: Command data struct pointer
580 * @flag: Command flag
581 * @argc: Command-line argument count
582 * @argv: Array of command-line arguments
583 *
584 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
585 * on error.
81a8824f
WD
586 *
587 * Syntax:
0f89c54b 588 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 589 */
54841ab5 590static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 591{
5468461d 592 uint chip;
81a8824f 593 ulong addr;
63656b76 594 int alen;
81a8824f
WD
595 uchar byte;
596 int count;
63656b76
SG
597 int ret;
598#ifdef CONFIG_DM_I2C
599 struct udevice *dev;
600#endif
81a8824f 601
47e26b1b 602 if ((argc < 4) || (argc > 5))
4c12eeb8 603 return CMD_RET_USAGE;
81a8824f
WD
604
605 /*
53677ef1
WD
606 * Chip is always specified.
607 */
81a8824f
WD
608 chip = simple_strtoul(argv[1], NULL, 16);
609
610 /*
611 * Address is always specified.
612 */
613 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 614 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 615 if (alen > 3)
4c12eeb8 616 return CMD_RET_USAGE;
81a8824f 617
63656b76
SG
618#ifdef CONFIG_DM_I2C
619 ret = i2c_get_cur_bus_chip(chip, &dev);
620 if (!ret && alen != -1)
621 ret = i2c_set_chip_offset_len(dev, alen);
622 if (ret)
623 return i2c_report_err(ret, I2C_ERR_WRITE);
624#endif
81a8824f
WD
625 /*
626 * Value to write is always specified.
627 */
628 byte = simple_strtoul(argv[3], NULL, 16);
629
630 /*
631 * Optional count
632 */
e857a5bd 633 if (argc == 5)
81a8824f 634 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 635 else
81a8824f 636 count = 1;
81a8824f
WD
637
638 while (count-- > 0) {
63656b76 639#ifdef CONFIG_DM_I2C
f9a4c2da 640 ret = dm_i2c_write(dev, addr++, &byte, 1);
63656b76
SG
641#else
642 ret = i2c_write(chip, addr++, alen, &byte, 1);
643#endif
644 if (ret)
9e533cb0 645 return i2c_report_err(ret, I2C_ERR_WRITE);
81a8824f
WD
646 /*
647 * Wait for the write to complete. The write can take
648 * up to 10mSec (we allow a little more time).
81a8824f 649 */
d4f5c728 650/*
651 * No write delay with FRAM devices.
652 */
6d0f6bcf 653#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 654 udelay(11000);
d4f5c728 655#endif
81a8824f
WD
656 }
657
06afa388 658 return 0;
81a8824f
WD
659}
660
06afa388
MV
661/**
662 * do_i2c_crc() - Handle the "i2c crc32" command-line command
663 * @cmdtp: Command data struct pointer
664 * @flag: Command flag
665 * @argc: Command-line argument count
666 * @argv: Array of command-line arguments
667 *
668 * Calculate a CRC on memory
669 *
670 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
671 * on error.
81a8824f
WD
672 *
673 * Syntax:
0f89c54b 674 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 675 */
54841ab5 676static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 677{
5468461d 678 uint chip;
81a8824f 679 ulong addr;
63656b76 680 int alen;
81a8824f
WD
681 int count;
682 uchar byte;
683 ulong crc;
684 ulong err;
63656b76
SG
685 int ret = 0;
686#ifdef CONFIG_DM_I2C
687 struct udevice *dev;
688#endif
81a8824f 689
47e26b1b 690 if (argc < 4)
4c12eeb8 691 return CMD_RET_USAGE;
81a8824f
WD
692
693 /*
53677ef1
WD
694 * Chip is always specified.
695 */
81a8824f
WD
696 chip = simple_strtoul(argv[1], NULL, 16);
697
698 /*
699 * Address is always specified.
700 */
701 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 702 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 703 if (alen > 3)
4c12eeb8 704 return CMD_RET_USAGE;
81a8824f 705
63656b76
SG
706#ifdef CONFIG_DM_I2C
707 ret = i2c_get_cur_bus_chip(chip, &dev);
708 if (!ret && alen != -1)
709 ret = i2c_set_chip_offset_len(dev, alen);
710 if (ret)
711 return i2c_report_err(ret, I2C_ERR_READ);
712#endif
81a8824f
WD
713 /*
714 * Count is always specified
715 */
716 count = simple_strtoul(argv[3], NULL, 16);
717
718 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
719 /*
720 * CRC a byte at a time. This is going to be slooow, but hey, the
721 * memories are small and slow too so hopefully nobody notices.
722 */
723 crc = 0;
724 err = 0;
e857a5bd 725 while (count-- > 0) {
63656b76 726#ifdef CONFIG_DM_I2C
f9a4c2da 727 ret = dm_i2c_read(dev, addr, &byte, 1);
63656b76
SG
728#else
729 ret = i2c_read(chip, addr, alen, &byte, 1);
730#endif
731 if (ret)
81a8824f 732 err++;
81a8824f
WD
733 crc = crc32 (crc, &byte, 1);
734 addr++;
735 }
e857a5bd 736 if (err > 0)
63656b76 737 i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 738 else
81a8824f 739 printf ("%08lx\n", crc);
81a8824f
WD
740
741 return 0;
742}
743
06afa388
MV
744/**
745 * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
746 * @cmdtp: Command data struct pointer
747 * @flag: Command flag
748 * @argc: Command-line argument count
749 * @argv: Array of command-line arguments
750 *
751 * Modify memory.
752 *
753 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
754 * on error.
81a8824f
WD
755 *
756 * Syntax:
0f89c54b
PT
757 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
758 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f 759 */
81a8824f 760static int
54841ab5 761mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
81a8824f 762{
5468461d 763 uint chip;
81a8824f 764 ulong addr;
63656b76 765 int alen;
81a8824f
WD
766 ulong data;
767 int size = 1;
768 int nbytes;
63656b76
SG
769 int ret;
770#ifdef CONFIG_DM_I2C
771 struct udevice *dev;
772#endif
81a8824f 773
47e26b1b 774 if (argc != 3)
4c12eeb8 775 return CMD_RET_USAGE;
81a8824f 776
b26440f1 777 bootretry_reset_cmd_timeout(); /* got a good command to get here */
81a8824f
WD
778 /*
779 * We use the last specified parameters, unless new ones are
780 * entered.
781 */
782 chip = i2c_mm_last_chip;
783 addr = i2c_mm_last_addr;
784 alen = i2c_mm_last_alen;
785
786 if ((flag & CMD_FLAG_REPEAT) == 0) {
787 /*
788 * New command specified. Check for a size specification.
789 * Defaults to byte if no or incorrect specification.
790 */
791 size = cmd_get_data_size(argv[0], 1);
792
793 /*
53677ef1
WD
794 * Chip is always specified.
795 */
81a8824f
WD
796 chip = simple_strtoul(argv[1], NULL, 16);
797
798 /*
799 * Address is always specified.
800 */
801 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 802 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 803 if (alen > 3)
4c12eeb8 804 return CMD_RET_USAGE;
81a8824f
WD
805 }
806
63656b76
SG
807#ifdef CONFIG_DM_I2C
808 ret = i2c_get_cur_bus_chip(chip, &dev);
809 if (!ret && alen != -1)
810 ret = i2c_set_chip_offset_len(dev, alen);
811 if (ret)
812 return i2c_report_err(ret, I2C_ERR_WRITE);
813#endif
814
81a8824f
WD
815 /*
816 * Print the address, followed by value. Then accept input for
817 * the next value. A non-converted value exits.
818 */
819 do {
820 printf("%08lx:", addr);
63656b76 821#ifdef CONFIG_DM_I2C
f9a4c2da 822 ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
63656b76
SG
823#else
824 ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
825#endif
826 if (ret)
9e533cb0
MY
827 return i2c_report_err(ret, I2C_ERR_READ);
828
829 data = cpu_to_be32(data);
830 if (size == 1)
831 printf(" %02lx", (data >> 24) & 0x000000FF);
832 else if (size == 2)
833 printf(" %04lx", (data >> 16) & 0x0000FFFF);
834 else
835 printf(" %08lx", data);
81a8824f 836
e1bf824d 837 nbytes = cli_readline(" ? ");
81a8824f
WD
838 if (nbytes == 0) {
839 /*
840 * <CR> pressed as only input, don't modify current
841 * location and move to next.
842 */
843 if (incrflag)
844 addr += size;
845 nbytes = size;
b26440f1
SG
846 /* good enough to not time out */
847 bootretry_reset_cmd_timeout();
81a8824f
WD
848 }
849#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 850 else if (nbytes == -2)
81a8824f 851 break; /* timed out, exit the command */
81a8824f
WD
852#endif
853 else {
854 char *endp;
855
856 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 857 if (size == 1)
81a8824f 858 data = data << 24;
e857a5bd 859 else if (size == 2)
81a8824f 860 data = data << 16;
81a8824f
WD
861 data = be32_to_cpu(data);
862 nbytes = endp - console_buffer;
863 if (nbytes) {
81a8824f
WD
864 /*
865 * good enough to not time out
866 */
b26440f1 867 bootretry_reset_cmd_timeout();
63656b76 868#ifdef CONFIG_DM_I2C
f9a4c2da
SG
869 ret = dm_i2c_write(dev, addr, (uchar *)&data,
870 size);
63656b76
SG
871#else
872 ret = i2c_write(chip, addr, alen,
873 (uchar *)&data, size);
874#endif
875 if (ret)
9e533cb0
MY
876 return i2c_report_err(ret,
877 I2C_ERR_WRITE);
6d0f6bcf
JCPV
878#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
879 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 880#endif
81a8824f
WD
881 if (incrflag)
882 addr += size;
883 }
884 }
885 } while (nbytes);
886
0800707b
PT
887 i2c_mm_last_chip = chip;
888 i2c_mm_last_addr = addr;
889 i2c_mm_last_alen = alen;
81a8824f
WD
890
891 return 0;
892}
893
06afa388
MV
894/**
895 * do_i2c_probe() - Handle the "i2c probe" command-line command
896 * @cmdtp: Command data struct pointer
897 * @flag: Command flag
898 * @argc: Command-line argument count
899 * @argv: Array of command-line arguments
900 *
901 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
902 * on error.
903 *
81a8824f 904 * Syntax:
54b99e51
EN
905 * i2c probe {addr}
906 *
907 * Returns zero (success) if one or more I2C devices was found
81a8824f 908 */
54841ab5 909static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
910{
911 int j;
54b99e51
EN
912 int addr = -1;
913 int found = 0;
6d0f6bcf 914#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 915 int k, skip;
3f4978c7 916 unsigned int bus = GET_BUS_NUM;
bb99ad6d 917#endif /* NOPROBES */
63656b76
SG
918 int ret;
919#ifdef CONFIG_DM_I2C
920 struct udevice *bus, *dev;
921
922 if (i2c_get_cur_bus(&bus))
923 return CMD_RET_FAILURE;
924#endif
81a8824f 925
54b99e51
EN
926 if (argc == 2)
927 addr = simple_strtol(argv[1], 0, 16);
928
4b9206ed 929 puts ("Valid chip addresses:");
e857a5bd 930 for (j = 0; j < 128; j++) {
54b99e51
EN
931 if ((0 <= addr) && (j != addr))
932 continue;
933
6d0f6bcf 934#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 935 skip = 0;
cfb25cc4 936 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 937 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
938 skip = 1;
939 break;
940 }
941 }
942 if (skip)
943 continue;
944#endif
63656b76 945#ifdef CONFIG_DM_I2C
f9a4c2da 946 ret = dm_i2c_probe(bus, j, 0, &dev);
63656b76
SG
947#else
948 ret = i2c_probe(j);
949#endif
950 if (ret == 0) {
81a8824f 951 printf(" %02X", j);
54b99e51
EN
952 found++;
953 }
81a8824f 954 }
4b9206ed 955 putc ('\n');
81a8824f 956
6d0f6bcf 957#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 958 puts ("Excluded chip addresses:");
cfb25cc4 959 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 960 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
961 printf(" %02X", NO_PROBE_ADDR(k));
962 }
4b9206ed 963 putc ('\n');
81a8824f
WD
964#endif
965
54b99e51 966 return (0 == found);
81a8824f
WD
967}
968
06afa388
MV
969/**
970 * do_i2c_loop() - Handle the "i2c loop" command-line command
971 * @cmdtp: Command data struct pointer
972 * @flag: Command flag
973 * @argc: Command-line argument count
974 * @argv: Array of command-line arguments
975 *
976 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
977 * on error.
978 *
81a8824f 979 * Syntax:
0f89c54b 980 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
981 * {length} - Number of bytes to read
982 * {delay} - A DECIMAL number and defaults to 1000 uSec
983 */
54841ab5 984static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 985{
5468461d 986 uint chip;
63656b76 987 int alen;
81a8824f
WD
988 uint addr;
989 uint length;
990 u_char bytes[16];
991 int delay;
63656b76
SG
992 int ret;
993#ifdef CONFIG_DM_I2C
994 struct udevice *dev;
995#endif
81a8824f 996
47e26b1b 997 if (argc < 3)
4c12eeb8 998 return CMD_RET_USAGE;
81a8824f
WD
999
1000 /*
1001 * Chip is always specified.
1002 */
1003 chip = simple_strtoul(argv[1], NULL, 16);
1004
1005 /*
1006 * Address is always specified.
1007 */
1008 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 1009 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 1010 if (alen > 3)
4c12eeb8 1011 return CMD_RET_USAGE;
63656b76
SG
1012#ifdef CONFIG_DM_I2C
1013 ret = i2c_get_cur_bus_chip(chip, &dev);
1014 if (!ret && alen != -1)
1015 ret = i2c_set_chip_offset_len(dev, alen);
1016 if (ret)
1017 return i2c_report_err(ret, I2C_ERR_WRITE);
1018#endif
81a8824f
WD
1019
1020 /*
1021 * Length is the number of objects, not number of bytes.
1022 */
1023 length = 1;
1024 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 1025 if (length > sizeof(bytes))
81a8824f 1026 length = sizeof(bytes);
81a8824f
WD
1027
1028 /*
1029 * The delay time (uSec) is optional.
1030 */
1031 delay = 1000;
e857a5bd 1032 if (argc > 3)
81a8824f 1033 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
1034 /*
1035 * Run the loop...
1036 */
e857a5bd 1037 while (1) {
63656b76 1038#ifdef CONFIG_DM_I2C
f9a4c2da 1039 ret = dm_i2c_read(dev, addr, bytes, length);
63656b76
SG
1040#else
1041 ret = i2c_read(chip, addr, alen, bytes, length);
1042#endif
1043 if (ret)
1044 i2c_report_err(ret, I2C_ERR_READ);
81a8824f
WD
1045 udelay(delay);
1046 }
1047
1048 /* NOTREACHED */
1049 return 0;
1050}
1051
81a8824f
WD
1052/*
1053 * The SDRAM command is separately configured because many
1054 * (most?) embedded boards don't use SDRAM DIMMs.
06afa388
MV
1055 *
1056 * FIXME: Document and probably move elsewhere!
81a8824f 1057 */
c76fe474 1058#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
1059static void print_ddr2_tcyc (u_char const b)
1060{
1061 printf ("%d.", (b >> 4) & 0x0F);
1062 switch (b & 0x0F) {
1063 case 0x0:
1064 case 0x1:
1065 case 0x2:
1066 case 0x3:
1067 case 0x4:
1068 case 0x5:
1069 case 0x6:
1070 case 0x7:
1071 case 0x8:
1072 case 0x9:
1073 printf ("%d ns\n", b & 0x0F);
1074 break;
1075 case 0xA:
1076 puts ("25 ns\n");
1077 break;
1078 case 0xB:
1079 puts ("33 ns\n");
1080 break;
1081 case 0xC:
1082 puts ("66 ns\n");
1083 break;
1084 case 0xD:
1085 puts ("75 ns\n");
1086 break;
1087 default:
1088 puts ("?? ns\n");
1089 break;
1090 }
1091}
1092
1093static void decode_bits (u_char const b, char const *str[], int const do_once)
1094{
1095 u_char mask;
1096
1097 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1098 if (b & mask) {
1099 puts (*str);
1100 if (do_once)
1101 return;
1102 }
1103 }
1104}
81a8824f
WD
1105
1106/*
1107 * Syntax:
0f89c54b 1108 * i2c sdram {i2c_chip}
81a8824f 1109 */
54841ab5 1110static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
81a8824f 1111{
632de067
LJ
1112 enum { unknown, EDO, SDRAM, DDR2 } type;
1113
5468461d 1114 uint chip;
81a8824f
WD
1115 u_char data[128];
1116 u_char cksum;
1117 int j;
1118
632de067
LJ
1119 static const char *decode_CAS_DDR2[] = {
1120 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1121 };
1122
1123 static const char *decode_CAS_default[] = {
1124 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1125 };
1126
1127 static const char *decode_CS_WE_default[] = {
1128 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1129 };
1130
1131 static const char *decode_byte21_default[] = {
1132 " TBD (bit 7)\n",
1133 " Redundant row address\n",
1134 " Differential clock input\n",
1135 " Registerd DQMB inputs\n",
1136 " Buffered DQMB inputs\n",
1137 " On-card PLL\n",
1138 " Registered address/control lines\n",
1139 " Buffered address/control lines\n"
1140 };
1141
1142 static const char *decode_byte22_DDR2[] = {
1143 " TBD (bit 7)\n",
1144 " TBD (bit 6)\n",
1145 " TBD (bit 5)\n",
1146 " TBD (bit 4)\n",
1147 " TBD (bit 3)\n",
1148 " Supports partial array self refresh\n",
1149 " Supports 50 ohm ODT\n",
1150 " Supports weak driver\n"
1151 };
1152
1153 static const char *decode_row_density_DDR2[] = {
1154 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1155 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1156 };
1157
1158 static const char *decode_row_density_default[] = {
1159 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1160 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1161 };
1162
47e26b1b 1163 if (argc < 2)
4c12eeb8 1164 return CMD_RET_USAGE;
47e26b1b 1165
81a8824f
WD
1166 /*
1167 * Chip is always specified.
632de067
LJ
1168 */
1169 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 1170
632de067 1171 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
4b9206ed 1172 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
1173 return 1;
1174 }
1175
1176 cksum = 0;
1177 for (j = 0; j < 63; j++) {
1178 cksum += data[j];
1179 }
e857a5bd 1180 if (cksum != data[63]) {
81a8824f 1181 printf ("WARNING: Configuration data checksum failure:\n"
632de067 1182 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 1183 }
632de067 1184 printf ("SPD data revision %d.%d\n",
81a8824f 1185 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
1186 printf ("Bytes used 0x%02X\n", data[0]);
1187 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1188
4b9206ed 1189 puts ("Memory type ");
632de067 1190 switch (data[2]) {
0df6b844
LJ
1191 case 2:
1192 type = EDO;
1193 puts ("EDO\n");
1194 break;
1195 case 4:
1196 type = SDRAM;
1197 puts ("SDRAM\n");
1198 break;
1199 case 8:
1200 type = DDR2;
1201 puts ("DDR2\n");
1202 break;
1203 default:
1204 type = unknown;
1205 puts ("unknown\n");
1206 break;
81a8824f 1207 }
632de067 1208
4b9206ed 1209 puts ("Row address bits ");
e857a5bd 1210 if ((data[3] & 0x00F0) == 0)
632de067 1211 printf ("%d\n", data[3] & 0x0F);
e857a5bd 1212 else
632de067
LJ
1213 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1214
4b9206ed 1215 puts ("Column address bits ");
e857a5bd 1216 if ((data[4] & 0x00F0) == 0)
632de067 1217 printf ("%d\n", data[4] & 0x0F);
e857a5bd 1218 else
632de067 1219 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
1220
1221 switch (type) {
1222 case DDR2:
632de067
LJ
1223 printf ("Number of ranks %d\n",
1224 (data[5] & 0x07) + 1);
0df6b844
LJ
1225 break;
1226 default:
632de067 1227 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
1228 break;
1229 }
1230
1231 switch (type) {
1232 case DDR2:
632de067 1233 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
1234 break;
1235 default:
632de067
LJ
1236 printf ("Module data width %d bits\n",
1237 (data[7] << 8) | data[6]);
0df6b844
LJ
1238 break;
1239 }
1240
4b9206ed 1241 puts ("Interface signal levels ");
81a8824f 1242 switch(data[8]) {
0df6b844 1243 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 1244 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
1245 case 2: puts ("HSTL 1.5 V\n"); break;
1246 case 3: puts ("SSTL 3.3 V\n"); break;
1247 case 4: puts ("SSTL 2.5 V\n"); break;
1248 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 1249 default: puts ("unknown\n"); break;
81a8824f 1250 }
0df6b844
LJ
1251
1252 switch (type) {
1253 case DDR2:
632de067
LJ
1254 printf ("SDRAM cycle time ");
1255 print_ddr2_tcyc (data[9]);
0df6b844
LJ
1256 break;
1257 default:
632de067
LJ
1258 printf ("SDRAM cycle time %d.%d ns\n",
1259 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
1260 break;
1261 }
1262
1263 switch (type) {
1264 case DDR2:
632de067
LJ
1265 printf ("SDRAM access time 0.%d%d ns\n",
1266 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1267 break;
1268 default:
632de067
LJ
1269 printf ("SDRAM access time %d.%d ns\n",
1270 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1271 break;
1272 }
1273
4b9206ed 1274 puts ("EDC configuration ");
632de067 1275 switch (data[11]) {
4b9206ed
WD
1276 case 0: puts ("None\n"); break;
1277 case 1: puts ("Parity\n"); break;
1278 case 2: puts ("ECC\n"); break;
1279 default: puts ("unknown\n"); break;
81a8824f 1280 }
632de067 1281
e857a5bd 1282 if ((data[12] & 0x80) == 0)
4b9206ed 1283 puts ("No self refresh, rate ");
e857a5bd 1284 else
4b9206ed 1285 puts ("Self refresh, rate ");
632de067 1286
81a8824f 1287 switch(data[12] & 0x7F) {
632de067
LJ
1288 case 0: puts ("15.625 us\n"); break;
1289 case 1: puts ("3.9 us\n"); break;
1290 case 2: puts ("7.8 us\n"); break;
1291 case 3: puts ("31.3 us\n"); break;
1292 case 4: puts ("62.5 us\n"); break;
1293 case 5: puts ("125 us\n"); break;
4b9206ed 1294 default: puts ("unknown\n"); break;
81a8824f 1295 }
0df6b844
LJ
1296
1297 switch (type) {
1298 case DDR2:
632de067 1299 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
1300 break;
1301 default:
632de067 1302 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 1303 if ((data[13] & 0x80) != 0) {
632de067
LJ
1304 printf (" (second bank) %d\n",
1305 2 * (data[13] & 0x7F));
0df6b844
LJ
1306 }
1307 break;
1308 }
1309
1310 switch (type) {
1311 case DDR2:
1312 if (data[14] != 0)
632de067 1313 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
1314 break;
1315 default:
1316 if (data[14] != 0) {
632de067
LJ
1317 printf ("EDC width %d\n",
1318 data[14] & 0x7F);
0df6b844
LJ
1319
1320 if ((data[14] & 0x80) != 0) {
632de067
LJ
1321 printf (" (second bank) %d\n",
1322 2 * (data[14] & 0x7F));
0df6b844
LJ
1323 }
1324 }
1325 break;
81a8824f 1326 }
0df6b844 1327
632de067
LJ
1328 if (DDR2 != type) {
1329 printf ("Min clock delay, back-to-back random column addresses "
1330 "%d\n", data[15]);
0df6b844
LJ
1331 }
1332
4b9206ed
WD
1333 puts ("Burst length(s) ");
1334 if (data[16] & 0x80) puts (" Page");
1335 if (data[16] & 0x08) puts (" 8");
1336 if (data[16] & 0x04) puts (" 4");
1337 if (data[16] & 0x02) puts (" 2");
1338 if (data[16] & 0x01) puts (" 1");
1339 putc ('\n');
632de067 1340 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1341
1342 switch (type) {
1343 case DDR2:
1344 puts ("CAS latency(s) ");
632de067 1345 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1346 putc ('\n');
1347 break;
1348 default:
1349 puts ("CAS latency(s) ");
632de067 1350 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1351 putc ('\n');
1352 break;
1353 }
1354
1355 if (DDR2 != type) {
1356 puts ("CS latency(s) ");
632de067 1357 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1358 putc ('\n');
1359 }
1360
1361 if (DDR2 != type) {
1362 puts ("WE latency(s) ");
632de067 1363 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1364 putc ('\n');
1365 }
1366
1367 switch (type) {
1368 case DDR2:
1369 puts ("Module attributes:\n");
1370 if (data[21] & 0x80)
1371 puts (" TBD (bit 7)\n");
1372 if (data[21] & 0x40)
1373 puts (" Analysis probe installed\n");
1374 if (data[21] & 0x20)
1375 puts (" TBD (bit 5)\n");
1376 if (data[21] & 0x10)
1377 puts (" FET switch external enable\n");
632de067 1378 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1379 if (data[20] & 0x11) {
632de067
LJ
1380 printf (" %d active registers on DIMM\n",
1381 (data[21] & 0x03) + 1);
0df6b844
LJ
1382 }
1383 break;
1384 default:
1385 puts ("Module attributes:\n");
1386 if (!data[21])
1387 puts (" (none)\n");
632de067
LJ
1388 else
1389 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1390 break;
1391 }
1392
1393 switch (type) {
1394 case DDR2:
632de067 1395 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1396 break;
1397 default:
1398 puts ("Device attributes:\n");
1399 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1400 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1401 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1402 else puts (" Upper Vcc tolerance 10%\n");
1403 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1404 else puts (" Lower Vcc tolerance 10%\n");
1405 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1406 if (data[22] & 0x04) puts (" Supports precharge all\n");
1407 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1408 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1409 break;
1410 }
1411
1412 switch (type) {
1413 case DDR2:
632de067
LJ
1414 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1415 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1416 break;
1417 default:
632de067
LJ
1418 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1419 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1420 break;
1421 }
1422
1423 switch (type) {
1424 case DDR2:
632de067
LJ
1425 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1426 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1427 break;
1428 default:
632de067
LJ
1429 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1430 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1431 break;
1432 }
1433
1434 switch (type) {
1435 case DDR2:
632de067
LJ
1436 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1437 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1438 break;
1439 default:
632de067
LJ
1440 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1441 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1442 break;
1443 }
1444
1445 switch (type) {
1446 case DDR2:
632de067
LJ
1447 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1448 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1449 break;
1450 default:
632de067
LJ
1451 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1452 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1453 break;
1454 }
1455
1456 switch (type) {
1457 case DDR2:
632de067
LJ
1458 printf ("Minimum row precharge %d.%02d ns\n",
1459 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1460 break;
1461 default:
632de067 1462 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1463 break;
1464 }
1465
1466 switch (type) {
1467 case DDR2:
632de067
LJ
1468 printf ("Row active to row active min %d.%02d ns\n",
1469 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1470 break;
1471 default:
632de067 1472 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1473 break;
1474 }
1475
1476 switch (type) {
1477 case DDR2:
632de067
LJ
1478 printf ("RAS to CAS delay min %d.%02d ns\n",
1479 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1480 break;
1481 default:
632de067 1482 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1483 break;
1484 }
1485
632de067 1486 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1487
1488 switch (type) {
1489 case DDR2:
632de067
LJ
1490 puts ("Density of each row ");
1491 decode_bits (data[31], decode_row_density_DDR2, 1);
1492 putc ('\n');
0df6b844
LJ
1493 break;
1494 default:
632de067
LJ
1495 puts ("Density of each row ");
1496 decode_bits (data[31], decode_row_density_default, 1);
1497 putc ('\n');
0df6b844
LJ
1498 break;
1499 }
1500
1501 switch (type) {
1502 case DDR2:
632de067 1503 puts ("Command and Address setup ");
0df6b844 1504 if (data[32] >= 0xA0) {
632de067
LJ
1505 printf ("1.%d%d ns\n",
1506 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1507 } else {
632de067
LJ
1508 printf ("0.%d%d ns\n",
1509 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1510 }
1511 break;
1512 default:
632de067
LJ
1513 printf ("Command and Address setup %c%d.%d ns\n",
1514 (data[32] & 0x80) ? '-' : '+',
1515 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1516 break;
1517 }
1518
1519 switch (type) {
1520 case DDR2:
632de067 1521 puts ("Command and Address hold ");
0df6b844 1522 if (data[33] >= 0xA0) {
632de067
LJ
1523 printf ("1.%d%d ns\n",
1524 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1525 } else {
632de067
LJ
1526 printf ("0.%d%d ns\n",
1527 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1528 }
1529 break;
1530 default:
632de067
LJ
1531 printf ("Command and Address hold %c%d.%d ns\n",
1532 (data[33] & 0x80) ? '-' : '+',
1533 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1534 break;
1535 }
1536
1537 switch (type) {
1538 case DDR2:
632de067
LJ
1539 printf ("Data signal input setup 0.%d%d ns\n",
1540 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1541 break;
1542 default:
632de067
LJ
1543 printf ("Data signal input setup %c%d.%d ns\n",
1544 (data[34] & 0x80) ? '-' : '+',
1545 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1546 break;
1547 }
1548
1549 switch (type) {
1550 case DDR2:
632de067
LJ
1551 printf ("Data signal input hold 0.%d%d ns\n",
1552 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1553 break;
1554 default:
632de067
LJ
1555 printf ("Data signal input hold %c%d.%d ns\n",
1556 (data[35] & 0x80) ? '-' : '+',
1557 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1558 break;
1559 }
1560
4b9206ed 1561 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1562 for (j = 64; j <= 71; j++)
632de067 1563 printf ("%02X ", data[j]);
4b9206ed 1564 putc ('\n');
632de067 1565 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1566 puts ("Manufacturer's Part Number ");
e857a5bd 1567 for (j = 73; j <= 90; j++)
632de067 1568 printf ("%02X ", data[j]);
4b9206ed 1569 putc ('\n');
632de067
LJ
1570 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1571 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1572 puts ("Assembly Serial Number ");
e857a5bd 1573 for (j = 95; j <= 98; j++)
632de067 1574 printf ("%02X ", data[j]);
4b9206ed 1575 putc ('\n');
81a8824f 1576
0df6b844 1577 if (DDR2 != type) {
632de067
LJ
1578 printf ("Speed rating PC%d\n",
1579 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1580 }
81a8824f
WD
1581 return 0;
1582}
90253178 1583#endif
81a8824f 1584
735987c5
TWHT
1585/*
1586 * Syntax:
1587 * i2c edid {i2c_chip}
1588 */
1589#if defined(CONFIG_I2C_EDID)
1590int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1591{
5468461d 1592 uint chip;
735987c5 1593 struct edid1_info edid;
63656b76
SG
1594 int ret;
1595#ifdef CONFIG_DM_I2C
1596 struct udevice *dev;
1597#endif
735987c5
TWHT
1598
1599 if (argc < 2) {
1600 cmd_usage(cmdtp);
1601 return 1;
1602 }
1603
1604 chip = simple_strtoul(argv[1], NULL, 16);
63656b76
SG
1605#ifdef CONFIG_DM_I2C
1606 ret = i2c_get_cur_bus_chip(chip, &dev);
1607 if (!ret)
f9a4c2da 1608 ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
63656b76
SG
1609#else
1610 ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1611#endif
1612 if (ret)
1613 return i2c_report_err(ret, I2C_ERR_READ);
735987c5
TWHT
1614
1615 if (edid_check_info(&edid)) {
1616 puts("Content isn't valid EDID.\n");
1617 return 1;
1618 }
1619
1620 edid_print_info(&edid);
1621 return 0;
1622
1623}
1624#endif /* CONFIG_I2C_EDID */
1625
06afa388 1626/**
3f4978c7 1627 * do_i2c_show_bus() - Handle the "i2c bus" command-line command
06afa388
MV
1628 * @cmdtp: Command data struct pointer
1629 * @flag: Command flag
1630 * @argc: Command-line argument count
1631 * @argv: Array of command-line arguments
1632 *
1633 * Returns zero always.
1634 */
3f4978c7 1635#if defined(CONFIG_SYS_I2C)
0e350f81
JH
1636static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
1637 char * const argv[])
67b23a32 1638{
3f4978c7
HS
1639 int i;
1640#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1641 int j;
1642#endif
67b23a32
HS
1643
1644 if (argc == 1) {
1645 /* show all busses */
3f4978c7
HS
1646 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1647 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1648#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1649 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1650 if (i2c_bus[i].next_hop[j].chip == 0)
1651 break;
1652 printf("->%s@0x%2x:%d",
1653 i2c_bus[i].next_hop[j].mux.name,
1654 i2c_bus[i].next_hop[j].chip,
1655 i2c_bus[i].next_hop[j].channel);
67b23a32 1656 }
3f4978c7
HS
1657#endif
1658 printf("\n");
67b23a32
HS
1659 }
1660 } else {
3f4978c7
HS
1661 /* show specific bus */
1662 i = simple_strtoul(argv[1], NULL, 10);
1663 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1664 printf("Invalid bus %d\n", i);
1665 return -1;
1666 }
1667 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1668#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1669 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1670 if (i2c_bus[i].next_hop[j].chip == 0)
1671 break;
1672 printf("->%s@0x%2x:%d",
1673 i2c_bus[i].next_hop[j].mux.name,
1674 i2c_bus[i].next_hop[j].chip,
1675 i2c_bus[i].next_hop[j].channel);
1676 }
1677#endif
1678 printf("\n");
67b23a32 1679 }
3f4978c7
HS
1680
1681 return 0;
67b23a32 1682}
3f4978c7 1683#endif
67b23a32 1684
06afa388
MV
1685/**
1686 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1687 * @cmdtp: Command data struct pointer
1688 * @flag: Command flag
1689 * @argc: Command-line argument count
1690 * @argv: Array of command-line arguments
1691 *
1692 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1693 * on error.
1694 */
63656b76
SG
1695#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1696 defined(CONFIG_DM_I2C)
0e350f81
JH
1697static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
1698 char * const argv[])
bb99ad6d 1699{
3f4978c7 1700 int ret = 0;
63656b76 1701 int bus_no;
bb99ad6d 1702
63656b76 1703 if (argc == 1) {
e857a5bd 1704 /* querying current setting */
63656b76
SG
1705#ifdef CONFIG_DM_I2C
1706 struct udevice *bus;
1707
1708 if (!i2c_get_cur_bus(&bus))
1709 bus_no = bus->seq;
1710 else
1711 bus_no = -1;
1712#else
1713 bus_no = i2c_get_bus_num();
1714#endif
1715 printf("Current bus is %d\n", bus_no);
1716 } else {
3f4978c7 1717 bus_no = simple_strtoul(argv[1], NULL, 10);
880a4127 1718#if defined(CONFIG_SYS_I2C)
3f4978c7
HS
1719 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1720 printf("Invalid bus %d\n", bus_no);
1721 return -1;
1722 }
880a4127 1723#endif
3f4978c7 1724 printf("Setting bus to %d\n", bus_no);
f9a4c2da
SG
1725#ifdef CONFIG_DM_I2C
1726 ret = cmd_i2c_set_bus_num(bus_no);
1727#else
3f4978c7 1728 ret = i2c_set_bus_num(bus_no);
f9a4c2da 1729#endif
e857a5bd 1730 if (ret)
bb99ad6d 1731 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d
BW
1732 }
1733 return ret;
1734}
3f4978c7 1735#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d 1736
06afa388
MV
1737/**
1738 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1739 * @cmdtp: Command data struct pointer
1740 * @flag: Command flag
1741 * @argc: Command-line argument count
1742 * @argv: Array of command-line arguments
1743 *
1744 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1745 * on error.
1746 */
54841ab5 1747static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1748{
1749 int speed, ret=0;
1750
63656b76
SG
1751#ifdef CONFIG_DM_I2C
1752 struct udevice *bus;
1753
1754 if (i2c_get_cur_bus(&bus))
1755 return 1;
1756#endif
1757 if (argc == 1) {
1758#ifdef CONFIG_DM_I2C
ca88b9b9 1759 speed = dm_i2c_get_bus_speed(bus);
63656b76
SG
1760#else
1761 speed = i2c_get_bus_speed();
1762#endif
e857a5bd 1763 /* querying current speed */
63656b76
SG
1764 printf("Current bus speed=%d\n", speed);
1765 } else {
bb99ad6d
BW
1766 speed = simple_strtoul(argv[1], NULL, 10);
1767 printf("Setting bus speed to %d Hz\n", speed);
63656b76 1768#ifdef CONFIG_DM_I2C
ca88b9b9 1769 ret = dm_i2c_set_bus_speed(bus, speed);
63656b76 1770#else
bb99ad6d 1771 ret = i2c_set_bus_speed(speed);
63656b76 1772#endif
e857a5bd 1773 if (ret)
bb99ad6d 1774 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d
BW
1775 }
1776 return ret;
1777}
1778
06afa388
MV
1779/**
1780 * do_i2c_mm() - Handle the "i2c mm" command-line command
1781 * @cmdtp: Command data struct pointer
1782 * @flag: Command flag
1783 * @argc: Command-line argument count
1784 * @argv: Array of command-line arguments
1785 *
1786 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1787 * on error.
1788 */
54841ab5 1789static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1790{
bfc3b77e
FM
1791 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1792}
1793
06afa388
MV
1794/**
1795 * do_i2c_nm() - Handle the "i2c nm" command-line command
1796 * @cmdtp: Command data struct pointer
1797 * @flag: Command flag
1798 * @argc: Command-line argument count
1799 * @argv: Array of command-line arguments
1800 *
1801 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1802 * on error.
1803 */
54841ab5 1804static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1805{
1806 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1807}
e96ad5d3 1808
06afa388
MV
1809/**
1810 * do_i2c_reset() - Handle the "i2c reset" command-line command
1811 * @cmdtp: Command data struct pointer
1812 * @flag: Command flag
1813 * @argc: Command-line argument count
1814 * @argv: Array of command-line arguments
1815 *
1816 * Returns zero always.
1817 */
54841ab5 1818static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e 1819{
63656b76
SG
1820#if defined(CONFIG_DM_I2C)
1821 struct udevice *bus;
1822
1823 if (i2c_get_cur_bus(&bus))
1824 return CMD_RET_FAILURE;
1825 if (i2c_deblock(bus)) {
1826 printf("Error: Not supported by the driver\n");
1827 return CMD_RET_FAILURE;
1828 }
1829#elif defined(CONFIG_SYS_I2C)
3f4978c7
HS
1830 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1831#else
bfc3b77e 1832 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3f4978c7 1833#endif
bfc3b77e
FM
1834 return 0;
1835}
1836
1837static cmd_tbl_t cmd_i2c_sub[] = {
3f4978c7
HS
1838#if defined(CONFIG_SYS_I2C)
1839 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
9a2accb4 1840#endif
bfc3b77e 1841 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
3f4978c7 1842#if defined(CONFIG_SYS_I2C) || \
63656b76 1843 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
bfc3b77e 1844 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1845#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1846#if defined(CONFIG_I2C_EDID)
1847 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1848#endif /* CONFIG_I2C_EDID */
bfc3b77e
FM
1849 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1850 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1851 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1852 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1853 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1854 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1855 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ed16f146 1856 U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
63656b76
SG
1857#ifdef CONFIG_DM_I2C
1858 U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
1859#endif
bfc3b77e 1860 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1861#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1862 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1863#endif
bfc3b77e
FM
1864 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1865};
1866
2e5167cc 1867#ifdef CONFIG_NEEDS_MANUAL_RELOC
f1d2b313
HS
1868void i2c_reloc(void) {
1869 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1870}
1871#endif
1872
06afa388
MV
1873/**
1874 * do_i2c() - Handle the "i2c" command-line command
1875 * @cmdtp: Command data struct pointer
1876 * @flag: Command flag
1877 * @argc: Command-line argument count
1878 * @argv: Array of command-line arguments
1879 *
1880 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1881 * on error.
1882 */
54841ab5 1883static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1884{
1885 cmd_tbl_t *c;
1886
4444b221 1887 if (argc < 2)
4c12eeb8 1888 return CMD_RET_USAGE;
4444b221 1889
bfc3b77e
FM
1890 /* Strip off leading 'i2c' command argument */
1891 argc--;
1892 argv++;
1893
1894 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1895
47e26b1b 1896 if (c)
4c12eeb8 1897 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 1898 else
4c12eeb8 1899 return CMD_RET_USAGE;
bb99ad6d 1900}
8bde7f77
WD
1901
1902/***************************************************/
088f1b19
KP
1903#ifdef CONFIG_SYS_LONGHELP
1904static char i2c_help_text[] =
3f4978c7
HS
1905#if defined(CONFIG_SYS_I2C)
1906 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
9a2accb4 1907#endif
fb0070e9 1908 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
3f4978c7 1909#if defined(CONFIG_SYS_I2C) || \
63656b76 1910 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
9bc2e4ee 1911 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 1912#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1913#if defined(CONFIG_I2C_EDID)
1914 "i2c edid chip - print EDID configuration information\n"
1915#endif /* CONFIG_I2C_EDID */
fb0070e9 1916 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
1917 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1918 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1919 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1920 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 1921 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
63656b76 1922 "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
ed16f146
LP
1923 "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
1924 " to I2C; the -s option selects bulk write in a single transaction\n"
63656b76
SG
1925#ifdef CONFIG_DM_I2C
1926 "i2c flags chip [flags] - set or get chip flags\n"
1927#endif
e43a27c4 1928 "i2c reset - re-init the I2C Controller\n"
c76fe474 1929#if defined(CONFIG_CMD_SDRAM)
fb0070e9 1930 "i2c sdram chip - print SDRAM configuration information\n"
90253178 1931#endif
088f1b19
KP
1932 "i2c speed [speed] - show or set I2C bus speed";
1933#endif
1934
1935U_BOOT_CMD(
ed16f146 1936 i2c, 7, 1, do_i2c,
088f1b19
KP
1937 "I2C sub-system",
1938 i2c_help_text
d9fc7032 1939);