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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * I2C Functions similar to the standard memory functions. | |
26 | * | |
27 | * There are several parameters in many of the commands that bear further | |
28 | * explanations: | |
29 | * | |
30 | * Two of the commands (imm and imw) take a byte/word/long modifier | |
31 | * (e.g. imm.w specifies the word-length modifier). This was done to | |
32 | * allow manipulating word-length registers. It was not done on any other | |
33 | * commands because it was not deemed useful. | |
34 | * | |
35 | * {i2c_chip} is the I2C chip address (the first byte sent on the bus). | |
36 | * Each I2C chip on the bus has a unique address. On the I2C data bus, | |
37 | * the address is the upper seven bits and the LSB is the "read/write" | |
38 | * bit. Note that the {i2c_chip} address specified on the command | |
39 | * line is not shifted up: e.g. a typical EEPROM memory chip may have | |
40 | * an I2C address of 0x50, but the data put on the bus will be 0xA0 | |
41 | * for write and 0xA1 for read. This "non shifted" address notation | |
42 | * matches at least half of the data sheets :-/. | |
43 | * | |
44 | * {addr} is the address (or offset) within the chip. Small memory | |
45 | * chips have 8 bit addresses. Large memory chips have 16 bit | |
46 | * addresses. Other memory chips have 9, 10, or 11 bit addresses. | |
47 | * Many non-memory chips have multiple registers and {addr} is used | |
48 | * as the register index. Some non-memory chips have only one register | |
49 | * and therefore don't need any {addr} parameter. | |
50 | * | |
51 | * The default {addr} parameter is one byte (.1) which works well for | |
52 | * memories and registers with 8 bits of address space. | |
53 | * | |
54 | * You can specify the length of the {addr} field with the optional .0, | |
55 | * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are | |
56 | * manipulating a single register device which doesn't use an address | |
57 | * field, use "0.0" for the address and the ".0" length field will | |
58 | * suppress the address in the I2C data stream. This also works for | |
59 | * successive reads using the I2C auto-incrementing memory pointer. | |
60 | * | |
61 | * If you are manipulating a large memory with 2-byte addresses, use | |
62 | * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal). | |
63 | * | |
64 | * Then there are the unfortunate memory chips that spill the most | |
65 | * significant 1, 2, or 3 bits of address into the chip address byte. | |
66 | * This effectively makes one chip (logically) look like 2, 4, or | |
67 | * 8 chips. This is handled (awkwardly) by #defining | |
6d0f6bcf | 68 | * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the |
81a8824f WD |
69 | * {addr} field (since .1 is the default, it doesn't actually have to |
70 | * be specified). Examples: given a memory chip at I2C chip address | |
71 | * 0x50, the following would happen... | |
72 | * imd 50 0 10 display 16 bytes starting at 0x000 | |
73 | * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd> | |
74 | * imd 50 100 10 display 16 bytes starting at 0x100 | |
75 | * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd> | |
76 | * imd 50 210 10 display 16 bytes starting at 0x210 | |
77 | * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd> | |
78 | * This is awfully ugly. It would be nice if someone would think up | |
79 | * a better way of handling this. | |
80 | * | |
81 | * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). | |
82 | */ | |
83 | ||
84 | #include <common.h> | |
85 | #include <command.h> | |
67b23a32 | 86 | #include <environment.h> |
81a8824f | 87 | #include <i2c.h> |
67b23a32 | 88 | #include <malloc.h> |
81a8824f WD |
89 | #include <asm/byteorder.h> |
90 | ||
81a8824f WD |
91 | /* Display values from last command. |
92 | * Memory modify remembered values are different from display memory. | |
93 | */ | |
94 | static uchar i2c_dp_last_chip; | |
95 | static uint i2c_dp_last_addr; | |
96 | static uint i2c_dp_last_alen; | |
97 | static uint i2c_dp_last_length = 0x10; | |
98 | ||
99 | static uchar i2c_mm_last_chip; | |
100 | static uint i2c_mm_last_addr; | |
101 | static uint i2c_mm_last_alen; | |
102 | ||
bb99ad6d BW |
103 | /* If only one I2C bus is present, the list of devices to ignore when |
104 | * the probe command is issued is represented by a 1D array of addresses. | |
105 | * When multiple buses are present, the list is an array of bus-address | |
106 | * pairs. The following macros take care of this */ | |
107 | ||
6d0f6bcf | 108 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
bb99ad6d BW |
109 | #if defined(CONFIG_I2C_MULTI_BUS) |
110 | static struct | |
111 | { | |
112 | uchar bus; | |
113 | uchar addr; | |
6d0f6bcf | 114 | } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; |
bb99ad6d BW |
115 | #define GET_BUS_NUM i2c_get_bus_num() |
116 | #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) | |
117 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) | |
118 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr | |
119 | #else /* single bus */ | |
6d0f6bcf | 120 | static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; |
bb99ad6d BW |
121 | #define GET_BUS_NUM 0 |
122 | #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ | |
123 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) | |
124 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)] | |
125 | #endif /* CONFIG_MULTI_BUS */ | |
126 | ||
127 | #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0])) | |
81a8824f WD |
128 | #endif |
129 | ||
67b23a32 HS |
130 | #if defined(CONFIG_I2C_MUX) |
131 | static I2C_MUX_DEVICE *i2c_mux_devices = NULL; | |
6d0f6bcf | 132 | static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS; |
67b23a32 HS |
133 | |
134 | DECLARE_GLOBAL_DATA_PTR; | |
135 | ||
136 | #endif | |
137 | ||
81a8824f WD |
138 | static int |
139 | mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); | |
81a8824f WD |
140 | |
141 | /* | |
142 | * Syntax: | |
143 | * imd {i2c_chip} {addr}{.0, .1, .2} {len} | |
144 | */ | |
145 | #define DISP_LINE_LEN 16 | |
146 | ||
147 | int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
148 | { | |
149 | u_char chip; | |
150 | uint addr, alen, length; | |
151 | int j, nbytes, linebytes; | |
152 | ||
153 | /* We use the last specified parameters, unless new ones are | |
154 | * entered. | |
155 | */ | |
156 | chip = i2c_dp_last_chip; | |
157 | addr = i2c_dp_last_addr; | |
158 | alen = i2c_dp_last_alen; | |
159 | length = i2c_dp_last_length; | |
160 | ||
161 | if (argc < 3) { | |
62c3ae7c | 162 | cmd_usage(cmdtp); |
81a8824f WD |
163 | return 1; |
164 | } | |
165 | ||
166 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
167 | /* | |
168 | * New command specified. | |
169 | */ | |
170 | alen = 1; | |
171 | ||
172 | /* | |
173 | * I2C chip address | |
174 | */ | |
175 | chip = simple_strtoul(argv[1], NULL, 16); | |
176 | ||
177 | /* | |
178 | * I2C data address within the chip. This can be 1 or | |
179 | * 2 bytes long. Some day it might be 3 bytes long :-). | |
180 | */ | |
181 | addr = simple_strtoul(argv[2], NULL, 16); | |
182 | alen = 1; | |
e857a5bd | 183 | for (j = 0; j < 8; j++) { |
81a8824f WD |
184 | if (argv[2][j] == '.') { |
185 | alen = argv[2][j+1] - '0'; | |
186 | if (alen > 4) { | |
62c3ae7c | 187 | cmd_usage(cmdtp); |
81a8824f WD |
188 | return 1; |
189 | } | |
190 | break; | |
e857a5bd | 191 | } else if (argv[2][j] == '\0') |
81a8824f | 192 | break; |
81a8824f WD |
193 | } |
194 | ||
195 | /* | |
196 | * If another parameter, it is the length to display. | |
197 | * Length is the number of objects, not number of bytes. | |
198 | */ | |
199 | if (argc > 3) | |
200 | length = simple_strtoul(argv[3], NULL, 16); | |
201 | } | |
202 | ||
203 | /* | |
204 | * Print the lines. | |
205 | * | |
206 | * We buffer all read data, so we can make sure data is read only | |
207 | * once. | |
208 | */ | |
209 | nbytes = length; | |
210 | do { | |
211 | unsigned char linebuf[DISP_LINE_LEN]; | |
212 | unsigned char *cp; | |
213 | ||
214 | linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; | |
215 | ||
e857a5bd | 216 | if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) |
4b9206ed | 217 | puts ("Error reading the chip.\n"); |
e857a5bd | 218 | else { |
81a8824f WD |
219 | printf("%04x:", addr); |
220 | cp = linebuf; | |
221 | for (j=0; j<linebytes; j++) { | |
222 | printf(" %02x", *cp++); | |
223 | addr++; | |
224 | } | |
4b9206ed | 225 | puts (" "); |
81a8824f WD |
226 | cp = linebuf; |
227 | for (j=0; j<linebytes; j++) { | |
228 | if ((*cp < 0x20) || (*cp > 0x7e)) | |
4b9206ed | 229 | puts ("."); |
81a8824f WD |
230 | else |
231 | printf("%c", *cp); | |
232 | cp++; | |
233 | } | |
4b9206ed | 234 | putc ('\n'); |
81a8824f WD |
235 | } |
236 | nbytes -= linebytes; | |
237 | } while (nbytes > 0); | |
238 | ||
239 | i2c_dp_last_chip = chip; | |
240 | i2c_dp_last_addr = addr; | |
241 | i2c_dp_last_alen = alen; | |
242 | i2c_dp_last_length = length; | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
248 | { | |
249 | return mod_i2c_mem (cmdtp, 1, flag, argc, argv); | |
250 | } | |
251 | ||
81a8824f WD |
252 | int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
253 | { | |
254 | return mod_i2c_mem (cmdtp, 0, flag, argc, argv); | |
255 | } | |
256 | ||
257 | /* Write (fill) memory | |
258 | * | |
259 | * Syntax: | |
260 | * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] | |
261 | */ | |
262 | int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
263 | { | |
264 | uchar chip; | |
265 | ulong addr; | |
266 | uint alen; | |
267 | uchar byte; | |
268 | int count; | |
269 | int j; | |
270 | ||
271 | if ((argc < 4) || (argc > 5)) { | |
62c3ae7c | 272 | cmd_usage(cmdtp); |
81a8824f WD |
273 | return 1; |
274 | } | |
275 | ||
276 | /* | |
53677ef1 WD |
277 | * Chip is always specified. |
278 | */ | |
81a8824f WD |
279 | chip = simple_strtoul(argv[1], NULL, 16); |
280 | ||
281 | /* | |
282 | * Address is always specified. | |
283 | */ | |
284 | addr = simple_strtoul(argv[2], NULL, 16); | |
285 | alen = 1; | |
e857a5bd | 286 | for (j = 0; j < 8; j++) { |
81a8824f WD |
287 | if (argv[2][j] == '.') { |
288 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 289 | if (alen > 4) { |
62c3ae7c | 290 | cmd_usage(cmdtp); |
81a8824f WD |
291 | return 1; |
292 | } | |
293 | break; | |
e857a5bd | 294 | } else if (argv[2][j] == '\0') |
81a8824f | 295 | break; |
81a8824f WD |
296 | } |
297 | ||
298 | /* | |
299 | * Value to write is always specified. | |
300 | */ | |
301 | byte = simple_strtoul(argv[3], NULL, 16); | |
302 | ||
303 | /* | |
304 | * Optional count | |
305 | */ | |
e857a5bd | 306 | if (argc == 5) |
81a8824f | 307 | count = simple_strtoul(argv[4], NULL, 16); |
e857a5bd | 308 | else |
81a8824f | 309 | count = 1; |
81a8824f WD |
310 | |
311 | while (count-- > 0) { | |
e857a5bd | 312 | if (i2c_write(chip, addr++, alen, &byte, 1) != 0) |
4b9206ed | 313 | puts ("Error writing the chip.\n"); |
81a8824f WD |
314 | /* |
315 | * Wait for the write to complete. The write can take | |
316 | * up to 10mSec (we allow a little more time). | |
317 | * | |
318 | * On some chips, while the write is in progress, the | |
319 | * chip doesn't respond. This apparently isn't a | |
320 | * universal feature so we don't take advantage of it. | |
321 | */ | |
d4f5c728 | 322 | /* |
323 | * No write delay with FRAM devices. | |
324 | */ | |
6d0f6bcf | 325 | #if !defined(CONFIG_SYS_I2C_FRAM) |
81a8824f | 326 | udelay(11000); |
d4f5c728 | 327 | #endif |
328 | ||
81a8824f | 329 | #if 0 |
e857a5bd | 330 | for (timeout = 0; timeout < 10; timeout++) { |
81a8824f | 331 | udelay(2000); |
e857a5bd | 332 | if (i2c_probe(chip) == 0) |
81a8824f WD |
333 | break; |
334 | } | |
335 | #endif | |
336 | } | |
337 | ||
338 | return (0); | |
339 | } | |
340 | ||
81a8824f WD |
341 | /* Calculate a CRC on memory |
342 | * | |
343 | * Syntax: | |
344 | * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count} | |
345 | */ | |
346 | int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
347 | { | |
348 | uchar chip; | |
349 | ulong addr; | |
350 | uint alen; | |
351 | int count; | |
352 | uchar byte; | |
353 | ulong crc; | |
354 | ulong err; | |
355 | int j; | |
356 | ||
357 | if (argc < 4) { | |
62c3ae7c | 358 | cmd_usage(cmdtp); |
81a8824f WD |
359 | return 1; |
360 | } | |
361 | ||
362 | /* | |
53677ef1 WD |
363 | * Chip is always specified. |
364 | */ | |
81a8824f WD |
365 | chip = simple_strtoul(argv[1], NULL, 16); |
366 | ||
367 | /* | |
368 | * Address is always specified. | |
369 | */ | |
370 | addr = simple_strtoul(argv[2], NULL, 16); | |
371 | alen = 1; | |
e857a5bd | 372 | for (j = 0; j < 8; j++) { |
81a8824f WD |
373 | if (argv[2][j] == '.') { |
374 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 375 | if (alen > 4) { |
62c3ae7c | 376 | cmd_usage(cmdtp); |
81a8824f WD |
377 | return 1; |
378 | } | |
379 | break; | |
e857a5bd | 380 | } else if (argv[2][j] == '\0') |
81a8824f | 381 | break; |
81a8824f WD |
382 | } |
383 | ||
384 | /* | |
385 | * Count is always specified | |
386 | */ | |
387 | count = simple_strtoul(argv[3], NULL, 16); | |
388 | ||
389 | printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1); | |
390 | /* | |
391 | * CRC a byte at a time. This is going to be slooow, but hey, the | |
392 | * memories are small and slow too so hopefully nobody notices. | |
393 | */ | |
394 | crc = 0; | |
395 | err = 0; | |
e857a5bd TT |
396 | while (count-- > 0) { |
397 | if (i2c_read(chip, addr, alen, &byte, 1) != 0) | |
81a8824f | 398 | err++; |
81a8824f WD |
399 | crc = crc32 (crc, &byte, 1); |
400 | addr++; | |
401 | } | |
e857a5bd | 402 | if (err > 0) |
4b9206ed | 403 | puts ("Error reading the chip,\n"); |
e857a5bd | 404 | else |
81a8824f | 405 | printf ("%08lx\n", crc); |
81a8824f WD |
406 | |
407 | return 0; | |
408 | } | |
409 | ||
81a8824f WD |
410 | /* Modify memory. |
411 | * | |
412 | * Syntax: | |
413 | * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} | |
414 | * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} | |
415 | */ | |
416 | ||
417 | static int | |
418 | mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) | |
419 | { | |
420 | uchar chip; | |
421 | ulong addr; | |
422 | uint alen; | |
423 | ulong data; | |
424 | int size = 1; | |
425 | int nbytes; | |
426 | int j; | |
427 | extern char console_buffer[]; | |
428 | ||
429 | if (argc != 3) { | |
62c3ae7c | 430 | cmd_usage(cmdtp); |
81a8824f WD |
431 | return 1; |
432 | } | |
433 | ||
434 | #ifdef CONFIG_BOOT_RETRY_TIME | |
435 | reset_cmd_timeout(); /* got a good command to get here */ | |
436 | #endif | |
437 | /* | |
438 | * We use the last specified parameters, unless new ones are | |
439 | * entered. | |
440 | */ | |
441 | chip = i2c_mm_last_chip; | |
442 | addr = i2c_mm_last_addr; | |
443 | alen = i2c_mm_last_alen; | |
444 | ||
445 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
446 | /* | |
447 | * New command specified. Check for a size specification. | |
448 | * Defaults to byte if no or incorrect specification. | |
449 | */ | |
450 | size = cmd_get_data_size(argv[0], 1); | |
451 | ||
452 | /* | |
53677ef1 WD |
453 | * Chip is always specified. |
454 | */ | |
81a8824f WD |
455 | chip = simple_strtoul(argv[1], NULL, 16); |
456 | ||
457 | /* | |
458 | * Address is always specified. | |
459 | */ | |
460 | addr = simple_strtoul(argv[2], NULL, 16); | |
461 | alen = 1; | |
e857a5bd | 462 | for (j = 0; j < 8; j++) { |
81a8824f WD |
463 | if (argv[2][j] == '.') { |
464 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 465 | if (alen > 4) { |
62c3ae7c | 466 | cmd_usage(cmdtp); |
81a8824f WD |
467 | return 1; |
468 | } | |
469 | break; | |
e857a5bd | 470 | } else if (argv[2][j] == '\0') |
81a8824f | 471 | break; |
81a8824f WD |
472 | } |
473 | } | |
474 | ||
475 | /* | |
476 | * Print the address, followed by value. Then accept input for | |
477 | * the next value. A non-converted value exits. | |
478 | */ | |
479 | do { | |
480 | printf("%08lx:", addr); | |
e857a5bd | 481 | if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 482 | puts ("\nError reading the chip,\n"); |
e857a5bd | 483 | else { |
81a8824f | 484 | data = cpu_to_be32(data); |
e857a5bd | 485 | if (size == 1) |
81a8824f | 486 | printf(" %02lx", (data >> 24) & 0x000000FF); |
e857a5bd | 487 | else if (size == 2) |
81a8824f | 488 | printf(" %04lx", (data >> 16) & 0x0000FFFF); |
e857a5bd | 489 | else |
81a8824f | 490 | printf(" %08lx", data); |
81a8824f WD |
491 | } |
492 | ||
493 | nbytes = readline (" ? "); | |
494 | if (nbytes == 0) { | |
495 | /* | |
496 | * <CR> pressed as only input, don't modify current | |
497 | * location and move to next. | |
498 | */ | |
499 | if (incrflag) | |
500 | addr += size; | |
501 | nbytes = size; | |
502 | #ifdef CONFIG_BOOT_RETRY_TIME | |
503 | reset_cmd_timeout(); /* good enough to not time out */ | |
504 | #endif | |
505 | } | |
506 | #ifdef CONFIG_BOOT_RETRY_TIME | |
e857a5bd | 507 | else if (nbytes == -2) |
81a8824f | 508 | break; /* timed out, exit the command */ |
81a8824f WD |
509 | #endif |
510 | else { | |
511 | char *endp; | |
512 | ||
513 | data = simple_strtoul(console_buffer, &endp, 16); | |
e857a5bd | 514 | if (size == 1) |
81a8824f | 515 | data = data << 24; |
e857a5bd | 516 | else if (size == 2) |
81a8824f | 517 | data = data << 16; |
81a8824f WD |
518 | data = be32_to_cpu(data); |
519 | nbytes = endp - console_buffer; | |
520 | if (nbytes) { | |
521 | #ifdef CONFIG_BOOT_RETRY_TIME | |
522 | /* | |
523 | * good enough to not time out | |
524 | */ | |
525 | reset_cmd_timeout(); | |
526 | #endif | |
e857a5bd | 527 | if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 528 | puts ("Error writing the chip.\n"); |
6d0f6bcf JCPV |
529 | #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS |
530 | udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); | |
2535d602 | 531 | #endif |
81a8824f WD |
532 | if (incrflag) |
533 | addr += size; | |
534 | } | |
535 | } | |
536 | } while (nbytes); | |
537 | ||
0800707b PT |
538 | i2c_mm_last_chip = chip; |
539 | i2c_mm_last_addr = addr; | |
540 | i2c_mm_last_alen = alen; | |
81a8824f WD |
541 | |
542 | return 0; | |
543 | } | |
544 | ||
545 | /* | |
546 | * Syntax: | |
547 | * iprobe {addr}{.0, .1, .2} | |
548 | */ | |
549 | int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
550 | { | |
551 | int j; | |
6d0f6bcf | 552 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 553 | int k, skip; |
bb99ad6d BW |
554 | uchar bus = GET_BUS_NUM; |
555 | #endif /* NOPROBES */ | |
81a8824f | 556 | |
4b9206ed | 557 | puts ("Valid chip addresses:"); |
e857a5bd | 558 | for (j = 0; j < 128; j++) { |
6d0f6bcf | 559 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 560 | skip = 0; |
e857a5bd TT |
561 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
562 | if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { | |
81a8824f WD |
563 | skip = 1; |
564 | break; | |
565 | } | |
566 | } | |
567 | if (skip) | |
568 | continue; | |
569 | #endif | |
e857a5bd | 570 | if (i2c_probe(j) == 0) |
81a8824f | 571 | printf(" %02X", j); |
81a8824f | 572 | } |
4b9206ed | 573 | putc ('\n'); |
81a8824f | 574 | |
6d0f6bcf | 575 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 576 | puts ("Excluded chip addresses:"); |
e857a5bd TT |
577 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
578 | if (COMPARE_BUS(bus,k)) | |
bb99ad6d BW |
579 | printf(" %02X", NO_PROBE_ADDR(k)); |
580 | } | |
4b9206ed | 581 | putc ('\n'); |
81a8824f WD |
582 | #endif |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
81a8824f WD |
587 | /* |
588 | * Syntax: | |
589 | * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] | |
590 | * {length} - Number of bytes to read | |
591 | * {delay} - A DECIMAL number and defaults to 1000 uSec | |
592 | */ | |
593 | int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
594 | { | |
595 | u_char chip; | |
596 | ulong alen; | |
597 | uint addr; | |
598 | uint length; | |
599 | u_char bytes[16]; | |
600 | int delay; | |
601 | int j; | |
602 | ||
603 | if (argc < 3) { | |
62c3ae7c | 604 | cmd_usage(cmdtp); |
81a8824f WD |
605 | return 1; |
606 | } | |
607 | ||
608 | /* | |
609 | * Chip is always specified. | |
610 | */ | |
611 | chip = simple_strtoul(argv[1], NULL, 16); | |
612 | ||
613 | /* | |
614 | * Address is always specified. | |
615 | */ | |
616 | addr = simple_strtoul(argv[2], NULL, 16); | |
617 | alen = 1; | |
e857a5bd | 618 | for (j = 0; j < 8; j++) { |
81a8824f WD |
619 | if (argv[2][j] == '.') { |
620 | alen = argv[2][j+1] - '0'; | |
621 | if (alen > 4) { | |
62c3ae7c | 622 | cmd_usage(cmdtp); |
81a8824f WD |
623 | return 1; |
624 | } | |
625 | break; | |
e857a5bd | 626 | } else if (argv[2][j] == '\0') |
81a8824f | 627 | break; |
81a8824f WD |
628 | } |
629 | ||
630 | /* | |
631 | * Length is the number of objects, not number of bytes. | |
632 | */ | |
633 | length = 1; | |
634 | length = simple_strtoul(argv[3], NULL, 16); | |
e857a5bd | 635 | if (length > sizeof(bytes)) |
81a8824f | 636 | length = sizeof(bytes); |
81a8824f WD |
637 | |
638 | /* | |
639 | * The delay time (uSec) is optional. | |
640 | */ | |
641 | delay = 1000; | |
e857a5bd | 642 | if (argc > 3) |
81a8824f | 643 | delay = simple_strtoul(argv[4], NULL, 10); |
81a8824f WD |
644 | /* |
645 | * Run the loop... | |
646 | */ | |
e857a5bd TT |
647 | while (1) { |
648 | if (i2c_read(chip, addr, alen, bytes, length) != 0) | |
4b9206ed | 649 | puts ("Error reading the chip.\n"); |
81a8824f WD |
650 | udelay(delay); |
651 | } | |
652 | ||
653 | /* NOTREACHED */ | |
654 | return 0; | |
655 | } | |
656 | ||
81a8824f WD |
657 | /* |
658 | * The SDRAM command is separately configured because many | |
659 | * (most?) embedded boards don't use SDRAM DIMMs. | |
660 | */ | |
c76fe474 | 661 | #if defined(CONFIG_CMD_SDRAM) |
632de067 LJ |
662 | static void print_ddr2_tcyc (u_char const b) |
663 | { | |
664 | printf ("%d.", (b >> 4) & 0x0F); | |
665 | switch (b & 0x0F) { | |
666 | case 0x0: | |
667 | case 0x1: | |
668 | case 0x2: | |
669 | case 0x3: | |
670 | case 0x4: | |
671 | case 0x5: | |
672 | case 0x6: | |
673 | case 0x7: | |
674 | case 0x8: | |
675 | case 0x9: | |
676 | printf ("%d ns\n", b & 0x0F); | |
677 | break; | |
678 | case 0xA: | |
679 | puts ("25 ns\n"); | |
680 | break; | |
681 | case 0xB: | |
682 | puts ("33 ns\n"); | |
683 | break; | |
684 | case 0xC: | |
685 | puts ("66 ns\n"); | |
686 | break; | |
687 | case 0xD: | |
688 | puts ("75 ns\n"); | |
689 | break; | |
690 | default: | |
691 | puts ("?? ns\n"); | |
692 | break; | |
693 | } | |
694 | } | |
695 | ||
696 | static void decode_bits (u_char const b, char const *str[], int const do_once) | |
697 | { | |
698 | u_char mask; | |
699 | ||
700 | for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) { | |
701 | if (b & mask) { | |
702 | puts (*str); | |
703 | if (do_once) | |
704 | return; | |
705 | } | |
706 | } | |
707 | } | |
81a8824f WD |
708 | |
709 | /* | |
710 | * Syntax: | |
711 | * sdram {i2c_chip} | |
712 | */ | |
632de067 | 713 | int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
81a8824f | 714 | { |
632de067 LJ |
715 | enum { unknown, EDO, SDRAM, DDR2 } type; |
716 | ||
81a8824f WD |
717 | u_char chip; |
718 | u_char data[128]; | |
719 | u_char cksum; | |
720 | int j; | |
721 | ||
632de067 LJ |
722 | static const char *decode_CAS_DDR2[] = { |
723 | " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" | |
724 | }; | |
725 | ||
726 | static const char *decode_CAS_default[] = { | |
727 | " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1" | |
728 | }; | |
729 | ||
730 | static const char *decode_CS_WE_default[] = { | |
731 | " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0" | |
732 | }; | |
733 | ||
734 | static const char *decode_byte21_default[] = { | |
735 | " TBD (bit 7)\n", | |
736 | " Redundant row address\n", | |
737 | " Differential clock input\n", | |
738 | " Registerd DQMB inputs\n", | |
739 | " Buffered DQMB inputs\n", | |
740 | " On-card PLL\n", | |
741 | " Registered address/control lines\n", | |
742 | " Buffered address/control lines\n" | |
743 | }; | |
744 | ||
745 | static const char *decode_byte22_DDR2[] = { | |
746 | " TBD (bit 7)\n", | |
747 | " TBD (bit 6)\n", | |
748 | " TBD (bit 5)\n", | |
749 | " TBD (bit 4)\n", | |
750 | " TBD (bit 3)\n", | |
751 | " Supports partial array self refresh\n", | |
752 | " Supports 50 ohm ODT\n", | |
753 | " Supports weak driver\n" | |
754 | }; | |
755 | ||
756 | static const char *decode_row_density_DDR2[] = { | |
757 | "512 MiB", "256 MiB", "128 MiB", "16 GiB", | |
758 | "8 GiB", "4 GiB", "2 GiB", "1 GiB" | |
759 | }; | |
760 | ||
761 | static const char *decode_row_density_default[] = { | |
762 | "512 MiB", "256 MiB", "128 MiB", "64 MiB", | |
763 | "32 MiB", "16 MiB", "8 MiB", "4 MiB" | |
764 | }; | |
765 | ||
81a8824f | 766 | if (argc < 2) { |
62c3ae7c | 767 | cmd_usage(cmdtp); |
81a8824f WD |
768 | return 1; |
769 | } | |
770 | /* | |
771 | * Chip is always specified. | |
632de067 LJ |
772 | */ |
773 | chip = simple_strtoul (argv[1], NULL, 16); | |
81a8824f | 774 | |
632de067 | 775 | if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { |
4b9206ed | 776 | puts ("No SDRAM Serial Presence Detect found.\n"); |
81a8824f WD |
777 | return 1; |
778 | } | |
779 | ||
780 | cksum = 0; | |
781 | for (j = 0; j < 63; j++) { | |
782 | cksum += data[j]; | |
783 | } | |
e857a5bd | 784 | if (cksum != data[63]) { |
81a8824f | 785 | printf ("WARNING: Configuration data checksum failure:\n" |
632de067 | 786 | " is 0x%02x, calculated 0x%02x\n", data[63], cksum); |
81a8824f | 787 | } |
632de067 | 788 | printf ("SPD data revision %d.%d\n", |
81a8824f | 789 | (data[62] >> 4) & 0x0F, data[62] & 0x0F); |
632de067 LJ |
790 | printf ("Bytes used 0x%02X\n", data[0]); |
791 | printf ("Serial memory size 0x%02X\n", 1 << data[1]); | |
792 | ||
4b9206ed | 793 | puts ("Memory type "); |
632de067 | 794 | switch (data[2]) { |
0df6b844 LJ |
795 | case 2: |
796 | type = EDO; | |
797 | puts ("EDO\n"); | |
798 | break; | |
799 | case 4: | |
800 | type = SDRAM; | |
801 | puts ("SDRAM\n"); | |
802 | break; | |
803 | case 8: | |
804 | type = DDR2; | |
805 | puts ("DDR2\n"); | |
806 | break; | |
807 | default: | |
808 | type = unknown; | |
809 | puts ("unknown\n"); | |
810 | break; | |
81a8824f | 811 | } |
632de067 | 812 | |
4b9206ed | 813 | puts ("Row address bits "); |
e857a5bd | 814 | if ((data[3] & 0x00F0) == 0) |
632de067 | 815 | printf ("%d\n", data[3] & 0x0F); |
e857a5bd | 816 | else |
632de067 LJ |
817 | printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); |
818 | ||
4b9206ed | 819 | puts ("Column address bits "); |
e857a5bd | 820 | if ((data[4] & 0x00F0) == 0) |
632de067 | 821 | printf ("%d\n", data[4] & 0x0F); |
e857a5bd | 822 | else |
632de067 | 823 | printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); |
0df6b844 LJ |
824 | |
825 | switch (type) { | |
826 | case DDR2: | |
632de067 LJ |
827 | printf ("Number of ranks %d\n", |
828 | (data[5] & 0x07) + 1); | |
0df6b844 LJ |
829 | break; |
830 | default: | |
632de067 | 831 | printf ("Module rows %d\n", data[5]); |
0df6b844 LJ |
832 | break; |
833 | } | |
834 | ||
835 | switch (type) { | |
836 | case DDR2: | |
632de067 | 837 | printf ("Module data width %d bits\n", data[6]); |
0df6b844 LJ |
838 | break; |
839 | default: | |
632de067 LJ |
840 | printf ("Module data width %d bits\n", |
841 | (data[7] << 8) | data[6]); | |
0df6b844 LJ |
842 | break; |
843 | } | |
844 | ||
4b9206ed | 845 | puts ("Interface signal levels "); |
81a8824f | 846 | switch(data[8]) { |
0df6b844 | 847 | case 0: puts ("TTL 5.0 V\n"); break; |
4b9206ed | 848 | case 1: puts ("LVTTL\n"); break; |
0df6b844 LJ |
849 | case 2: puts ("HSTL 1.5 V\n"); break; |
850 | case 3: puts ("SSTL 3.3 V\n"); break; | |
851 | case 4: puts ("SSTL 2.5 V\n"); break; | |
852 | case 5: puts ("SSTL 1.8 V\n"); break; | |
4b9206ed | 853 | default: puts ("unknown\n"); break; |
81a8824f | 854 | } |
0df6b844 LJ |
855 | |
856 | switch (type) { | |
857 | case DDR2: | |
632de067 LJ |
858 | printf ("SDRAM cycle time "); |
859 | print_ddr2_tcyc (data[9]); | |
0df6b844 LJ |
860 | break; |
861 | default: | |
632de067 LJ |
862 | printf ("SDRAM cycle time %d.%d ns\n", |
863 | (data[9] >> 4) & 0x0F, data[9] & 0x0F); | |
0df6b844 LJ |
864 | break; |
865 | } | |
866 | ||
867 | switch (type) { | |
868 | case DDR2: | |
632de067 LJ |
869 | printf ("SDRAM access time 0.%d%d ns\n", |
870 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
871 | break; |
872 | default: | |
632de067 LJ |
873 | printf ("SDRAM access time %d.%d ns\n", |
874 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
875 | break; |
876 | } | |
877 | ||
4b9206ed | 878 | puts ("EDC configuration "); |
632de067 | 879 | switch (data[11]) { |
4b9206ed WD |
880 | case 0: puts ("None\n"); break; |
881 | case 1: puts ("Parity\n"); break; | |
882 | case 2: puts ("ECC\n"); break; | |
883 | default: puts ("unknown\n"); break; | |
81a8824f | 884 | } |
632de067 | 885 | |
e857a5bd | 886 | if ((data[12] & 0x80) == 0) |
4b9206ed | 887 | puts ("No self refresh, rate "); |
e857a5bd | 888 | else |
4b9206ed | 889 | puts ("Self refresh, rate "); |
632de067 | 890 | |
81a8824f | 891 | switch(data[12] & 0x7F) { |
632de067 LJ |
892 | case 0: puts ("15.625 us\n"); break; |
893 | case 1: puts ("3.9 us\n"); break; | |
894 | case 2: puts ("7.8 us\n"); break; | |
895 | case 3: puts ("31.3 us\n"); break; | |
896 | case 4: puts ("62.5 us\n"); break; | |
897 | case 5: puts ("125 us\n"); break; | |
4b9206ed | 898 | default: puts ("unknown\n"); break; |
81a8824f | 899 | } |
0df6b844 LJ |
900 | |
901 | switch (type) { | |
902 | case DDR2: | |
632de067 | 903 | printf ("SDRAM width (primary) %d\n", data[13]); |
0df6b844 LJ |
904 | break; |
905 | default: | |
632de067 | 906 | printf ("SDRAM width (primary) %d\n", data[13] & 0x7F); |
0df6b844 | 907 | if ((data[13] & 0x80) != 0) { |
632de067 LJ |
908 | printf (" (second bank) %d\n", |
909 | 2 * (data[13] & 0x7F)); | |
0df6b844 LJ |
910 | } |
911 | break; | |
912 | } | |
913 | ||
914 | switch (type) { | |
915 | case DDR2: | |
916 | if (data[14] != 0) | |
632de067 | 917 | printf ("EDC width %d\n", data[14]); |
0df6b844 LJ |
918 | break; |
919 | default: | |
920 | if (data[14] != 0) { | |
632de067 LJ |
921 | printf ("EDC width %d\n", |
922 | data[14] & 0x7F); | |
0df6b844 LJ |
923 | |
924 | if ((data[14] & 0x80) != 0) { | |
632de067 LJ |
925 | printf (" (second bank) %d\n", |
926 | 2 * (data[14] & 0x7F)); | |
0df6b844 LJ |
927 | } |
928 | } | |
929 | break; | |
81a8824f | 930 | } |
0df6b844 | 931 | |
632de067 LJ |
932 | if (DDR2 != type) { |
933 | printf ("Min clock delay, back-to-back random column addresses " | |
934 | "%d\n", data[15]); | |
0df6b844 LJ |
935 | } |
936 | ||
4b9206ed WD |
937 | puts ("Burst length(s) "); |
938 | if (data[16] & 0x80) puts (" Page"); | |
939 | if (data[16] & 0x08) puts (" 8"); | |
940 | if (data[16] & 0x04) puts (" 4"); | |
941 | if (data[16] & 0x02) puts (" 2"); | |
942 | if (data[16] & 0x01) puts (" 1"); | |
943 | putc ('\n'); | |
632de067 | 944 | printf ("Number of banks %d\n", data[17]); |
0df6b844 LJ |
945 | |
946 | switch (type) { | |
947 | case DDR2: | |
948 | puts ("CAS latency(s) "); | |
632de067 | 949 | decode_bits (data[18], decode_CAS_DDR2, 0); |
0df6b844 LJ |
950 | putc ('\n'); |
951 | break; | |
952 | default: | |
953 | puts ("CAS latency(s) "); | |
632de067 | 954 | decode_bits (data[18], decode_CAS_default, 0); |
0df6b844 LJ |
955 | putc ('\n'); |
956 | break; | |
957 | } | |
958 | ||
959 | if (DDR2 != type) { | |
960 | puts ("CS latency(s) "); | |
632de067 | 961 | decode_bits (data[19], decode_CS_WE_default, 0); |
0df6b844 LJ |
962 | putc ('\n'); |
963 | } | |
964 | ||
965 | if (DDR2 != type) { | |
966 | puts ("WE latency(s) "); | |
632de067 | 967 | decode_bits (data[20], decode_CS_WE_default, 0); |
0df6b844 LJ |
968 | putc ('\n'); |
969 | } | |
970 | ||
971 | switch (type) { | |
972 | case DDR2: | |
973 | puts ("Module attributes:\n"); | |
974 | if (data[21] & 0x80) | |
975 | puts (" TBD (bit 7)\n"); | |
976 | if (data[21] & 0x40) | |
977 | puts (" Analysis probe installed\n"); | |
978 | if (data[21] & 0x20) | |
979 | puts (" TBD (bit 5)\n"); | |
980 | if (data[21] & 0x10) | |
981 | puts (" FET switch external enable\n"); | |
632de067 | 982 | printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); |
0df6b844 | 983 | if (data[20] & 0x11) { |
632de067 LJ |
984 | printf (" %d active registers on DIMM\n", |
985 | (data[21] & 0x03) + 1); | |
0df6b844 LJ |
986 | } |
987 | break; | |
988 | default: | |
989 | puts ("Module attributes:\n"); | |
990 | if (!data[21]) | |
991 | puts (" (none)\n"); | |
632de067 LJ |
992 | else |
993 | decode_bits (data[21], decode_byte21_default, 0); | |
0df6b844 LJ |
994 | break; |
995 | } | |
996 | ||
997 | switch (type) { | |
998 | case DDR2: | |
632de067 | 999 | decode_bits (data[22], decode_byte22_DDR2, 0); |
0df6b844 LJ |
1000 | break; |
1001 | default: | |
1002 | puts ("Device attributes:\n"); | |
1003 | if (data[22] & 0x80) puts (" TBD (bit 7)\n"); | |
1004 | if (data[22] & 0x40) puts (" TBD (bit 6)\n"); | |
1005 | if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); | |
1006 | else puts (" Upper Vcc tolerance 10%\n"); | |
1007 | if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); | |
1008 | else puts (" Lower Vcc tolerance 10%\n"); | |
1009 | if (data[22] & 0x08) puts (" Supports write1/read burst\n"); | |
1010 | if (data[22] & 0x04) puts (" Supports precharge all\n"); | |
1011 | if (data[22] & 0x02) puts (" Supports auto precharge\n"); | |
1012 | if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); | |
1013 | break; | |
1014 | } | |
1015 | ||
1016 | switch (type) { | |
1017 | case DDR2: | |
632de067 LJ |
1018 | printf ("SDRAM cycle time (2nd highest CAS latency) "); |
1019 | print_ddr2_tcyc (data[23]); | |
0df6b844 LJ |
1020 | break; |
1021 | default: | |
632de067 LJ |
1022 | printf ("SDRAM cycle time (2nd highest CAS latency) %d." |
1023 | "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); | |
0df6b844 LJ |
1024 | break; |
1025 | } | |
1026 | ||
1027 | switch (type) { | |
1028 | case DDR2: | |
632de067 LJ |
1029 | printf ("SDRAM access from clock (2nd highest CAS latency) 0." |
1030 | "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1031 | break; |
1032 | default: | |
632de067 LJ |
1033 | printf ("SDRAM access from clock (2nd highest CAS latency) %d." |
1034 | "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1035 | break; |
1036 | } | |
1037 | ||
1038 | switch (type) { | |
1039 | case DDR2: | |
632de067 LJ |
1040 | printf ("SDRAM cycle time (3rd highest CAS latency) "); |
1041 | print_ddr2_tcyc (data[25]); | |
0df6b844 LJ |
1042 | break; |
1043 | default: | |
632de067 LJ |
1044 | printf ("SDRAM cycle time (3rd highest CAS latency) %d." |
1045 | "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); | |
0df6b844 LJ |
1046 | break; |
1047 | } | |
1048 | ||
1049 | switch (type) { | |
1050 | case DDR2: | |
632de067 LJ |
1051 | printf ("SDRAM access from clock (3rd highest CAS latency) 0." |
1052 | "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1053 | break; |
1054 | default: | |
632de067 LJ |
1055 | printf ("SDRAM access from clock (3rd highest CAS latency) %d." |
1056 | "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1057 | break; |
1058 | } | |
1059 | ||
1060 | switch (type) { | |
1061 | case DDR2: | |
632de067 LJ |
1062 | printf ("Minimum row precharge %d.%02d ns\n", |
1063 | (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); | |
0df6b844 LJ |
1064 | break; |
1065 | default: | |
632de067 | 1066 | printf ("Minimum row precharge %d ns\n", data[27]); |
0df6b844 LJ |
1067 | break; |
1068 | } | |
1069 | ||
1070 | switch (type) { | |
1071 | case DDR2: | |
632de067 LJ |
1072 | printf ("Row active to row active min %d.%02d ns\n", |
1073 | (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); | |
0df6b844 LJ |
1074 | break; |
1075 | default: | |
632de067 | 1076 | printf ("Row active to row active min %d ns\n", data[28]); |
0df6b844 LJ |
1077 | break; |
1078 | } | |
1079 | ||
1080 | switch (type) { | |
1081 | case DDR2: | |
632de067 LJ |
1082 | printf ("RAS to CAS delay min %d.%02d ns\n", |
1083 | (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); | |
0df6b844 LJ |
1084 | break; |
1085 | default: | |
632de067 | 1086 | printf ("RAS to CAS delay min %d ns\n", data[29]); |
0df6b844 LJ |
1087 | break; |
1088 | } | |
1089 | ||
632de067 | 1090 | printf ("Minimum RAS pulse width %d ns\n", data[30]); |
0df6b844 LJ |
1091 | |
1092 | switch (type) { | |
1093 | case DDR2: | |
632de067 LJ |
1094 | puts ("Density of each row "); |
1095 | decode_bits (data[31], decode_row_density_DDR2, 1); | |
1096 | putc ('\n'); | |
0df6b844 LJ |
1097 | break; |
1098 | default: | |
632de067 LJ |
1099 | puts ("Density of each row "); |
1100 | decode_bits (data[31], decode_row_density_default, 1); | |
1101 | putc ('\n'); | |
0df6b844 LJ |
1102 | break; |
1103 | } | |
1104 | ||
1105 | switch (type) { | |
1106 | case DDR2: | |
632de067 | 1107 | puts ("Command and Address setup "); |
0df6b844 | 1108 | if (data[32] >= 0xA0) { |
632de067 LJ |
1109 | printf ("1.%d%d ns\n", |
1110 | ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); | |
0df6b844 | 1111 | } else { |
632de067 LJ |
1112 | printf ("0.%d%d ns\n", |
1113 | ((data[32] >> 4) & 0x0F), data[32] & 0x0F); | |
0df6b844 LJ |
1114 | } |
1115 | break; | |
1116 | default: | |
632de067 LJ |
1117 | printf ("Command and Address setup %c%d.%d ns\n", |
1118 | (data[32] & 0x80) ? '-' : '+', | |
1119 | (data[32] >> 4) & 0x07, data[32] & 0x0F); | |
0df6b844 LJ |
1120 | break; |
1121 | } | |
1122 | ||
1123 | switch (type) { | |
1124 | case DDR2: | |
632de067 | 1125 | puts ("Command and Address hold "); |
0df6b844 | 1126 | if (data[33] >= 0xA0) { |
632de067 LJ |
1127 | printf ("1.%d%d ns\n", |
1128 | ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); | |
0df6b844 | 1129 | } else { |
632de067 LJ |
1130 | printf ("0.%d%d ns\n", |
1131 | ((data[33] >> 4) & 0x0F), data[33] & 0x0F); | |
0df6b844 LJ |
1132 | } |
1133 | break; | |
1134 | default: | |
632de067 LJ |
1135 | printf ("Command and Address hold %c%d.%d ns\n", |
1136 | (data[33] & 0x80) ? '-' : '+', | |
1137 | (data[33] >> 4) & 0x07, data[33] & 0x0F); | |
0df6b844 LJ |
1138 | break; |
1139 | } | |
1140 | ||
1141 | switch (type) { | |
1142 | case DDR2: | |
632de067 LJ |
1143 | printf ("Data signal input setup 0.%d%d ns\n", |
1144 | (data[34] >> 4) & 0x0F, data[34] & 0x0F); | |
0df6b844 LJ |
1145 | break; |
1146 | default: | |
632de067 LJ |
1147 | printf ("Data signal input setup %c%d.%d ns\n", |
1148 | (data[34] & 0x80) ? '-' : '+', | |
1149 | (data[34] >> 4) & 0x07, data[34] & 0x0F); | |
0df6b844 LJ |
1150 | break; |
1151 | } | |
1152 | ||
1153 | switch (type) { | |
1154 | case DDR2: | |
632de067 LJ |
1155 | printf ("Data signal input hold 0.%d%d ns\n", |
1156 | (data[35] >> 4) & 0x0F, data[35] & 0x0F); | |
0df6b844 LJ |
1157 | break; |
1158 | default: | |
632de067 LJ |
1159 | printf ("Data signal input hold %c%d.%d ns\n", |
1160 | (data[35] & 0x80) ? '-' : '+', | |
1161 | (data[35] >> 4) & 0x07, data[35] & 0x0F); | |
0df6b844 LJ |
1162 | break; |
1163 | } | |
1164 | ||
4b9206ed | 1165 | puts ("Manufacturer's JEDEC ID "); |
e857a5bd | 1166 | for (j = 64; j <= 71; j++) |
632de067 | 1167 | printf ("%02X ", data[j]); |
4b9206ed | 1168 | putc ('\n'); |
632de067 | 1169 | printf ("Manufacturing Location %02X\n", data[72]); |
4b9206ed | 1170 | puts ("Manufacturer's Part Number "); |
e857a5bd | 1171 | for (j = 73; j <= 90; j++) |
632de067 | 1172 | printf ("%02X ", data[j]); |
4b9206ed | 1173 | putc ('\n'); |
632de067 LJ |
1174 | printf ("Revision Code %02X %02X\n", data[91], data[92]); |
1175 | printf ("Manufacturing Date %02X %02X\n", data[93], data[94]); | |
4b9206ed | 1176 | puts ("Assembly Serial Number "); |
e857a5bd | 1177 | for (j = 95; j <= 98; j++) |
632de067 | 1178 | printf ("%02X ", data[j]); |
4b9206ed | 1179 | putc ('\n'); |
81a8824f | 1180 | |
0df6b844 | 1181 | if (DDR2 != type) { |
632de067 LJ |
1182 | printf ("Speed rating PC%d\n", |
1183 | data[126] == 0x66 ? 66 : data[126]); | |
0df6b844 | 1184 | } |
81a8824f WD |
1185 | return 0; |
1186 | } | |
90253178 | 1187 | #endif |
81a8824f | 1188 | |
bb99ad6d | 1189 | #if defined(CONFIG_I2C_CMD_TREE) |
e43a27c4 HS |
1190 | int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
1191 | { | |
6d0f6bcf | 1192 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
e43a27c4 HS |
1193 | return 0; |
1194 | } | |
1195 | ||
67b23a32 HS |
1196 | #if defined(CONFIG_I2C_MUX) |
1197 | int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1198 | { | |
1199 | int ret=0; | |
1200 | ||
1201 | if (argc == 1) { | |
1202 | /* show all busses */ | |
1203 | I2C_MUX *mux; | |
1204 | I2C_MUX_DEVICE *device = i2c_mux_devices; | |
1205 | ||
1206 | printf ("Busses reached over muxes:\n"); | |
1207 | while (device != NULL) { | |
1208 | printf ("Bus ID: %x\n", device->busid); | |
1209 | printf (" reached over Mux(es):\n"); | |
1210 | mux = device->mux; | |
1211 | while (mux != NULL) { | |
1212 | printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel); | |
1213 | mux = mux->next; | |
1214 | } | |
1215 | device = device->next; | |
1216 | } | |
1217 | } else { | |
1218 | I2C_MUX_DEVICE *dev; | |
1219 | ||
1220 | dev = i2c_mux_ident_muxstring ((uchar *)argv[1]); | |
1221 | ret = 0; | |
1222 | } | |
1223 | return ret; | |
1224 | } | |
1225 | #endif /* CONFIG_I2C_MUX */ | |
1226 | ||
bb99ad6d BW |
1227 | #if defined(CONFIG_I2C_MULTI_BUS) |
1228 | int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1229 | { | |
1230 | int bus_idx, ret=0; | |
1231 | ||
e857a5bd TT |
1232 | if (argc == 1) |
1233 | /* querying current setting */ | |
bb99ad6d | 1234 | printf("Current bus is %d\n", i2c_get_bus_num()); |
e857a5bd | 1235 | else { |
bb99ad6d BW |
1236 | bus_idx = simple_strtoul(argv[1], NULL, 10); |
1237 | printf("Setting bus to %d\n", bus_idx); | |
1238 | ret = i2c_set_bus_num(bus_idx); | |
e857a5bd | 1239 | if (ret) |
bb99ad6d | 1240 | printf("Failure changing bus number (%d)\n", ret); |
bb99ad6d BW |
1241 | } |
1242 | return ret; | |
1243 | } | |
1244 | #endif /* CONFIG_I2C_MULTI_BUS */ | |
1245 | ||
1246 | int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1247 | { | |
1248 | int speed, ret=0; | |
1249 | ||
e857a5bd TT |
1250 | if (argc == 1) |
1251 | /* querying current speed */ | |
bb99ad6d | 1252 | printf("Current bus speed=%d\n", i2c_get_bus_speed()); |
e857a5bd | 1253 | else { |
bb99ad6d BW |
1254 | speed = simple_strtoul(argv[1], NULL, 10); |
1255 | printf("Setting bus speed to %d Hz\n", speed); | |
1256 | ret = i2c_set_bus_speed(speed); | |
e857a5bd | 1257 | if (ret) |
bb99ad6d | 1258 | printf("Failure changing bus speed (%d)\n", ret); |
bb99ad6d BW |
1259 | } |
1260 | return ret; | |
1261 | } | |
1262 | ||
1263 | int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1264 | { | |
67b23a32 HS |
1265 | #if defined(CONFIG_I2C_MUX) |
1266 | if (!strncmp(argv[1], "bu", 2)) | |
1267 | return do_i2c_add_bus(cmdtp, flag, --argc, ++argv); | |
1268 | #endif /* CONFIG_I2C_MUX */ | |
9bc2e4ee PT |
1269 | if (!strncmp(argv[1], "sp", 2)) |
1270 | return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv); | |
bb99ad6d | 1271 | #if defined(CONFIG_I2C_MULTI_BUS) |
e857a5bd | 1272 | if (!strncmp(argv[1], "de", 2)) |
bb99ad6d | 1273 | return do_i2c_bus_num(cmdtp, flag, --argc, ++argv); |
bb99ad6d | 1274 | #endif /* CONFIG_I2C_MULTI_BUS */ |
e857a5bd | 1275 | if (!strncmp(argv[1], "md", 2)) |
bb99ad6d | 1276 | return do_i2c_md(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1277 | if (!strncmp(argv[1], "mm", 2)) |
bb99ad6d | 1278 | return do_i2c_mm(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1279 | if (!strncmp(argv[1], "mw", 2)) |
bb99ad6d | 1280 | return do_i2c_mw(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1281 | if (!strncmp(argv[1], "nm", 2)) |
bb99ad6d | 1282 | return do_i2c_nm(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1283 | if (!strncmp(argv[1], "cr", 2)) |
bb99ad6d | 1284 | return do_i2c_crc(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1285 | if (!strncmp(argv[1], "pr", 2)) |
bb99ad6d | 1286 | return do_i2c_probe(cmdtp, flag, --argc, ++argv); |
e43a27c4 HS |
1287 | if (!strncmp(argv[1], "re", 2)) |
1288 | return do_i2c_reset(cmdtp, flag, --argc, ++argv); | |
e857a5bd | 1289 | if (!strncmp(argv[1], "lo", 2)) |
bb99ad6d | 1290 | return do_i2c_loop(cmdtp, flag, --argc, ++argv); |
c76fe474 | 1291 | #if defined(CONFIG_CMD_SDRAM) |
e857a5bd | 1292 | if (!strncmp(argv[1], "sd", 2)) |
bb99ad6d | 1293 | return do_sdram(cmdtp, flag, --argc, ++argv); |
90253178 | 1294 | #endif |
bb99ad6d | 1295 | else |
62c3ae7c | 1296 | cmd_usage(cmdtp); |
bb99ad6d BW |
1297 | return 0; |
1298 | } | |
1299 | #endif /* CONFIG_I2C_CMD_TREE */ | |
8bde7f77 WD |
1300 | |
1301 | /***************************************************/ | |
1302 | ||
d9fc7032 MF |
1303 | #if defined(CONFIG_I2C_CMD_TREE) |
1304 | U_BOOT_CMD( | |
1305 | i2c, 6, 1, do_i2c, | |
53677ef1 | 1306 | "i2c - I2C sub-system\n", |
67b23a32 HS |
1307 | #if defined(CONFIG_I2C_MUX) |
1308 | "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.\n" | |
1309 | #endif /* CONFIG_I2C_MUX */ | |
9bc2e4ee | 1310 | "speed [speed] - show or set I2C bus speed\n" |
d9fc7032 | 1311 | #if defined(CONFIG_I2C_MULTI_BUS) |
9bc2e4ee | 1312 | "i2c dev [dev] - show or set current I2C bus\n" |
d9fc7032 | 1313 | #endif /* CONFIG_I2C_MULTI_BUS */ |
d9fc7032 MF |
1314 | "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" |
1315 | "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" | |
1316 | "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" | |
1317 | "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" | |
1318 | "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" | |
1319 | "i2c probe - show devices on the I2C bus\n" | |
e43a27c4 | 1320 | "i2c reset - re-init the I2C Controller\n" |
d9fc7032 | 1321 | "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" |
c76fe474 | 1322 | #if defined(CONFIG_CMD_SDRAM) |
d9fc7032 | 1323 | "i2c sdram chip - print SDRAM configuration information\n" |
90253178 | 1324 | #endif |
d9fc7032 | 1325 | ); |
0c75c9d8 | 1326 | #endif /* CONFIG_I2C_CMD_TREE */ |
0d498393 WD |
1327 | U_BOOT_CMD( |
1328 | imd, 4, 1, do_i2c_md, \ | |
8bde7f77 WD |
1329 | "imd - i2c memory display\n", \ |
1330 | "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ | |
1331 | ); | |
1332 | ||
0d498393 | 1333 | U_BOOT_CMD( |
53677ef1 | 1334 | imm, 3, 1, do_i2c_mm, |
8bde7f77 WD |
1335 | "imm - i2c memory modify (auto-incrementing)\n", |
1336 | "chip address[.0, .1, .2]\n" | |
1337 | " - memory modify, auto increment address\n" | |
1338 | ); | |
0d498393 WD |
1339 | U_BOOT_CMD( |
1340 | inm, 3, 1, do_i2c_nm, | |
8bde7f77 WD |
1341 | "inm - memory modify (constant address)\n", |
1342 | "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" | |
1343 | ); | |
1344 | ||
0d498393 WD |
1345 | U_BOOT_CMD( |
1346 | imw, 5, 1, do_i2c_mw, | |
8bde7f77 WD |
1347 | "imw - memory write (fill)\n", |
1348 | "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" | |
1349 | ); | |
1350 | ||
0d498393 WD |
1351 | U_BOOT_CMD( |
1352 | icrc32, 5, 1, do_i2c_crc, | |
8bde7f77 WD |
1353 | "icrc32 - checksum calculation\n", |
1354 | "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" | |
1355 | ); | |
1356 | ||
0d498393 WD |
1357 | U_BOOT_CMD( |
1358 | iprobe, 1, 1, do_i2c_probe, | |
8bde7f77 WD |
1359 | "iprobe - probe to discover valid I2C chip addresses\n", |
1360 | "\n -discover valid I2C chip addresses\n" | |
1361 | ); | |
1362 | ||
1363 | /* | |
1364 | * Require full name for "iloop" because it is an infinite loop! | |
1365 | */ | |
0d498393 WD |
1366 | U_BOOT_CMD( |
1367 | iloop, 5, 1, do_i2c_loop, | |
8bde7f77 WD |
1368 | "iloop - infinite loop on address range\n", |
1369 | "chip address[.0, .1, .2] [# of objects]\n" | |
1370 | " - loop, reading a set of addresses\n" | |
1371 | ); | |
1372 | ||
c76fe474 | 1373 | #if defined(CONFIG_CMD_SDRAM) |
0d498393 WD |
1374 | U_BOOT_CMD( |
1375 | isdram, 2, 1, do_sdram, | |
8bde7f77 WD |
1376 | "isdram - print SDRAM configuration information\n", |
1377 | "chip\n - print SDRAM configuration information\n" | |
1378 | " (valid chip values 50..57)\n" | |
1379 | ); | |
1380 | #endif | |
67b23a32 HS |
1381 | |
1382 | #if defined(CONFIG_I2C_MUX) | |
1383 | ||
1384 | int i2c_mux_add_device(I2C_MUX_DEVICE *dev) | |
1385 | { | |
1386 | I2C_MUX_DEVICE *devtmp = i2c_mux_devices; | |
1387 | ||
1388 | if (i2c_mux_devices == NULL) { | |
1389 | i2c_mux_devices = dev; | |
1390 | return 0; | |
1391 | } | |
1392 | while (devtmp->next != NULL) | |
1393 | devtmp = devtmp->next; | |
1394 | ||
1395 | devtmp->next = dev; | |
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | I2C_MUX_DEVICE *i2c_mux_search_device(int id) | |
1400 | { | |
1401 | I2C_MUX_DEVICE *device = i2c_mux_devices; | |
1402 | ||
1403 | while (device != NULL) { | |
1404 | if (device->busid == id) | |
1405 | return device; | |
1406 | device = device->next; | |
1407 | } | |
1408 | return NULL; | |
1409 | } | |
1410 | ||
1411 | /* searches in the buf from *pos the next ':'. | |
1412 | * returns: | |
1413 | * 0 if found (with *pos = where) | |
1414 | * < 0 if an error occured | |
1415 | * > 0 if the end of buf is reached | |
1416 | */ | |
1417 | static int i2c_mux_search_next (int *pos, uchar *buf, int len) | |
1418 | { | |
1419 | while ((buf[*pos] != ':') && (*pos < len)) { | |
1420 | *pos += 1; | |
1421 | } | |
1422 | if (*pos >= len) | |
1423 | return 1; | |
1424 | if (buf[*pos] != ':') | |
1425 | return -1; | |
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | static int i2c_mux_get_busid (void) | |
1430 | { | |
1431 | int tmp = i2c_mux_busid; | |
1432 | ||
1433 | i2c_mux_busid ++; | |
1434 | return tmp; | |
1435 | } | |
1436 | ||
1437 | /* Analyses a Muxstring and sends immediately the | |
1438 | Commands to the Muxes. Runs from Flash. | |
1439 | */ | |
1440 | int i2c_mux_ident_muxstring_f (uchar *buf) | |
1441 | { | |
1442 | int pos = 0; | |
1443 | int oldpos; | |
1444 | int ret = 0; | |
1445 | int len = strlen((char *)buf); | |
1446 | int chip; | |
1447 | uchar channel; | |
1448 | int was = 0; | |
1449 | ||
1450 | while (ret == 0) { | |
1451 | oldpos = pos; | |
1452 | /* search name */ | |
1453 | ret = i2c_mux_search_next(&pos, buf, len); | |
1454 | if (ret != 0) | |
1455 | printf ("ERROR\n"); | |
1456 | /* search address */ | |
1457 | pos ++; | |
1458 | oldpos = pos; | |
1459 | ret = i2c_mux_search_next(&pos, buf, len); | |
1460 | if (ret != 0) | |
1461 | printf ("ERROR\n"); | |
1462 | buf[pos] = 0; | |
1463 | chip = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1464 | buf[pos] = ':'; | |
1465 | /* search channel */ | |
1466 | pos ++; | |
1467 | oldpos = pos; | |
1468 | ret = i2c_mux_search_next(&pos, buf, len); | |
1469 | if (ret < 0) | |
1470 | printf ("ERROR\n"); | |
1471 | was = 0; | |
1472 | if (buf[pos] != 0) { | |
1473 | buf[pos] = 0; | |
1474 | was = 1; | |
1475 | } | |
1476 | channel = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1477 | if (was) | |
1478 | buf[pos] = ':'; | |
1479 | if (i2c_write(chip, 0, 0, &channel, 1) != 0) { | |
1480 | printf ("Error setting Mux: chip:%x channel: \ | |
1481 | %x\n", chip, channel); | |
1482 | return -1; | |
1483 | } | |
1484 | pos ++; | |
1485 | oldpos = pos; | |
1486 | ||
1487 | } | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | /* Analyses a Muxstring and if this String is correct | |
1493 | * adds a new I2C Bus. | |
1494 | */ | |
1495 | I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf) | |
1496 | { | |
1497 | I2C_MUX_DEVICE *device; | |
1498 | I2C_MUX *mux; | |
1499 | int pos = 0; | |
1500 | int oldpos; | |
1501 | int ret = 0; | |
1502 | int len = strlen((char *)buf); | |
1503 | int was = 0; | |
1504 | ||
1505 | device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE)); | |
1506 | device->mux = NULL; | |
1507 | device->busid = i2c_mux_get_busid (); | |
1508 | device->next = NULL; | |
1509 | while (ret == 0) { | |
1510 | mux = (I2C_MUX *)malloc (sizeof(I2C_MUX)); | |
1511 | mux->next = NULL; | |
1512 | /* search name of mux */ | |
1513 | oldpos = pos; | |
1514 | ret = i2c_mux_search_next(&pos, buf, len); | |
1515 | if (ret != 0) | |
1516 | printf ("%s no name.\n", __FUNCTION__); | |
1517 | mux->name = (char *)malloc (pos - oldpos + 1); | |
1518 | memcpy (mux->name, &buf[oldpos], pos - oldpos); | |
1519 | mux->name[pos - oldpos] = 0; | |
1520 | /* search address */ | |
1521 | pos ++; | |
1522 | oldpos = pos; | |
1523 | ret = i2c_mux_search_next(&pos, buf, len); | |
1524 | if (ret != 0) | |
1525 | printf ("%s no mux address.\n", __FUNCTION__); | |
1526 | buf[pos] = 0; | |
1527 | mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1528 | buf[pos] = ':'; | |
1529 | /* search channel */ | |
1530 | pos ++; | |
1531 | oldpos = pos; | |
1532 | ret = i2c_mux_search_next(&pos, buf, len); | |
1533 | if (ret < 0) | |
1534 | printf ("%s no mux channel.\n", __FUNCTION__); | |
1535 | was = 0; | |
1536 | if (buf[pos] != 0) { | |
1537 | buf[pos] = 0; | |
1538 | was = 1; | |
1539 | } | |
1540 | mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1541 | if (was) | |
1542 | buf[pos] = ':'; | |
1543 | if (device->mux == NULL) | |
1544 | device->mux = mux; | |
1545 | else { | |
1546 | I2C_MUX *muxtmp = device->mux; | |
1547 | while (muxtmp->next != NULL) { | |
1548 | muxtmp = muxtmp->next; | |
1549 | } | |
1550 | muxtmp->next = mux; | |
1551 | } | |
1552 | pos ++; | |
1553 | oldpos = pos; | |
1554 | } | |
1555 | if (ret > 0) { | |
1556 | /* Add Device */ | |
1557 | i2c_mux_add_device (device); | |
1558 | return device; | |
1559 | } | |
1560 | ||
1561 | return NULL; | |
1562 | } | |
1563 | ||
1564 | int i2x_mux_select_mux(int bus) | |
1565 | { | |
1566 | I2C_MUX_DEVICE *dev; | |
1567 | I2C_MUX *mux; | |
1568 | ||
1569 | if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) { | |
1570 | /* select Default Mux Bus */ | |
6d0f6bcf JCPV |
1571 | #if defined(CONFIG_SYS_I2C_IVM_BUS) |
1572 | i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS); | |
67b23a32 HS |
1573 | #else |
1574 | { | |
1575 | unsigned char *buf; | |
1576 | buf = (unsigned char *) getenv("EEprom_ivm"); | |
1577 | if (buf != NULL) | |
1578 | i2c_mux_ident_muxstring_f (buf); | |
1579 | } | |
1580 | #endif | |
1581 | return 0; | |
1582 | } | |
1583 | dev = i2c_mux_search_device(bus); | |
1584 | if (dev == NULL) | |
1585 | return -1; | |
1586 | ||
1587 | mux = dev->mux; | |
1588 | while (mux != NULL) { | |
1589 | if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) { | |
1590 | printf ("Error setting Mux: chip:%x channel: \ | |
1591 | %x\n", mux->chip, mux->channel); | |
1592 | return -1; | |
1593 | } | |
1594 | mux = mux->next; | |
1595 | } | |
1596 | return 0; | |
1597 | } | |
1598 | #endif /* CONFIG_I2C_MUX */ |