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ec2b74ff 1/*
0e870980 2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
ec2b74ff 3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
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5 */
6
7#include <common.h>
8#include <command.h>
9
088f1b19 10static int
54841ab5 11cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ec2b74ff 12{
79679d80 13 unsigned long cpuid;
ec2b74ff 14
47e26b1b 15 if (argc < 3)
4c12eeb8 16 return CMD_RET_USAGE;
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17
18 cpuid = simple_strtoul(argv[1], NULL, 10);
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19 if (!is_core_valid(cpuid)) {
20 printf ("Core num: %lu is not valid\n", cpuid);
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21 return 1;
22 }
23
24
25 if (argc == 3) {
47e26b1b 26 if (strncmp(argv[2], "reset", 5) == 0)
ec2b74ff 27 cpu_reset(cpuid);
47e26b1b 28 else if (strncmp(argv[2], "status", 6) == 0)
ec2b74ff 29 cpu_status(cpuid);
47e26b1b 30 else if (strncmp(argv[2], "disable", 7) == 0)
4194b366 31 return cpu_disable(cpuid);
47e26b1b 32 else
4c12eeb8 33 return CMD_RET_USAGE;
47e26b1b 34
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35 return 0;
36 }
37
38 /* 4 or greater, make sure its release */
47e26b1b 39 if (strncmp(argv[2], "release", 7) != 0)
4c12eeb8 40 return CMD_RET_USAGE;
ec2b74ff 41
47e26b1b 42 if (cpu_release(cpuid, argc - 3, argv + 3))
4c12eeb8 43 return CMD_RET_USAGE;
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44
45 return 0;
46}
47
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48#ifdef CONFIG_SYS_LONGHELP
49static char cpu_help_text[] =
50 "<num> reset - Reset cpu <num>\n"
51 "cpu <num> status - Status of cpu <num>\n"
52 "cpu <num> disable - Disable cpu <num>\n"
53 "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
ec2b74ff 54#ifdef CONFIG_PPC
088f1b19 55 "\n"
79679d80 56 " [args] : <pir> <r3> <r6>\n" \
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57 " pir - processor id (if writeable)\n" \
58 " r3 - value for gpr 3\n" \
ec2b74ff 59 " r6 - value for gpr 6\n" \
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60 "\n" \
61 " Use '-' for any arg if you want the default value.\n" \
79679d80 62 " Default for r3 is <num> and r6 is 0\n" \
ec2b74ff 63 "\n" \
79679d80 64 " When cpu <num> is released r4 and r5 = 0.\n" \
a89c33db 65 " r7 will contain the size of the initial mapped area"
ec2b74ff 66#endif
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67 "";
68#endif
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69
70U_BOOT_CMD(
6d0f6bcf 71 cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd,
088f1b19 72 "Multiprocessor CPU boot manipulation and release", cpu_help_text
a89c33db 73);