]> git.ipfire.org Git - people/ms/u-boot.git/blame - common/cmd_mp.c
Add support to disable cpu's in multicore processors
[people/ms/u-boot.git] / common / cmd_mp.c
CommitLineData
ec2b74ff 1/*
0e870980 2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
ec2b74ff
KG
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <command.h>
25
26int
27cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
28{
79679d80 29 unsigned long cpuid;
ec2b74ff
KG
30
31 if (argc < 3) {
62c3ae7c 32 cmd_usage(cmdtp);
ec2b74ff
KG
33 return 1;
34 }
35
36 cpuid = simple_strtoul(argv[1], NULL, 10);
0e870980 37 if (cpuid >= cpu_numcores()) {
348753d4 38 printf ("Core num: %lu is out of range[0..%d]\n",
0e870980 39 cpuid, cpu_numcores() - 1);
ec2b74ff
KG
40 return 1;
41 }
42
43
44 if (argc == 3) {
45 if (strncmp(argv[2], "reset", 5) == 0) {
46 cpu_reset(cpuid);
47 } else if (strncmp(argv[2], "status", 6) == 0) {
48 cpu_status(cpuid);
4194b366
KG
49 } else if (strncmp(argv[2], "disable", 7) == 0) {
50 return cpu_disable(cpuid);
ec2b74ff 51 } else {
62c3ae7c 52 cmd_usage(cmdtp);
ec2b74ff
KG
53 return 1;
54 }
55 return 0;
56 }
57
58 /* 4 or greater, make sure its release */
59 if (strncmp(argv[2], "release", 7) != 0) {
62c3ae7c 60 cmd_usage(cmdtp);
ec2b74ff
KG
61 return 1;
62 }
63
79679d80 64 if (cpu_release(cpuid, argc - 3, argv + 3)) {
62c3ae7c 65 cmd_usage(cmdtp);
ec2b74ff
KG
66 return 1;
67 }
68
69 return 0;
70}
71
72#ifdef CONFIG_PPC
73#define CPU_ARCH_HELP \
79679d80 74 " [args] : <pir> <r3> <r6>\n" \
ec2b74ff
KG
75 " pir - processor id (if writeable)\n" \
76 " r3 - value for gpr 3\n" \
ec2b74ff 77 " r6 - value for gpr 6\n" \
ec2b74ff
KG
78 "\n" \
79 " Use '-' for any arg if you want the default value.\n" \
79679d80 80 " Default for r3 is <num> and r6 is 0\n" \
ec2b74ff 81 "\n" \
79679d80 82 " When cpu <num> is released r4 and r5 = 0.\n" \
a89c33db 83 " r7 will contain the size of the initial mapped area"
ec2b74ff
KG
84#endif
85
86U_BOOT_CMD(
6d0f6bcf 87 cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd,
2fb2604d 88 "Multiprocessor CPU boot manipulation and release",
ec2b74ff
KG
89 "<num> reset - Reset cpu <num>\n"
90 "cpu <num> status - Status of cpu <num>\n"
4194b366 91 "cpu <num> disable - Disable cpu <num>\n"
a89c33db 92 "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
ec2b74ff 93#ifdef CPU_ARCH_HELP
a89c33db 94 "\n"
ec2b74ff
KG
95 CPU_ARCH_HELP
96#endif
a89c33db 97);