* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
[people/ms/u-boot.git] / common / cmd_nand.c
CommitLineData
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1/*
2 * Driver for NAND support, Rick Bronson
3 * borrowed heavily from:
4 * (c) 1999 Machine Vision Holdings, Inc.
5 * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
6 *
7 */
8
9#include <common.h>
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10#include <command.h>
11#include <malloc.h>
12#include <asm/io.h>
13
14#ifdef CONFIG_SHOW_BOOT_PROGRESS
15# include <status_led.h>
16# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
17#else
18# define SHOW_BOOT_PROGRESS(arg)
19#endif
20
21#if (CONFIG_COMMANDS & CFG_CMD_NAND)
22
23#include <linux/mtd/nftl.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/nand_ids.h>
26
27/*
28 * Definition of the out of band configuration structure
29 */
30struct nand_oob_config {
31 int ecc_pos[6]; /* position of ECC bytes inside oob */
32 int badblock_pos; /* position of bad block flag inside oob -1 = inactive */
33 int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */
34} oob_config = { {0}, 0, 0};
35
36#define NAND_DEBUG
37#undef ECC_DEBUG
38#undef PSYCHO_DEBUG
39#undef NFTL_DEBUG
40
41#define CONFIG_MTD_NAND_ECC /* enable ECC */
42/* #define CONFIG_MTD_NAND_ECC_JFFS2 */
43
44/*
45 * Function Prototypes
46 */
47static void nand_print(struct nand_chip *nand);
48static int nand_rw (struct nand_chip* nand, int cmd,
49 size_t start, size_t len,
50 size_t * retlen, u_char * buf);
51static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len);
52static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
53 size_t * retlen, u_char *buf, u_char *ecc_code);
54static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
55 size_t * retlen, const u_char * buf, u_char * ecc_code);
56#ifdef CONFIG_MTD_NAND_ECC
57static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
58static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
59#endif
60
61static struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
62
63/* Current NAND Device */
64static int curr_device = -1;
65
66/* ------------------------------------------------------------------------- */
67
68int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
69{
70 int rcode = 0;
71
72 switch (argc) {
73 case 0:
74 case 1:
75 printf ("Usage:\n%s\n", cmdtp->usage);
76 return 1;
77 case 2:
78 if (strcmp(argv[1],"info") == 0) {
79 int i;
80
81 putc ('\n');
82
83 for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
84 if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
85 continue; /* list only known devices */
86 printf ("Device %d: ", i);
87 nand_print(&nand_dev_desc[i]);
88 }
89 return 0;
90
91 } else if (strcmp(argv[1],"device") == 0) {
92 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
93 puts ("\nno devices available\n");
94 return 1;
95 }
96 printf ("\nDevice %d: ", curr_device);
97 nand_print(&nand_dev_desc[curr_device]);
98 return 0;
99 }
100 printf ("Usage:\n%s\n", cmdtp->usage);
101 return 1;
102 case 3:
103 if (strcmp(argv[1],"device") == 0) {
104 int dev = (int)simple_strtoul(argv[2], NULL, 10);
105
106 printf ("\nDevice %d: ", dev);
107 if (dev >= CFG_MAX_NAND_DEVICE) {
108 puts ("unknown device\n");
109 return 1;
110 }
111 nand_print(&nand_dev_desc[dev]);
112 /*nand_print (dev);*/
113
114 if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
115 return 1;
116 }
117
118 curr_device = dev;
119
120 puts ("... is now current device\n");
121
122 return 0;
123 }
124
125 printf ("Usage:\n%s\n", cmdtp->usage);
126 return 1;
127 default:
128 /* at least 4 args */
129
130 if (strcmp(argv[1],"read") == 0 || strcmp(argv[1],"write") == 0) {
131 ulong addr = simple_strtoul(argv[2], NULL, 16);
132 ulong off = simple_strtoul(argv[3], NULL, 16);
133 ulong size = simple_strtoul(argv[4], NULL, 16);
134 int cmd = (strcmp(argv[1],"read") == 0);
135 int ret, total;
136
137 printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
138 cmd ? "read" : "write", curr_device, off, size);
139
140 ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
141 &total, (u_char*)addr);
142
143 printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write",
144 ret ? "ERROR" : "OK");
145
146 return ret;
147 } else if (strcmp(argv[1],"erase") == 0) {
148 ulong off = simple_strtoul(argv[2], NULL, 16);
149 ulong size = simple_strtoul(argv[3], NULL, 16);
150 int ret;
151
152 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
153 curr_device, off, size);
154
155 ret = nand_erase (nand_dev_desc + curr_device, off, size);
156
157 printf("%s\n", ret ? "ERROR" : "OK");
158
159 return ret;
160 } else {
161 printf ("Usage:\n%s\n", cmdtp->usage);
162 rcode = 1;
163 }
164
165 return rcode;
166 }
167}
168
169int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
170{
171 char *boot_device = NULL;
172 char *ep;
173 int dev;
174 ulong cnt;
175 ulong addr;
176 ulong offset = 0;
177 image_header_t *hdr;
178 int rcode = 0;
179 switch (argc) {
180 case 1:
181 addr = CFG_LOAD_ADDR;
182 boot_device = getenv ("bootdevice");
183 break;
184 case 2:
185 addr = simple_strtoul(argv[1], NULL, 16);
186 boot_device = getenv ("bootdevice");
187 break;
188 case 3:
189 addr = simple_strtoul(argv[1], NULL, 16);
190 boot_device = argv[2];
191 break;
192 case 4:
193 addr = simple_strtoul(argv[1], NULL, 16);
194 boot_device = argv[2];
195 offset = simple_strtoul(argv[3], NULL, 16);
196 break;
197 default:
198 printf ("Usage:\n%s\n", cmdtp->usage);
199 SHOW_BOOT_PROGRESS (-1);
200 return 1;
201 }
202
203 if (!boot_device) {
204 puts ("\n** No boot device **\n");
205 SHOW_BOOT_PROGRESS (-1);
206 return 1;
207 }
208
209 dev = simple_strtoul(boot_device, &ep, 16);
210
211 if ((dev >= CFG_MAX_NAND_DEVICE) ||
212 (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
213 printf ("\n** Device %d not available\n", dev);
214 SHOW_BOOT_PROGRESS (-1);
215 return 1;
216 }
217
218 printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
219 dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
220 offset);
221
222 if (nand_rw (nand_dev_desc + dev, 1, offset,
223 SECTORSIZE, NULL, (u_char *)addr)) {
224 printf ("** Read error on %d\n", dev);
225 SHOW_BOOT_PROGRESS (-1);
226 return 1;
227 }
228
229 hdr = (image_header_t *)addr;
230
231 if (ntohl(hdr->ih_magic) == IH_MAGIC) {
232
233 print_image_hdr (hdr);
234
235 cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
236 cnt -= SECTORSIZE;
237 } else {
238 printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
239 SHOW_BOOT_PROGRESS (-1);
240 return 1;
241 }
242
243 if (nand_rw (nand_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
244 NULL, (u_char *)(addr+SECTORSIZE))) {
245 printf ("** Read error on %d\n", dev);
246 SHOW_BOOT_PROGRESS (-1);
247 return 1;
248 }
249
250 /* Loading ok, update default load address */
251
252 load_addr = addr;
253
254 /* Check if we should attempt an auto-start */
255 if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
256 char *local_args[2];
257 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
258
259 local_args[0] = argv[0];
260 local_args[1] = NULL;
261
262 printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
263
264 do_bootm (cmdtp, 0, 1, local_args);
265 rcode = 1;
266 }
267 return rcode;
268}
269
270static int nand_rw (struct nand_chip* nand, int cmd,
271 size_t start, size_t len,
272 size_t * retlen, u_char * buf)
273{
274 int noecc, ret = 0, n, total = 0;
275 char eccbuf[6];
276
277 while(len) {
278 /* The ECC will not be calculated correctly if
279 less than 512 is written or read */
280 noecc = (start != (start | 0x1ff) + 1) || (len < 0x200);
281 if (cmd)
282 ret = nand_read_ecc(nand, start, len,
283 &n, (u_char*)buf,
284 noecc ? NULL : eccbuf);
285 else
286 ret = nand_write_ecc(nand, start, len,
287 &n, (u_char*)buf,
288 noecc ? NULL : eccbuf);
289
290 if (ret)
291 break;
292
293 start += n;
294 buf += n;
295 total += n;
296 len -= n;
297 }
298 if (retlen)
299 *retlen = total;
300
301 return ret;
302}
303
304static void nand_print(struct nand_chip *nand)
0db5bca8 305{
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306 printf("%s at 0x%lX,\n"
307 "\t %d chip%s %s, size %d MB, \n"
308 "\t total size %ld MB, sector size %ld kB\n",
309 nand->name, nand->IO_ADDR, nand->numchips,
310 nand->numchips>1 ? "s" : "", nand->chips_name,
311 1 << (nand->chipshift - 20),
312 nand->totlen >> 20, nand->erasesize >> 10);
313
314 if (nand->nftl_found) {
315 struct NFTLrecord *nftl = &nand->nftl;
316 unsigned long bin_size, flash_size;
317
318 bin_size = nftl->nb_boot_blocks * nand->erasesize;
319 flash_size = (nftl->nb_blocks - nftl->nb_boot_blocks) * nand->erasesize;
320
321 printf("\t NFTL boot record:\n"
322 "\t Binary partition: size %ld%s\n"
323 "\t Flash disk partition: size %ld%s, offset 0x%lx\n",
324 bin_size > (1 << 20) ? bin_size >> 20 : bin_size >> 10,
325 bin_size > (1 << 20) ? "MB" : "kB",
326 flash_size > (1 << 20) ? flash_size >> 20 : flash_size >> 10,
327 flash_size > (1 << 20) ? "MB" : "kB", bin_size);
328 } else {
329 puts ("\t No NFTL boot record found.\n");
330 }
331}
332
333/* ------------------------------------------------------------------------- */
334
335/* This function is needed to avoid calls of the __ashrdi3 function. */
0db5bca8 336#if 0
dc7c9a1a 337static int shr(int val, int shift)
0db5bca8 338{
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339 return val >> shift;
340}
0db5bca8 341#endif
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342static int NanD_WaitReady(struct nand_chip *nand)
343{
344 /* This is inline, to optimise the common case, where it's ready instantly */
345 int ret = 0;
0db5bca8 346 NAND_WAIT_READY(nand);
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347
348 return ret;
349}
350
351/* NanD_Command: Send a flash command to the flash chip */
352
353static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
354{
355 unsigned long nandptr = nand->IO_ADDR;
356
357 /* Assert the CLE (Command Latch Enable) line to the flash chip */
358 NAND_CTL_SETCLE(nandptr);
359
360 /* Send the command */
361 WRITE_NAND_COMMAND(command, nandptr);
362
363 /* Lower the CLE line */
364 NAND_CTL_CLRCLE(nandptr);
365
366 return NanD_WaitReady(nand);
367}
368
369/* NanD_Address: Set the current address for the flash chip */
370
371static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
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372{
373 unsigned long nandptr;
374 int i;
dc7c9a1a 375
0db5bca8 376 nandptr = nand->IO_ADDR;
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377
378 /* Assert the ALE (Address Latch Enable) line to the flash chip */
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379 NAND_CTL_SETALE(nandptr);
380
381 /* Send the address */
382 /* Devices with 256-byte page are addressed as:
383 * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
384 * there is no device on the market with page256
385 * and more than 24 bits.
386 * Devices with 512-byte page are addressed as:
387 * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
388 * 25-31 is sent only if the chip support it.
389 * bit 8 changes the read command to be sent
390 * (NAND_CMD_READ0 or NAND_CMD_READ1).
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391 */
392
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393 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
394 WRITE_NAND_ADDRESS(ofs, nandptr);
dc7c9a1a 395
0db5bca8 396 ofs = ofs >> nand->page_shift;
dc7c9a1a 397
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398 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
399 for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8)
400 WRITE_NAND_ADDRESS(ofs, nandptr);
dc7c9a1a 401
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402 /* Lower the ALE line */
403 NAND_CTL_CLRALE(nandptr);
dc7c9a1a 404
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405 /* Wait for the chip to respond */
406 return NanD_WaitReady(nand);
407}
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408
409/* NanD_SelectChip: Select a given flash chip within the current floor */
410
411static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
412{
413 /* Wait for it to be ready */
414 return NanD_WaitReady(nand);
415}
416
417/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
418
419static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
420{
421 int mfr, id, i;
422
0db5bca8 423 NAND_ENABLE_CE(nand); /* set pin low */
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424 /* Reset the chip */
425 if (NanD_Command(nand, NAND_CMD_RESET)) {
426#ifdef NAND_DEBUG
427 printf("NanD_Command (reset) for %d,%d returned true\n",
428 floor, chip);
429#endif
0db5bca8 430 NAND_DISABLE_CE(nand); /* set pin high */
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431 return 0;
432 }
433
434 /* Read the NAND chip ID: 1. Send ReadID command */
435 if (NanD_Command(nand, NAND_CMD_READID)) {
436#ifdef NAND_DEBUG
437 printf("NanD_Command (ReadID) for %d,%d returned true\n",
438 floor, chip);
439#endif
0db5bca8 440 NAND_DISABLE_CE(nand); /* set pin high */
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441 return 0;
442 }
443
444 /* Read the NAND chip ID: 2. Send address byte zero */
445 NanD_Address(nand, ADDR_COLUMN, 0);
446
447 /* Read the manufacturer and device id codes from the device */
448
449 mfr = READ_NAND(nand->IO_ADDR);
450
451 id = READ_NAND(nand->IO_ADDR);
452
453 NAND_DISABLE_CE(nand); /* set pin high */
454 /* No response - return failure */
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455 if (mfr == 0xff || mfr == 0) {
456 printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
457 return 0;
458 }
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459
460 /* Check it's the same as the first chip we identified.
461 * M-Systems say that any given nand_chip device should only
462 * contain _one_ type of flash part, although that's not a
463 * hardware restriction. */
464 if (nand->mfr) {
465 if (nand->mfr == mfr && nand->id == id)
466 return 1; /* This is another the same the first */
467 else
468 printf("Flash chip at floor %d, chip %d is different:\n",
469 floor, chip);
470 }
471
472 /* Print and store the manufacturer and ID codes. */
473 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
474 if (mfr == nand_flash_ids[i].manufacture_id &&
475 id == nand_flash_ids[i].model_id) {
476#ifdef NAND_DEBUG
477 printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
478 "Chip ID: 0x%2.2X (%s)\n", mfr, id,
479 nand_flash_ids[i].name);
480#endif
481 if (!nand->mfr) {
482 nand->mfr = mfr;
483 nand->id = id;
484 nand->chipshift =
485 nand_flash_ids[i].chipshift;
486 nand->page256 = nand_flash_ids[i].page256;
487 if (nand->page256) {
488 nand->oobblock = 256;
489 nand->oobsize = 8;
490 nand->page_shift = 8;
491 } else {
492 nand->oobblock = 512;
493 nand->oobsize = 16;
494 nand->page_shift = 9;
495 }
496 nand->pageadrlen =
497 nand_flash_ids[i].pageadrlen;
498 nand->erasesize =
499 nand_flash_ids[i].erasesize;
500 nand->chips_name =
501 nand_flash_ids[i].name;
502 return 1;
503 }
504 return 0;
505 }
506 }
507
508
509#ifdef NAND_DEBUG
510 /* We haven't fully identified the chip. Print as much as we know. */
511 printf("Unknown flash chip found: %2.2X %2.2X\n",
512 id, mfr);
513#endif
514
515 return 0;
516}
517
518/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
519
520static void NanD_ScanChips(struct nand_chip *nand)
521{
522 int floor, chip;
523 int numchips[NAND_MAX_FLOORS];
524 int maxchips = NAND_MAX_CHIPS;
525 int ret = 1;
526
527 nand->numchips = 0;
528 nand->mfr = 0;
529 nand->id = 0;
530
531
532 /* For each floor, find the number of valid chips it contains */
533 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
534 ret = 1;
535 numchips[floor] = 0;
536 for (chip = 0; chip < maxchips && ret != 0; chip++) {
537
538 ret = NanD_IdentChip(nand, floor, chip);
539 if (ret) {
540 numchips[floor]++;
541 nand->numchips++;
542 }
543 }
544 }
545
546 /* If there are none at all that we recognise, bail */
547 if (!nand->numchips) {
548 puts ("No flash chips recognised.\n");
549 return;
550 }
551
552 /* Allocate an array to hold the information for each chip */
553 nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
554 if (!nand->chips) {
555 puts ("No memory for allocating chip info structures\n");
556 return;
557 }
558
559 ret = 0;
560
561 /* Fill out the chip array with {floor, chipno} for each
562 * detected chip in the device. */
563 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
564 for (chip = 0; chip < numchips[floor]; chip++) {
565 nand->chips[ret].floor = floor;
566 nand->chips[ret].chip = chip;
567 nand->chips[ret].curadr = 0;
568 nand->chips[ret].curmode = 0x50;
569 ret++;
570 }
571 }
572
573 /* Calculate and print the total size of the device */
574 nand->totlen = nand->numchips * (1 << nand->chipshift);
575
576#ifdef NAND_DEBUG
577 printf("%d flash chips found. Total nand_chip size: %ld MB\n",
578 nand->numchips, nand->totlen >> 20);
579#endif
580}
0db5bca8 581
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582#ifdef CONFIG_MTD_NAND_ECC
583/* we need to be fast here, 1 us per read translates to 1 second per meg */
584static void nand_fast_copy (unsigned char *source, unsigned char *dest, long cntr)
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585{
586 while (cntr > 16) {
587 *dest++ = *source++;
588 *dest++ = *source++;
589 *dest++ = *source++;
590 *dest++ = *source++;
591 *dest++ = *source++;
592 *dest++ = *source++;
593 *dest++ = *source++;
594 *dest++ = *source++;
595 *dest++ = *source++;
596 *dest++ = *source++;
597 *dest++ = *source++;
598 *dest++ = *source++;
599 *dest++ = *source++;
600 *dest++ = *source++;
601 *dest++ = *source++;
602 *dest++ = *source++;
603 cntr -= 16;
604 }
605
606 while (cntr > 0) {
607 *dest++ = *source++;
608 cntr--;
609 }
610}
dc7c9a1a 611#endif
0db5bca8 612
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613/* we need to be fast here, 1 us per read translates to 1 second per meg */
614static void nand_fast_read(unsigned char *data_buf, int cntr, unsigned long nandptr)
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615{
616 while (cntr > 16) {
617 *data_buf++ = READ_NAND(nandptr);
618 *data_buf++ = READ_NAND(nandptr);
619 *data_buf++ = READ_NAND(nandptr);
620 *data_buf++ = READ_NAND(nandptr);
621 *data_buf++ = READ_NAND(nandptr);
622 *data_buf++ = READ_NAND(nandptr);
623 *data_buf++ = READ_NAND(nandptr);
624 *data_buf++ = READ_NAND(nandptr);
625 *data_buf++ = READ_NAND(nandptr);
626 *data_buf++ = READ_NAND(nandptr);
627 *data_buf++ = READ_NAND(nandptr);
628 *data_buf++ = READ_NAND(nandptr);
629 *data_buf++ = READ_NAND(nandptr);
630 *data_buf++ = READ_NAND(nandptr);
631 *data_buf++ = READ_NAND(nandptr);
632 *data_buf++ = READ_NAND(nandptr);
633 cntr -= 16;
634 }
635
636 while (cntr > 0) {
637 *data_buf++ = READ_NAND(nandptr);
638 cntr--;
639 }
640}
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641
642/* This routine is made available to other mtd code via
643 * inter_module_register. It must only be accessed through
644 * inter_module_get which will bump the use count of this module. The
645 * addresses passed back in mtd are valid as long as the use count of
646 * this module is non-zero, i.e. between inter_module_get and
647 * inter_module_put. Keith Owens <kaos@ocs.com.au> 29 Oct 2000.
648 */
649
650/*
651 * NAND read with ECC
652 */
653static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
654 size_t * retlen, u_char *buf, u_char *ecc_code)
655{
656 int col, page;
657 int ecc_status = 0;
658#ifdef CONFIG_MTD_NAND_ECC
659 int j;
660 int ecc_failed = 0;
661 u_char *data_poi;
662 u_char ecc_calc[6];
663#endif
664 unsigned long nandptr = nand->IO_ADDR;
665
666 /* Do not allow reads past end of device */
667 if ((start + len) > nand->totlen) {
0db5bca8 668 printf ("%s: Attempt read beyond end of device %x %x %x\n", __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
dc7c9a1a
WD
669 *retlen = 0;
670 return -1;
671 }
672
673 /* First we calculate the starting page */
0db5bca8
WD
674 /*page = shr(start, nand->page_shift);*/
675 page = start >> nand->page_shift;
dc7c9a1a
WD
676
677 /* Get raw starting column */
678 col = start & (nand->oobblock - 1);
679
680 /* Initialize return value */
681 *retlen = 0;
682
683 /* Select the NAND device */
684 NAND_ENABLE_CE(nand); /* set pin low */
685
686 /* Loop until all data read */
687 while (*retlen < len) {
688
689
690#ifdef CONFIG_MTD_NAND_ECC
691
692 /* Do we have this page in cache ? */
693 if (nand->cache_page == page)
694 goto readdata;
695 /* Send the read command */
696 NanD_Command(nand, NAND_CMD_READ0);
697 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
698 /* Read in a page + oob data */
699 nand_fast_read(nand->data_buf, nand->oobblock + nand->oobsize, nandptr);
700
701 /* copy data into cache, for read out of cache and if ecc fails */
702 if (nand->data_cache)
703 memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize);
704
705 /* Pick the ECC bytes out of the oob data */
706 for (j = 0; j < 6; j++)
707 ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
708
709 /* Calculate the ECC and verify it */
710 /* If block was not written with ECC, skip ECC */
711 if (oob_config.eccvalid_pos != -1 &&
712 (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
713
714 nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
715 switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
716 case -1:
0db5bca8 717 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
dc7c9a1a
WD
718 ecc_failed++;
719 break;
720 case 1:
721 case 2: /* transfer ECC corrected data to cache */
722 memcpy (nand->data_cache, nand->data_buf, 256);
723 break;
724 }
725 }
726
727 if (oob_config.eccvalid_pos != -1 &&
728 nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
729
730 nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
731 switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
732 case -1:
0db5bca8 733 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
dc7c9a1a
WD
734 ecc_failed++;
735 break;
736 case 1:
737 case 2: /* transfer ECC corrected data to cache */
738 if (nand->data_cache)
739 memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
740 break;
741 }
742 }
743readdata:
744 /* Read the data from ECC data buffer into return buffer */
745 data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
746 data_poi += col;
747 if ((*retlen + (nand->oobblock - col)) >= len) {
748 nand_fast_copy (data_poi, buf + *retlen, len - *retlen);
749 *retlen = len;
750 } else {
751 nand_fast_copy (data_poi, buf + *retlen, nand->oobblock - col);
752 *retlen += nand->oobblock - col;
753 }
754 /* Set cache page address, invalidate, if ecc_failed */
755 nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
756
757 ecc_status += ecc_failed;
758 ecc_failed = 0;
759
760#else
761 /* Send the read command */
762 NanD_Command(nand, NAND_CMD_READ0);
763 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
764 /* Read the data directly into the return buffer */
765 if ((*retlen + (nand->oobblock - col)) >= len) {
766 nand_fast_read(buf + *retlen, len - *retlen, nandptr);
767 *retlen = len;
768 /* We're done */
769 continue;
770 } else {
771 nand_fast_read(buf + *retlen, nand->oobblock - col, nandptr);
772 *retlen += nand->oobblock - col;
773 }
774#endif
775 /* For subsequent reads align to page boundary. */
776 col = 0;
777 /* Increment page address */
778 page++;
779 }
780
781 /* De-select the NAND device */
0db5bca8 782 NAND_DISABLE_CE(nand); /* set pin high */
dc7c9a1a
WD
783
784 /*
785 * Return success, if no ECC failures, else -EIO
786 * fs driver will take care of that, because
787 * retlen == desired len and result == -EIO
788 */
789 return ecc_status ? -1 : 0;
790}
791
dc7c9a1a
WD
792/*
793 * Nand_page_program function is used for write and writev !
794 */
795static int nand_write_page (struct nand_chip *nand,
796 int page, int col, int last, u_char * ecc_code)
797{
798
799 int i;
800#ifdef CONFIG_MTD_NAND_ECC
801 unsigned long nandptr = nand->IO_ADDR;
802#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
803 int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
804#endif
805#endif
806 /* pad oob area */
807 for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
808 nand->data_buf[i] = 0xff;
809
810#ifdef CONFIG_MTD_NAND_ECC
811 /* Zero out the ECC array */
812 for (i = 0; i < 6; i++)
813 ecc_code[i] = 0x00;
814
815 /* Read back previous written data, if col > 0 */
816 if (col) {
817 NanD_Command(nand, NAND_CMD_READ0);
0db5bca8 818 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
dc7c9a1a
WD
819 for (i = 0; i < col; i++)
820 nand->data_buf[i] = READ_NAND (nandptr);
821 }
822
823 /* Calculate and write the ECC if we have enough data */
824 if ((col < nand->eccsize) && (last >= nand->eccsize)) {
825 nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
826 for (i = 0; i < 3; i++)
827 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
828 if (oob_config.eccvalid_pos != -1)
829 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] = 0xf0;
830 }
831
832 /* Calculate and write the second ECC if we have enough data */
833 if ((nand->oobblock == 512) && (last == nand->oobblock)) {
834 nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
835 for (i = 3; i < 6; i++)
836 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
837 if (oob_config.eccvalid_pos != -1)
838 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] &= 0x0f;
839 }
840#endif
841 /* Prepad for partial page programming !!! */
842 for (i = 0; i < col; i++)
843 nand->data_buf[i] = 0xff;
844
845 /* Postpad for partial page programming !!! oob is already padded */
846 for (i = last; i < nand->oobblock; i++)
847 nand->data_buf[i] = 0xff;
848
849 /* Send command to begin auto page programming */
850 NanD_Command(nand, NAND_CMD_SEQIN);
851 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
852
853 /* Write out complete page of data */
854 for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
0db5bca8 855 WRITE_NAND(nand->data_buf[i], nand->IO_ADDR);
dc7c9a1a
WD
856
857 /* Send command to actually program the data */
0db5bca8
WD
858 NanD_Command(nand, NAND_CMD_PAGEPROG);
859 NanD_Command(nand, NAND_CMD_STATUS);
dc7c9a1a
WD
860
861 /* See if device thinks it succeeded */
862 if (READ_NAND(nand->IO_ADDR) & 0x01) {
0db5bca8 863 printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page);
dc7c9a1a
WD
864 return -1;
865 }
866#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
867 /*
868 * The NAND device assumes that it is always writing to
869 * a cleanly erased page. Hence, it performs its internal
870 * write verification only on bits that transitioned from
871 * 1 to 0. The device does NOT verify the whole page on a
872 * byte by byte basis. It is possible that the page was
873 * not completely erased or the page is becoming unusable
874 * due to wear. The read with ECC would catch the error
875 * later when the ECC page check fails, but we would rather
876 * catch it early in the page write stage. Better to write
877 * no data than invalid data.
878 */
879
880 /* Send command to read back the page */
881 if (col < nand->eccsize)
0db5bca8 882 NanD_Command(nand, NAND_CMD_READ0);
dc7c9a1a 883 else
0db5bca8
WD
884 NanD_Command(nand, NAND_CMD_READ1);
885 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
dc7c9a1a
WD
886
887 /* Loop through and verify the data */
888 for (i = col; i < last; i++) {
889 if (nand->data_buf[i] != readb (nand->IO_ADDR)) {
0db5bca8 890 printf ("%s: Failed write verify, page 0x%08x ", __FUNCTION__, page);
dc7c9a1a
WD
891 return -1;
892 }
893 }
894
895#ifdef CONFIG_MTD_NAND_ECC
896 /*
897 * We also want to check that the ECC bytes wrote
898 * correctly for the same reasons stated above.
899 */
900 NanD_Command(nand, NAND_CMD_READOOB);
901 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
902 for (i = 0; i < nand->oobsize; i++)
903 nand->data_buf[i] = readb (nand->IO_ADDR);
904 for (i = 0; i < ecc_bytes; i++) {
905 if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
0db5bca8
WD
906 printf ("%s: Failed ECC write "
907 "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
dc7c9a1a
WD
908 return -1;
909 }
910 }
911#endif
912#endif
913 return 0;
914}
0db5bca8 915
dc7c9a1a
WD
916static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
917 size_t * retlen, const u_char * buf, u_char * ecc_code)
918{
919 int i, page, col, cnt, ret = 0;
920
921 /* Do not allow write past end of device */
922 if ((to + len) > nand->totlen) {
0db5bca8 923 printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
dc7c9a1a
WD
924 return -1;
925 }
926
927 /* Shift to get page */
928 page = ((int) to) >> nand->page_shift;
929
930 /* Get the starting column */
931 col = to & (nand->oobblock - 1);
932
933 /* Initialize return length value */
934 *retlen = 0;
935
936 /* Select the NAND device */
0db5bca8 937 NAND_ENABLE_CE(nand); /* set pin low */
dc7c9a1a
WD
938
939 /* Check the WP bit */
0db5bca8 940 NanD_Command(nand, NAND_CMD_STATUS);
dc7c9a1a 941 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
0db5bca8 942 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
dc7c9a1a
WD
943 ret = -1;
944 goto out;
945 }
946
947 /* Loop until all data is written */
948 while (*retlen < len) {
949 /* Invalidate cache, if we write to this page */
950 if (nand->cache_page == page)
951 nand->cache_page = -1;
952
953 /* Write data into buffer */
954 if ((col + len) >= nand->oobblock)
955 for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++)
956 nand->data_buf[i] = buf[(*retlen + cnt)];
957 else
958 for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++)
959 nand->data_buf[i] = buf[(*retlen + cnt)];
960 /* We use the same function for write and writev !) */
961 ret = nand_write_page (nand, page, col, i, ecc_code);
962 if (ret)
963 goto out;
964
965 /* Next data start at page boundary */
966 col = 0;
967
968 /* Update written bytes count */
969 *retlen += cnt;
970
971 /* Increment page address */
972 page++;
973 }
974
975 /* Return happy */
976 *retlen = len;
977
978out:
979 /* De-select the NAND device */
0db5bca8 980 NAND_DISABLE_CE(nand); /* set pin high */
dc7c9a1a
WD
981
982 return ret;
983}
984
985#if 0 /* not used */
986/* Read a buffer from NanD */
987static void NanD_ReadBuf(struct nand_chip *nand, u_char * buf, int len)
988{
989 unsigned long nandptr;
990
991 nandptr = nand->IO_ADDR;
992
993 for (; len > 0; len--)
994 *buf++ = READ_NAND(nandptr);
995
996}
997/* Write a buffer to NanD */
998static void NanD_WriteBuf(struct nand_chip *nand, const u_char * buf, int len)
999{
1000 unsigned long nandptr;
1001 int i;
1002
1003 nandptr = nand->IO_ADDR;
1004
1005 if (len <= 0)
1006 return;
1007
1008 for (i = 0; i < len; i++)
1009 WRITE_NAND(buf[i], nandptr);
1010
1011}
1012
1013/* find_boot_record: Find the NFTL Media Header and its Spare copy which contains the
1014 * various device information of the NFTL partition and Bad Unit Table. Update
1015 * the ReplUnitTable[] table accroding to the Bad Unit Table. ReplUnitTable[]
1016 * is used for management of Erase Unit in other routines in nftl.c and nftlmount.c
1017 */
1018static int find_boot_record(struct NFTLrecord *nftl)
1019{
1020 struct nftl_uci1 h1;
1021 struct nftl_oob oob;
1022 unsigned int block, boot_record_count = 0;
1023 int retlen;
1024 u8 buf[SECTORSIZE];
1025 struct NFTLMediaHeader *mh = &nftl->MediaHdr;
1026 unsigned int i;
1027
1028 nftl->MediaUnit = BLOCK_NIL;
1029 nftl->SpareMediaUnit = BLOCK_NIL;
1030
1031 /* search for a valid boot record */
1032 for (block = 0; block < nftl->nb_blocks; block++) {
1033 int ret;
1034
1035 /* Check for ANAND header first. Then can whinge if it's found but later
1036 checks fail */
1037 if ((ret = nand_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE,
1038 &retlen, buf, NULL))) {
1039 static int warncount = 5;
1040
1041 if (warncount) {
1042 printf("Block read at 0x%x failed\n", block * nftl->EraseSize);
1043 if (!--warncount)
1044 puts ("Further failures for this block will not be printed\n");
1045 }
1046 continue;
1047 }
1048
1049 if (retlen < 6 || memcmp(buf, "ANAND", 6)) {
1050 /* ANAND\0 not found. Continue */
1051#ifdef PSYCHO_DEBUG
1052 printf("ANAND header not found at 0x%x\n", block * nftl->EraseSize);
1053#endif
1054 continue;
1055 }
1056
1057#ifdef NFTL_DEBUG
1058 printf("ANAND header found at 0x%x\n", block * nftl->EraseSize);
1059#endif
1060
1061 /* To be safer with BIOS, also use erase mark as discriminant */
1062 if ((ret = nand_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8,
1063 8, &retlen, (char *)&h1) < 0)) {
1064#ifdef NFTL_DEBUG
1065 printf("ANAND header found at 0x%x, but OOB data read failed\n",
1066 block * nftl->EraseSize);
1067#endif
1068 continue;
1069 }
1070
1071 /* OK, we like it. */
1072
1073 if (boot_record_count) {
1074 /* We've already processed one. So we just check if
1075 this one is the same as the first one we found */
1076 if (memcmp(mh, buf, sizeof(struct NFTLMediaHeader))) {
1077#ifdef NFTL_DEBUG
1078 printf("NFTL Media Headers at 0x%x and 0x%x disagree.\n",
1079 nftl->MediaUnit * nftl->EraseSize, block * nftl->EraseSize);
1080#endif
1081 /* if (debug) Print both side by side */
1082 return -1;
1083 }
1084 if (boot_record_count == 1)
1085 nftl->SpareMediaUnit = block;
1086
1087 boot_record_count++;
1088 continue;
1089 }
1090
1091 /* This is the first we've seen. Copy the media header structure into place */
1092 memcpy(mh, buf, sizeof(struct NFTLMediaHeader));
1093
1094 /* Do some sanity checks on it */
1095 if (mh->UnitSizeFactor != 0xff) {
1096 puts ("Sorry, we don't support UnitSizeFactor "
1097 "of != 1 yet.\n");
1098 return -1;
1099 }
1100
1101 nftl->nb_boot_blocks = le16_to_cpu(mh->FirstPhysicalEUN);
1102 if ((nftl->nb_boot_blocks + 2) >= nftl->nb_blocks) {
1103 printf ("NFTL Media Header sanity check failed:\n"
1104 "nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n",
1105 nftl->nb_boot_blocks, nftl->nb_blocks);
1106 return -1;
1107 }
1108
1109 nftl->numvunits = le32_to_cpu(mh->FormattedSize) / nftl->EraseSize;
1110 if (nftl->numvunits > (nftl->nb_blocks - nftl->nb_boot_blocks - 2)) {
1111 printf ("NFTL Media Header sanity check failed:\n"
1112 "numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n",
1113 nftl->numvunits,
1114 nftl->nb_blocks,
1115 nftl->nb_boot_blocks);
1116 return -1;
1117 }
1118
1119 nftl->nr_sects = nftl->numvunits * (nftl->EraseSize / SECTORSIZE);
1120
1121 /* If we're not using the last sectors in the device for some reason,
1122 reduce nb_blocks accordingly so we forget they're there */
1123 nftl->nb_blocks = le16_to_cpu(mh->NumEraseUnits) + le16_to_cpu(mh->FirstPhysicalEUN);
1124
1125 /* read the Bad Erase Unit Table and modify ReplUnitTable[] accordingly */
1126 for (i = 0; i < nftl->nb_blocks; i++) {
1127 if ((i & (SECTORSIZE - 1)) == 0) {
1128 /* read one sector for every SECTORSIZE of blocks */
1129 if ((ret = nand_read_ecc(nftl->mtd, block * nftl->EraseSize +
1130 i + SECTORSIZE, SECTORSIZE,
1131 &retlen, buf, (char *)&oob)) < 0) {
1132 puts ("Read of bad sector table failed\n");
1133 return -1;
1134 }
1135 }
1136 /* mark the Bad Erase Unit as RESERVED in ReplUnitTable */
1137 if (buf[i & (SECTORSIZE - 1)] != 0xff)
1138 nftl->ReplUnitTable[i] = BLOCK_RESERVED;
1139 }
1140
1141 nftl->MediaUnit = block;
1142 boot_record_count++;
1143
1144 } /* foreach (block) */
1145
1146 return boot_record_count?0:-1;
1147}
1148static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
1149 size_t * retlen, u_char * buf)
1150{
1151 int len256 = 0, ret;
1152 unsigned long nandptr;
1153 struct Nand *mychip;
0db5bca8 1154 int ret = 0;
dc7c9a1a
WD
1155
1156 nandptr = nand->IO_ADDR;
1157
1158 mychip = &nand->chips[shr(ofs, nand->chipshift)];
1159
1160 /* update address for 2M x 8bit devices. OOB starts on the second */
1161 /* page to maintain compatibility with nand_read_ecc. */
1162 if (nand->page256) {
1163 if (!(ofs & 0x8))
1164 ofs += 0x100;
1165 else
1166 ofs -= 0x8;
1167 }
1168
1169 NanD_Command(nand, NAND_CMD_READOOB);
1170 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1171
1172 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1173 /* Note: datasheet says it should automaticaly wrap to the */
1174 /* next OOB block, but it didn't work here. mf. */
1175 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1176 len256 = (ofs | 0x7) + 1 - ofs;
1177 NanD_ReadBuf(nand, buf, len256);
1178
1179 NanD_Command(nand, NAND_CMD_READOOB);
1180 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1181 }
1182
1183 NanD_ReadBuf(nand, &buf[len256], len - len256);
1184
1185 *retlen = len;
1186 /* Reading the full OOB data drops us off of the end of the page,
1187 * causing the flash device to go into busy mode, so we need
1188 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
1189
1190 ret = NanD_WaitReady(nand);
1191
1192 return ret;
1193
1194}
1195static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
1196 size_t * retlen, const u_char * buf)
1197{
1198 int len256 = 0;
1199 unsigned long nandptr = nand->IO_ADDR;
1200
1201#ifdef PSYCHO_DEBUG
1202 printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
1203 (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
1204 buf[8], buf[9], buf[14],buf[15]);
1205#endif
1206
1207 /* Reset the chip */
1208 NanD_Command(nand, NAND_CMD_RESET);
1209
1210 /* issue the Read2 command to set the pointer to the Spare Data Area. */
1211 NanD_Command(nand, NAND_CMD_READOOB);
1212 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1213
1214 /* update address for 2M x 8bit devices. OOB starts on the second */
1215 /* page to maintain compatibility with nand_read_ecc. */
1216 if (nand->page256) {
1217 if (!(ofs & 0x8))
1218 ofs += 0x100;
1219 else
1220 ofs -= 0x8;
1221 }
1222
1223 /* issue the Serial Data In command to initial the Page Program process */
1224 NanD_Command(nand, NAND_CMD_SEQIN);
1225 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1226
1227 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1228 /* Note: datasheet says it should automaticaly wrap to the */
1229 /* next OOB block, but it didn't work here. mf. */
1230 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1231 len256 = (ofs | 0x7) + 1 - ofs;
1232 NanD_WriteBuf(nand, buf, len256);
1233
1234 NanD_Command(nand, NAND_CMD_PAGEPROG);
1235 NanD_Command(nand, NAND_CMD_STATUS);
1236 /* NanD_WaitReady() is implicit in NanD_Command */
1237
1238 if (READ_NAND(nandptr) & 1) {
1239 puts ("Error programming oob data\n");
1240 /* There was an error */
1241 *retlen = 0;
1242 return -1;
1243 }
1244 NanD_Command(nand, NAND_CMD_SEQIN);
1245 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1246 }
1247
1248 NanD_WriteBuf(nand, &buf[len256], len - len256);
1249
1250 NanD_Command(nand, NAND_CMD_PAGEPROG);
1251 NanD_Command(nand, NAND_CMD_STATUS);
1252 /* NanD_WaitReady() is implicit in NanD_Command */
1253
1254 if (READ_NAND(nandptr) & 1) {
1255 puts ("Error programming oob data\n");
1256 /* There was an error */
1257 *retlen = 0;
1258 return -1;
1259 }
1260
1261 *retlen = len;
1262 return 0;
1263
1264}
1265#endif
1266
1267static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len)
1268{
1269 unsigned long nandptr;
1270 struct Nand *mychip;
85ec0bcc 1271 int ret = 0;
dc7c9a1a
WD
1272
1273 if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
1274 printf ("Offset and size must be sector aligned, erasesize = %d\n",
1275 (int) nand->erasesize);
1276 return -1;
1277 }
1278
1279 nandptr = nand->IO_ADDR;
1280
85ec0bcc
WD
1281 /* Select the NAND device */
1282 NAND_ENABLE_CE(nand); /* set pin low */
1283
1284 /* Check the WP bit */
1285 NanD_Command(nand, NAND_CMD_STATUS);
1286 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1287 printf ("nand_write_ecc: Device is write protected!!!\n");
1288 ret = -1;
1289 goto out;
1290 }
1291
0db5bca8
WD
1292 /* Select the NAND device */
1293 NAND_ENABLE_CE(nand); /* set pin low */
1294
1295 /* Check the WP bit */
1296 NanD_Command(nand, NAND_CMD_STATUS);
1297 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1298 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1299 ret = -1;
1300 goto out;
1301 }
1302
dc7c9a1a
WD
1303 /* FIXME: Do nand in the background. Use timers or schedule_task() */
1304 while(len) {
0db5bca8
WD
1305 /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
1306 mychip = &nand->chips[ofs >> nand->chipshift];
dc7c9a1a
WD
1307
1308 NanD_Command(nand, NAND_CMD_ERASE1);
1309 NanD_Address(nand, ADDR_PAGE, ofs);
1310 NanD_Command(nand, NAND_CMD_ERASE2);
1311
1312 NanD_Command(nand, NAND_CMD_STATUS);
1313
1314 if (READ_NAND(nandptr) & 1) {
0db5bca8
WD
1315 printf ("%s: Error erasing at 0x%lx\n",
1316 __FUNCTION__, (long)ofs);
dc7c9a1a 1317 /* There was an error */
85ec0bcc
WD
1318 ret = -1;
1319 goto out;
dc7c9a1a
WD
1320 }
1321 ofs += nand->erasesize;
1322 len -= nand->erasesize;
1323 }
1324
85ec0bcc
WD
1325out:
1326 /* De-select the NAND device */
1327 NAND_DISABLE_CE(nand); /* set pin high */
1328
1329 return ret;
dc7c9a1a
WD
1330}
1331
1332static inline int nandcheck(unsigned long potential, unsigned long physadr)
1333{
dc7c9a1a
WD
1334 return 0;
1335}
1336
1337void nand_probe(unsigned long physadr)
1338{
1339 struct nand_chip *nand = NULL;
1340 int i = 0, ChipID = 1;
1341
1342#ifdef CONFIG_MTD_NAND_ECC_JFFS2
1343 oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
1344 oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
1345 oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
1346 oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
1347 oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
1348 oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
1349 oob_config.badblock_pos = 5;
1350 oob_config.eccvalid_pos = 4;
1351#else
1352 oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
1353 oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
1354 oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
1355 oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
1356 oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
1357 oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
1358 oob_config.badblock_pos = NAND_NOOB_BADBPOS;
1359 oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
1360#endif
1361
1362 for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
1363 if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
1364 nand = nand_dev_desc + i;
1365 break;
1366 }
1367 }
1368
0db5bca8
WD
1369 if (curr_device == -1)
1370 curr_device = i;
dc7c9a1a 1371
0db5bca8 1372 memset((char *)nand, 0, sizeof(struct nand_chip));
dc7c9a1a 1373
0db5bca8
WD
1374 nand->cache_page = -1; /* init the cache page */
1375 nand->IO_ADDR = physadr;
1376 nand->ChipID = ChipID;
1377 NanD_ScanChips(nand);
1378 nand->data_buf = malloc (nand->oobblock + nand->oobsize);
1379 if (!nand->data_buf) {
1380 puts ("Cannot allocate memory for data structures.\n");
1381 return;
1382 }
dc7c9a1a
WD
1383}
1384
1385#ifdef CONFIG_MTD_NAND_ECC
1386/*
1387 * Pre-calculated 256-way 1 byte column parity
1388 */
1389static const u_char nand_ecc_precalc_table[] = {
1390 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
1391 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1392 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1393 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1394 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1395 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1396 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1397 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1398 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1399 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1400 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1401 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1402 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1403 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1404 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1405 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
1406};
1407
1408
1409/*
1410 * Creates non-inverted ECC code from line parity
1411 */
1412static void nand_trans_result(u_char reg2, u_char reg3,
1413 u_char *ecc_code)
1414{
1415 u_char a, b, i, tmp1, tmp2;
1416
1417 /* Initialize variables */
1418 a = b = 0x80;
1419 tmp1 = tmp2 = 0;
1420
1421 /* Calculate first ECC byte */
1422 for (i = 0; i < 4; i++) {
1423 if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
1424 tmp1 |= b;
1425 b >>= 1;
1426 if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
1427 tmp1 |= b;
1428 b >>= 1;
1429 a >>= 1;
1430 }
1431
1432 /* Calculate second ECC byte */
1433 b = 0x80;
1434 for (i = 0; i < 4; i++) {
1435 if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
1436 tmp2 |= b;
1437 b >>= 1;
1438 if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
1439 tmp2 |= b;
1440 b >>= 1;
1441 a >>= 1;
1442 }
1443
1444 /* Store two of the ECC bytes */
1445 ecc_code[0] = tmp1;
1446 ecc_code[1] = tmp2;
1447}
1448
1449/*
1450 * Calculate 3 byte ECC code for 256 byte block
1451 */
1452static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
1453{
1454 u_char idx, reg1, reg2, reg3;
1455 int j;
1456
1457 /* Initialize variables */
1458 reg1 = reg2 = reg3 = 0;
1459 ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
1460
1461 /* Build up column parity */
1462 for(j = 0; j < 256; j++) {
1463
1464 /* Get CP0 - CP5 from table */
1465 idx = nand_ecc_precalc_table[dat[j]];
1466 reg1 ^= (idx & 0x3f);
1467
1468 /* All bit XOR = 1 ? */
1469 if (idx & 0x40) {
1470 reg3 ^= (u_char) j;
1471 reg2 ^= ~((u_char) j);
1472 }
1473 }
1474
1475 /* Create non-inverted ECC code from line parity */
1476 nand_trans_result(reg2, reg3, ecc_code);
1477
1478 /* Calculate final ECC code */
1479 ecc_code[0] = ~ecc_code[0];
1480 ecc_code[1] = ~ecc_code[1];
1481 ecc_code[2] = ((~reg1) << 2) | 0x03;
1482}
1483
1484/*
1485 * Detect and correct a 1 bit error for 256 byte block
1486 */
1487static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
1488{
1489 u_char a, b, c, d1, d2, d3, add, bit, i;
1490
1491 /* Do error detection */
1492 d1 = calc_ecc[0] ^ read_ecc[0];
1493 d2 = calc_ecc[1] ^ read_ecc[1];
1494 d3 = calc_ecc[2] ^ read_ecc[2];
1495
1496 if ((d1 | d2 | d3) == 0) {
1497 /* No errors */
1498 return 0;
1499 }
1500 else {
1501 a = (d1 ^ (d1 >> 1)) & 0x55;
1502 b = (d2 ^ (d2 >> 1)) & 0x55;
1503 c = (d3 ^ (d3 >> 1)) & 0x54;
1504
1505 /* Found and will correct single bit error in the data */
1506 if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
1507 c = 0x80;
1508 add = 0;
1509 a = 0x80;
1510 for (i=0; i<4; i++) {
1511 if (d1 & c)
1512 add |= a;
1513 c >>= 2;
1514 a >>= 1;
1515 }
1516 c = 0x80;
1517 for (i=0; i<4; i++) {
1518 if (d2 & c)
1519 add |= a;
1520 c >>= 2;
1521 a >>= 1;
1522 }
1523 bit = 0;
1524 b = 0x04;
1525 c = 0x80;
1526 for (i=0; i<3; i++) {
1527 if (d3 & c)
1528 bit |= b;
1529 c >>= 2;
1530 b >>= 1;
1531 }
1532 b = 0x01;
1533 a = dat[add];
1534 a ^= (b << bit);
1535 dat[add] = a;
1536 return 1;
1537 }
1538 else {
1539 i = 0;
1540 while (d1) {
1541 if (d1 & 0x01)
1542 ++i;
1543 d1 >>= 1;
1544 }
1545 while (d2) {
1546 if (d2 & 0x01)
1547 ++i;
1548 d2 >>= 1;
1549 }
1550 while (d3) {
1551 if (d3 & 0x01)
1552 ++i;
1553 d3 >>= 1;
1554 }
1555 if (i == 1) {
1556 /* ECC Code Error Correction */
1557 read_ecc[0] = calc_ecc[0];
1558 read_ecc[1] = calc_ecc[1];
1559 read_ecc[2] = calc_ecc[2];
1560 return 2;
1561 }
1562 else {
1563 /* Uncorrectable Error */
1564 return -1;
1565 }
1566 }
1567 }
1568
1569 /* Should never happen */
1570 return -1;
1571}
1572#endif
1573#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */