* Patch by Arun Dharankar, 24 Mar 2003:
[people/ms/u-boot.git] / common / cmd_nand.c
CommitLineData
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WD
1/*
2 * Driver for NAND support, Rick Bronson
3 * borrowed heavily from:
4 * (c) 1999 Machine Vision Holdings, Inc.
5 * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
6 *
7 */
8
9#include <common.h>
dc7c9a1a
WD
10#include <command.h>
11#include <malloc.h>
12#include <asm/io.h>
13
14#ifdef CONFIG_SHOW_BOOT_PROGRESS
15# include <status_led.h>
16# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
17#else
18# define SHOW_BOOT_PROGRESS(arg)
19#endif
20
21#if (CONFIG_COMMANDS & CFG_CMD_NAND)
22
23#include <linux/mtd/nftl.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/nand_ids.h>
26
27/*
28 * Definition of the out of band configuration structure
29 */
30struct nand_oob_config {
31 int ecc_pos[6]; /* position of ECC bytes inside oob */
32 int badblock_pos; /* position of bad block flag inside oob -1 = inactive */
33 int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */
34} oob_config = { {0}, 0, 0};
35
36#define NAND_DEBUG
37#undef ECC_DEBUG
38#undef PSYCHO_DEBUG
39#undef NFTL_DEBUG
40
41#define CONFIG_MTD_NAND_ECC /* enable ECC */
42/* #define CONFIG_MTD_NAND_ECC_JFFS2 */
43
44/*
45 * Function Prototypes
46 */
47static void nand_print(struct nand_chip *nand);
48static int nand_rw (struct nand_chip* nand, int cmd,
49 size_t start, size_t len,
50 size_t * retlen, u_char * buf);
51static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len);
52static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
53 size_t * retlen, u_char *buf, u_char *ecc_code);
54static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
55 size_t * retlen, const u_char * buf, u_char * ecc_code);
56#ifdef CONFIG_MTD_NAND_ECC
57static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
58static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
59#endif
60
61static struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
62
63/* Current NAND Device */
64static int curr_device = -1;
65
66/* ------------------------------------------------------------------------- */
67
68int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
69{
70 int rcode = 0;
71
72 switch (argc) {
73 case 0:
74 case 1:
75 printf ("Usage:\n%s\n", cmdtp->usage);
76 return 1;
77 case 2:
78 if (strcmp(argv[1],"info") == 0) {
79 int i;
80
81 putc ('\n');
82
83 for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
84 if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
85 continue; /* list only known devices */
86 printf ("Device %d: ", i);
87 nand_print(&nand_dev_desc[i]);
88 }
89 return 0;
90
91 } else if (strcmp(argv[1],"device") == 0) {
92 if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
93 puts ("\nno devices available\n");
94 return 1;
95 }
96 printf ("\nDevice %d: ", curr_device);
97 nand_print(&nand_dev_desc[curr_device]);
98 return 0;
99 }
100 printf ("Usage:\n%s\n", cmdtp->usage);
101 return 1;
102 case 3:
103 if (strcmp(argv[1],"device") == 0) {
104 int dev = (int)simple_strtoul(argv[2], NULL, 10);
105
106 printf ("\nDevice %d: ", dev);
107 if (dev >= CFG_MAX_NAND_DEVICE) {
108 puts ("unknown device\n");
109 return 1;
110 }
111 nand_print(&nand_dev_desc[dev]);
112 /*nand_print (dev);*/
113
114 if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
115 return 1;
116 }
117
118 curr_device = dev;
119
120 puts ("... is now current device\n");
121
122 return 0;
123 }
124
125 printf ("Usage:\n%s\n", cmdtp->usage);
126 return 1;
127 default:
128 /* at least 4 args */
129
130 if (strcmp(argv[1],"read") == 0 || strcmp(argv[1],"write") == 0) {
131 ulong addr = simple_strtoul(argv[2], NULL, 16);
132 ulong off = simple_strtoul(argv[3], NULL, 16);
133 ulong size = simple_strtoul(argv[4], NULL, 16);
134 int cmd = (strcmp(argv[1],"read") == 0);
135 int ret, total;
136
137 printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
138 cmd ? "read" : "write", curr_device, off, size);
139
140 ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
141 &total, (u_char*)addr);
142
143 printf ("%d bytes %s: %s\n", total, cmd ? "read" : "write",
144 ret ? "ERROR" : "OK");
145
146 return ret;
147 } else if (strcmp(argv[1],"erase") == 0) {
148 ulong off = simple_strtoul(argv[2], NULL, 16);
149 ulong size = simple_strtoul(argv[3], NULL, 16);
150 int ret;
151
152 printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
153 curr_device, off, size);
154
155 ret = nand_erase (nand_dev_desc + curr_device, off, size);
156
157 printf("%s\n", ret ? "ERROR" : "OK");
158
159 return ret;
160 } else {
161 printf ("Usage:\n%s\n", cmdtp->usage);
162 rcode = 1;
163 }
164
165 return rcode;
166 }
167}
168
169int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
170{
171 char *boot_device = NULL;
172 char *ep;
173 int dev;
174 ulong cnt;
175 ulong addr;
176 ulong offset = 0;
177 image_header_t *hdr;
178 int rcode = 0;
179 switch (argc) {
180 case 1:
181 addr = CFG_LOAD_ADDR;
182 boot_device = getenv ("bootdevice");
183 break;
184 case 2:
185 addr = simple_strtoul(argv[1], NULL, 16);
186 boot_device = getenv ("bootdevice");
187 break;
188 case 3:
189 addr = simple_strtoul(argv[1], NULL, 16);
190 boot_device = argv[2];
191 break;
192 case 4:
193 addr = simple_strtoul(argv[1], NULL, 16);
194 boot_device = argv[2];
195 offset = simple_strtoul(argv[3], NULL, 16);
196 break;
197 default:
198 printf ("Usage:\n%s\n", cmdtp->usage);
199 SHOW_BOOT_PROGRESS (-1);
200 return 1;
201 }
202
203 if (!boot_device) {
204 puts ("\n** No boot device **\n");
205 SHOW_BOOT_PROGRESS (-1);
206 return 1;
207 }
208
209 dev = simple_strtoul(boot_device, &ep, 16);
210
211 if ((dev >= CFG_MAX_NAND_DEVICE) ||
212 (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
213 printf ("\n** Device %d not available\n", dev);
214 SHOW_BOOT_PROGRESS (-1);
215 return 1;
216 }
217
218 printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n",
219 dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
220 offset);
221
222 if (nand_rw (nand_dev_desc + dev, 1, offset,
223 SECTORSIZE, NULL, (u_char *)addr)) {
224 printf ("** Read error on %d\n", dev);
225 SHOW_BOOT_PROGRESS (-1);
226 return 1;
227 }
228
229 hdr = (image_header_t *)addr;
230
231 if (ntohl(hdr->ih_magic) == IH_MAGIC) {
232
233 print_image_hdr (hdr);
234
235 cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
236 cnt -= SECTORSIZE;
237 } else {
238 printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
239 SHOW_BOOT_PROGRESS (-1);
240 return 1;
241 }
242
243 if (nand_rw (nand_dev_desc + dev, 1, offset + SECTORSIZE, cnt,
244 NULL, (u_char *)(addr+SECTORSIZE))) {
245 printf ("** Read error on %d\n", dev);
246 SHOW_BOOT_PROGRESS (-1);
247 return 1;
248 }
249
250 /* Loading ok, update default load address */
251
252 load_addr = addr;
253
254 /* Check if we should attempt an auto-start */
255 if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
256 char *local_args[2];
257 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
258
259 local_args[0] = argv[0];
260 local_args[1] = NULL;
261
262 printf ("Automatic boot of image at addr 0x%08lX ...\n", addr);
263
264 do_bootm (cmdtp, 0, 1, local_args);
265 rcode = 1;
266 }
267 return rcode;
268}
269
270static int nand_rw (struct nand_chip* nand, int cmd,
271 size_t start, size_t len,
272 size_t * retlen, u_char * buf)
273{
274 int noecc, ret = 0, n, total = 0;
275 char eccbuf[6];
276
277 while(len) {
278 /* The ECC will not be calculated correctly if
279 less than 512 is written or read */
280 noecc = (start != (start | 0x1ff) + 1) || (len < 0x200);
281 if (cmd)
282 ret = nand_read_ecc(nand, start, len,
283 &n, (u_char*)buf,
284 noecc ? NULL : eccbuf);
285 else
286 ret = nand_write_ecc(nand, start, len,
287 &n, (u_char*)buf,
288 noecc ? NULL : eccbuf);
289
290 if (ret)
291 break;
292
293 start += n;
294 buf += n;
295 total += n;
296 len -= n;
297 }
298 if (retlen)
299 *retlen = total;
300
301 return ret;
302}
303
304static void nand_print(struct nand_chip *nand)
305 {
306 printf("%s at 0x%lX,\n"
307 "\t %d chip%s %s, size %d MB, \n"
308 "\t total size %ld MB, sector size %ld kB\n",
309 nand->name, nand->IO_ADDR, nand->numchips,
310 nand->numchips>1 ? "s" : "", nand->chips_name,
311 1 << (nand->chipshift - 20),
312 nand->totlen >> 20, nand->erasesize >> 10);
313
314 if (nand->nftl_found) {
315 struct NFTLrecord *nftl = &nand->nftl;
316 unsigned long bin_size, flash_size;
317
318 bin_size = nftl->nb_boot_blocks * nand->erasesize;
319 flash_size = (nftl->nb_blocks - nftl->nb_boot_blocks) * nand->erasesize;
320
321 printf("\t NFTL boot record:\n"
322 "\t Binary partition: size %ld%s\n"
323 "\t Flash disk partition: size %ld%s, offset 0x%lx\n",
324 bin_size > (1 << 20) ? bin_size >> 20 : bin_size >> 10,
325 bin_size > (1 << 20) ? "MB" : "kB",
326 flash_size > (1 << 20) ? flash_size >> 20 : flash_size >> 10,
327 flash_size > (1 << 20) ? "MB" : "kB", bin_size);
328 } else {
329 puts ("\t No NFTL boot record found.\n");
330 }
331}
332
333/* ------------------------------------------------------------------------- */
334
335/* This function is needed to avoid calls of the __ashrdi3 function. */
336static int shr(int val, int shift)
337 {
338 return val >> shift;
339}
340
341static int NanD_WaitReady(struct nand_chip *nand)
342{
343 /* This is inline, to optimise the common case, where it's ready instantly */
344 int ret = 0;
345 NAND_WAIT_READY(nand);
346
347 return ret;
348}
349
350/* NanD_Command: Send a flash command to the flash chip */
351
352static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
353{
354 unsigned long nandptr = nand->IO_ADDR;
355
356 /* Assert the CLE (Command Latch Enable) line to the flash chip */
357 NAND_CTL_SETCLE(nandptr);
358
359 /* Send the command */
360 WRITE_NAND_COMMAND(command, nandptr);
361
362 /* Lower the CLE line */
363 NAND_CTL_CLRCLE(nandptr);
364
365 return NanD_WaitReady(nand);
366}
367
368/* NanD_Address: Set the current address for the flash chip */
369
370static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
371 {
372 unsigned long nandptr;
373 int i;
374
375 nandptr = nand->IO_ADDR;
376
377 /* Assert the ALE (Address Latch Enable) line to the flash chip */
378 NAND_CTL_SETALE(nandptr);
379
380 /* Send the address */
381 /* Devices with 256-byte page are addressed as:
382 Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
383 * there is no device on the market with page256
384 and more than 24 bits.
385 Devices with 512-byte page are addressed as:
386 Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
387 * 25-31 is sent only if the chip support it.
388 * bit 8 changes the read command to be sent
389 (NAND_CMD_READ0 or NAND_CMD_READ1).
390 */
391
392 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
393 WRITE_NAND_ADDRESS(ofs, nandptr);
394
395 ofs = ofs >> nand->page_shift;
396
397 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
398 for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8)
399 WRITE_NAND_ADDRESS(ofs, nandptr);
400
401 /* Lower the ALE line */
402 NAND_CTL_CLRALE(nandptr);
403
404 /* Wait for the chip to respond */
405 return NanD_WaitReady(nand);
406 }
407
408/* NanD_SelectChip: Select a given flash chip within the current floor */
409
410static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
411{
412 /* Wait for it to be ready */
413 return NanD_WaitReady(nand);
414}
415
416/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
417
418static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
419{
420 int mfr, id, i;
421
422 NAND_ENABLE_CE(nand); /* set pin low */
423 /* Reset the chip */
424 if (NanD_Command(nand, NAND_CMD_RESET)) {
425#ifdef NAND_DEBUG
426 printf("NanD_Command (reset) for %d,%d returned true\n",
427 floor, chip);
428#endif
429 NAND_DISABLE_CE(nand); /* set pin high */
430 return 0;
431 }
432
433 /* Read the NAND chip ID: 1. Send ReadID command */
434 if (NanD_Command(nand, NAND_CMD_READID)) {
435#ifdef NAND_DEBUG
436 printf("NanD_Command (ReadID) for %d,%d returned true\n",
437 floor, chip);
438#endif
439 NAND_DISABLE_CE(nand); /* set pin high */
440 return 0;
441 }
442
443 /* Read the NAND chip ID: 2. Send address byte zero */
444 NanD_Address(nand, ADDR_COLUMN, 0);
445
446 /* Read the manufacturer and device id codes from the device */
447
448 mfr = READ_NAND(nand->IO_ADDR);
449
450 id = READ_NAND(nand->IO_ADDR);
451
452 NAND_DISABLE_CE(nand); /* set pin high */
453 /* No response - return failure */
454 if (mfr == 0xff || mfr == 0)
455 {
456 printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
457 return 0;
458 }
459
460 /* Check it's the same as the first chip we identified.
461 * M-Systems say that any given nand_chip device should only
462 * contain _one_ type of flash part, although that's not a
463 * hardware restriction. */
464 if (nand->mfr) {
465 if (nand->mfr == mfr && nand->id == id)
466 return 1; /* This is another the same the first */
467 else
468 printf("Flash chip at floor %d, chip %d is different:\n",
469 floor, chip);
470 }
471
472 /* Print and store the manufacturer and ID codes. */
473 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
474 if (mfr == nand_flash_ids[i].manufacture_id &&
475 id == nand_flash_ids[i].model_id) {
476#ifdef NAND_DEBUG
477 printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
478 "Chip ID: 0x%2.2X (%s)\n", mfr, id,
479 nand_flash_ids[i].name);
480#endif
481 if (!nand->mfr) {
482 nand->mfr = mfr;
483 nand->id = id;
484 nand->chipshift =
485 nand_flash_ids[i].chipshift;
486 nand->page256 = nand_flash_ids[i].page256;
487 if (nand->page256) {
488 nand->oobblock = 256;
489 nand->oobsize = 8;
490 nand->page_shift = 8;
491 } else {
492 nand->oobblock = 512;
493 nand->oobsize = 16;
494 nand->page_shift = 9;
495 }
496 nand->pageadrlen =
497 nand_flash_ids[i].pageadrlen;
498 nand->erasesize =
499 nand_flash_ids[i].erasesize;
500 nand->chips_name =
501 nand_flash_ids[i].name;
502 return 1;
503 }
504 return 0;
505 }
506 }
507
508
509#ifdef NAND_DEBUG
510 /* We haven't fully identified the chip. Print as much as we know. */
511 printf("Unknown flash chip found: %2.2X %2.2X\n",
512 id, mfr);
513#endif
514
515 return 0;
516}
517
518/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
519
520static void NanD_ScanChips(struct nand_chip *nand)
521{
522 int floor, chip;
523 int numchips[NAND_MAX_FLOORS];
524 int maxchips = NAND_MAX_CHIPS;
525 int ret = 1;
526
527 nand->numchips = 0;
528 nand->mfr = 0;
529 nand->id = 0;
530
531
532 /* For each floor, find the number of valid chips it contains */
533 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
534 ret = 1;
535 numchips[floor] = 0;
536 for (chip = 0; chip < maxchips && ret != 0; chip++) {
537
538 ret = NanD_IdentChip(nand, floor, chip);
539 if (ret) {
540 numchips[floor]++;
541 nand->numchips++;
542 }
543 }
544 }
545
546 /* If there are none at all that we recognise, bail */
547 if (!nand->numchips) {
548 puts ("No flash chips recognised.\n");
549 return;
550 }
551
552 /* Allocate an array to hold the information for each chip */
553 nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
554 if (!nand->chips) {
555 puts ("No memory for allocating chip info structures\n");
556 return;
557 }
558
559 ret = 0;
560
561 /* Fill out the chip array with {floor, chipno} for each
562 * detected chip in the device. */
563 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
564 for (chip = 0; chip < numchips[floor]; chip++) {
565 nand->chips[ret].floor = floor;
566 nand->chips[ret].chip = chip;
567 nand->chips[ret].curadr = 0;
568 nand->chips[ret].curmode = 0x50;
569 ret++;
570 }
571 }
572
573 /* Calculate and print the total size of the device */
574 nand->totlen = nand->numchips * (1 << nand->chipshift);
575
576#ifdef NAND_DEBUG
577 printf("%d flash chips found. Total nand_chip size: %ld MB\n",
578 nand->numchips, nand->totlen >> 20);
579#endif
580}
581#ifdef CONFIG_MTD_NAND_ECC
582/* we need to be fast here, 1 us per read translates to 1 second per meg */
583static void nand_fast_copy (unsigned char *source, unsigned char *dest, long cntr)
584 {
585 while (cntr > 16)
586 {
587 *dest++ = *source++;
588 *dest++ = *source++;
589 *dest++ = *source++;
590 *dest++ = *source++;
591 *dest++ = *source++;
592 *dest++ = *source++;
593 *dest++ = *source++;
594 *dest++ = *source++;
595 *dest++ = *source++;
596 *dest++ = *source++;
597 *dest++ = *source++;
598 *dest++ = *source++;
599 *dest++ = *source++;
600 *dest++ = *source++;
601 *dest++ = *source++;
602 *dest++ = *source++;
603 cntr -= 16;
604 }
605 while (cntr > 0)
606 {
607 *dest++ = *source++;
608 cntr--;
609 }
610 }
611#endif
612/* we need to be fast here, 1 us per read translates to 1 second per meg */
613static void nand_fast_read(unsigned char *data_buf, int cntr, unsigned long nandptr)
614 {
615 while (cntr > 16)
616 {
617 *data_buf++ = READ_NAND(nandptr);
618 *data_buf++ = READ_NAND(nandptr);
619 *data_buf++ = READ_NAND(nandptr);
620 *data_buf++ = READ_NAND(nandptr);
621 *data_buf++ = READ_NAND(nandptr);
622 *data_buf++ = READ_NAND(nandptr);
623 *data_buf++ = READ_NAND(nandptr);
624 *data_buf++ = READ_NAND(nandptr);
625 *data_buf++ = READ_NAND(nandptr);
626 *data_buf++ = READ_NAND(nandptr);
627 *data_buf++ = READ_NAND(nandptr);
628 *data_buf++ = READ_NAND(nandptr);
629 *data_buf++ = READ_NAND(nandptr);
630 *data_buf++ = READ_NAND(nandptr);
631 *data_buf++ = READ_NAND(nandptr);
632 *data_buf++ = READ_NAND(nandptr);
633 cntr -= 16;
634 }
635 while (cntr > 0)
636 {
637 *data_buf++ = READ_NAND(nandptr);
638 cntr--;
639 }
640 }
641
642/* This routine is made available to other mtd code via
643 * inter_module_register. It must only be accessed through
644 * inter_module_get which will bump the use count of this module. The
645 * addresses passed back in mtd are valid as long as the use count of
646 * this module is non-zero, i.e. between inter_module_get and
647 * inter_module_put. Keith Owens <kaos@ocs.com.au> 29 Oct 2000.
648 */
649
650/*
651 * NAND read with ECC
652 */
653static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
654 size_t * retlen, u_char *buf, u_char *ecc_code)
655{
656 int col, page;
657 int ecc_status = 0;
658#ifdef CONFIG_MTD_NAND_ECC
659 int j;
660 int ecc_failed = 0;
661 u_char *data_poi;
662 u_char ecc_calc[6];
663#endif
664 unsigned long nandptr = nand->IO_ADDR;
665
666 /* Do not allow reads past end of device */
667 if ((start + len) > nand->totlen) {
668 printf ("nand_read_ecc: Attempt read beyond end of device %x %x %x\n", (uint) start, (uint) len, (uint) nand->totlen);
669 *retlen = 0;
670 return -1;
671 }
672
673 /* First we calculate the starting page */
674 page = shr(start, nand->page_shift);
675
676 /* Get raw starting column */
677 col = start & (nand->oobblock - 1);
678
679 /* Initialize return value */
680 *retlen = 0;
681
682 /* Select the NAND device */
683 NAND_ENABLE_CE(nand); /* set pin low */
684
685 /* Loop until all data read */
686 while (*retlen < len) {
687
688
689#ifdef CONFIG_MTD_NAND_ECC
690
691 /* Do we have this page in cache ? */
692 if (nand->cache_page == page)
693 goto readdata;
694 /* Send the read command */
695 NanD_Command(nand, NAND_CMD_READ0);
696 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
697 /* Read in a page + oob data */
698 nand_fast_read(nand->data_buf, nand->oobblock + nand->oobsize, nandptr);
699
700 /* copy data into cache, for read out of cache and if ecc fails */
701 if (nand->data_cache)
702 memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize);
703
704 /* Pick the ECC bytes out of the oob data */
705 for (j = 0; j < 6; j++)
706 ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
707
708 /* Calculate the ECC and verify it */
709 /* If block was not written with ECC, skip ECC */
710 if (oob_config.eccvalid_pos != -1 &&
711 (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
712
713 nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
714 switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
715 case -1:
716 printf ("nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
717 ecc_failed++;
718 break;
719 case 1:
720 case 2: /* transfer ECC corrected data to cache */
721 memcpy (nand->data_cache, nand->data_buf, 256);
722 break;
723 }
724 }
725
726 if (oob_config.eccvalid_pos != -1 &&
727 nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
728
729 nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
730 switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
731 case -1:
732 printf ("nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page);
733 ecc_failed++;
734 break;
735 case 1:
736 case 2: /* transfer ECC corrected data to cache */
737 if (nand->data_cache)
738 memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
739 break;
740 }
741 }
742readdata:
743 /* Read the data from ECC data buffer into return buffer */
744 data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
745 data_poi += col;
746 if ((*retlen + (nand->oobblock - col)) >= len) {
747 nand_fast_copy (data_poi, buf + *retlen, len - *retlen);
748 *retlen = len;
749 } else {
750 nand_fast_copy (data_poi, buf + *retlen, nand->oobblock - col);
751 *retlen += nand->oobblock - col;
752 }
753 /* Set cache page address, invalidate, if ecc_failed */
754 nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
755
756 ecc_status += ecc_failed;
757 ecc_failed = 0;
758
759#else
760 /* Send the read command */
761 NanD_Command(nand, NAND_CMD_READ0);
762 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
763 /* Read the data directly into the return buffer */
764 if ((*retlen + (nand->oobblock - col)) >= len) {
765 nand_fast_read(buf + *retlen, len - *retlen, nandptr);
766 *retlen = len;
767 /* We're done */
768 continue;
769 } else {
770 nand_fast_read(buf + *retlen, nand->oobblock - col, nandptr);
771 *retlen += nand->oobblock - col;
772 }
773#endif
774 /* For subsequent reads align to page boundary. */
775 col = 0;
776 /* Increment page address */
777 page++;
778 }
779
780 /* De-select the NAND device */
781 NAND_DISABLE_CE(nand); /* set pin high */
782
783 /*
784 * Return success, if no ECC failures, else -EIO
785 * fs driver will take care of that, because
786 * retlen == desired len and result == -EIO
787 */
788 return ecc_status ? -1 : 0;
789}
790
791
792/*
793 * Nand_page_program function is used for write and writev !
794 */
795static int nand_write_page (struct nand_chip *nand,
796 int page, int col, int last, u_char * ecc_code)
797{
798
799 int i;
800#ifdef CONFIG_MTD_NAND_ECC
801 unsigned long nandptr = nand->IO_ADDR;
802#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
803 int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
804#endif
805#endif
806 /* pad oob area */
807 for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
808 nand->data_buf[i] = 0xff;
809
810#ifdef CONFIG_MTD_NAND_ECC
811 /* Zero out the ECC array */
812 for (i = 0; i < 6; i++)
813 ecc_code[i] = 0x00;
814
815 /* Read back previous written data, if col > 0 */
816 if (col) {
817 NanD_Command(nand, NAND_CMD_READ0);
818 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
819 for (i = 0; i < col; i++)
820 nand->data_buf[i] = READ_NAND (nandptr);
821 }
822
823 /* Calculate and write the ECC if we have enough data */
824 if ((col < nand->eccsize) && (last >= nand->eccsize)) {
825 nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
826 for (i = 0; i < 3; i++)
827 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
828 if (oob_config.eccvalid_pos != -1)
829 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] = 0xf0;
830 }
831
832 /* Calculate and write the second ECC if we have enough data */
833 if ((nand->oobblock == 512) && (last == nand->oobblock)) {
834 nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
835 for (i = 3; i < 6; i++)
836 nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
837 if (oob_config.eccvalid_pos != -1)
838 nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] &= 0x0f;
839 }
840#endif
841 /* Prepad for partial page programming !!! */
842 for (i = 0; i < col; i++)
843 nand->data_buf[i] = 0xff;
844
845 /* Postpad for partial page programming !!! oob is already padded */
846 for (i = last; i < nand->oobblock; i++)
847 nand->data_buf[i] = 0xff;
848
849 /* Send command to begin auto page programming */
850 NanD_Command(nand, NAND_CMD_SEQIN);
851 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
852
853 /* Write out complete page of data */
854 for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
855 WRITE_NAND(nand->data_buf[i], nand->IO_ADDR);
856
857 /* Send command to actually program the data */
858 NanD_Command(nand, NAND_CMD_PAGEPROG);
859 NanD_Command(nand, NAND_CMD_STATUS);
860
861 /* See if device thinks it succeeded */
862 if (READ_NAND(nand->IO_ADDR) & 0x01) {
863 printf ("nand_write_ecc: " "Failed write, page 0x%08x, ", page);
864 return -1;
865 }
866#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
867 /*
868 * The NAND device assumes that it is always writing to
869 * a cleanly erased page. Hence, it performs its internal
870 * write verification only on bits that transitioned from
871 * 1 to 0. The device does NOT verify the whole page on a
872 * byte by byte basis. It is possible that the page was
873 * not completely erased or the page is becoming unusable
874 * due to wear. The read with ECC would catch the error
875 * later when the ECC page check fails, but we would rather
876 * catch it early in the page write stage. Better to write
877 * no data than invalid data.
878 */
879
880 /* Send command to read back the page */
881 if (col < nand->eccsize)
882 NanD_Command(nand, NAND_CMD_READ0);
883 else
884 NanD_Command(nand, NAND_CMD_READ1);
885 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
886
887 /* Loop through and verify the data */
888 for (i = col; i < last; i++) {
889 if (nand->data_buf[i] != readb (nand->IO_ADDR)) {
890 printf ("nand_write_ecc: " "Failed write verify, page 0x%08x ", page);
891 return -1;
892 }
893 }
894
895#ifdef CONFIG_MTD_NAND_ECC
896 /*
897 * We also want to check that the ECC bytes wrote
898 * correctly for the same reasons stated above.
899 */
900 NanD_Command(nand, NAND_CMD_READOOB);
901 NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
902 for (i = 0; i < nand->oobsize; i++)
903 nand->data_buf[i] = readb (nand->IO_ADDR);
904 for (i = 0; i < ecc_bytes; i++) {
905 if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
906 printf ("nand_write_ecc: Failed ECC write "
907 "verify, page 0x%08x, " "%6i bytes were succesful\n", page, i);
908 return -1;
909 }
910 }
911#endif
912#endif
913 return 0;
914}
915static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
916 size_t * retlen, const u_char * buf, u_char * ecc_code)
917{
918 int i, page, col, cnt, ret = 0;
919
920 /* Do not allow write past end of device */
921 if ((to + len) > nand->totlen) {
922 printf ("nand_write_oob: Attempt to write past end of page\n");
923 return -1;
924 }
925
926 /* Shift to get page */
927 page = ((int) to) >> nand->page_shift;
928
929 /* Get the starting column */
930 col = to & (nand->oobblock - 1);
931
932 /* Initialize return length value */
933 *retlen = 0;
934
935 /* Select the NAND device */
936 NAND_ENABLE_CE(nand); /* set pin low */
937
938 /* Check the WP bit */
939 NanD_Command(nand, NAND_CMD_STATUS);
940 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
941 printf ("nand_write_ecc: Device is write protected!!!\n");
942 ret = -1;
943 goto out;
944 }
945
946 /* Loop until all data is written */
947 while (*retlen < len) {
948 /* Invalidate cache, if we write to this page */
949 if (nand->cache_page == page)
950 nand->cache_page = -1;
951
952 /* Write data into buffer */
953 if ((col + len) >= nand->oobblock)
954 for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++)
955 nand->data_buf[i] = buf[(*retlen + cnt)];
956 else
957 for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++)
958 nand->data_buf[i] = buf[(*retlen + cnt)];
959 /* We use the same function for write and writev !) */
960 ret = nand_write_page (nand, page, col, i, ecc_code);
961 if (ret)
962 goto out;
963
964 /* Next data start at page boundary */
965 col = 0;
966
967 /* Update written bytes count */
968 *retlen += cnt;
969
970 /* Increment page address */
971 page++;
972 }
973
974 /* Return happy */
975 *retlen = len;
976
977out:
978 /* De-select the NAND device */
979 NAND_DISABLE_CE(nand); /* set pin high */
980
981 return ret;
982}
983
984#if 0 /* not used */
985/* Read a buffer from NanD */
986static void NanD_ReadBuf(struct nand_chip *nand, u_char * buf, int len)
987{
988 unsigned long nandptr;
989
990 nandptr = nand->IO_ADDR;
991
992 for (; len > 0; len--)
993 *buf++ = READ_NAND(nandptr);
994
995}
996/* Write a buffer to NanD */
997static void NanD_WriteBuf(struct nand_chip *nand, const u_char * buf, int len)
998{
999 unsigned long nandptr;
1000 int i;
1001
1002 nandptr = nand->IO_ADDR;
1003
1004 if (len <= 0)
1005 return;
1006
1007 for (i = 0; i < len; i++)
1008 WRITE_NAND(buf[i], nandptr);
1009
1010}
1011
1012/* find_boot_record: Find the NFTL Media Header and its Spare copy which contains the
1013 * various device information of the NFTL partition and Bad Unit Table. Update
1014 * the ReplUnitTable[] table accroding to the Bad Unit Table. ReplUnitTable[]
1015 * is used for management of Erase Unit in other routines in nftl.c and nftlmount.c
1016 */
1017static int find_boot_record(struct NFTLrecord *nftl)
1018{
1019 struct nftl_uci1 h1;
1020 struct nftl_oob oob;
1021 unsigned int block, boot_record_count = 0;
1022 int retlen;
1023 u8 buf[SECTORSIZE];
1024 struct NFTLMediaHeader *mh = &nftl->MediaHdr;
1025 unsigned int i;
1026
1027 nftl->MediaUnit = BLOCK_NIL;
1028 nftl->SpareMediaUnit = BLOCK_NIL;
1029
1030 /* search for a valid boot record */
1031 for (block = 0; block < nftl->nb_blocks; block++) {
1032 int ret;
1033
1034 /* Check for ANAND header first. Then can whinge if it's found but later
1035 checks fail */
1036 if ((ret = nand_read_ecc(nftl->mtd, block * nftl->EraseSize, SECTORSIZE,
1037 &retlen, buf, NULL))) {
1038 static int warncount = 5;
1039
1040 if (warncount) {
1041 printf("Block read at 0x%x failed\n", block * nftl->EraseSize);
1042 if (!--warncount)
1043 puts ("Further failures for this block will not be printed\n");
1044 }
1045 continue;
1046 }
1047
1048 if (retlen < 6 || memcmp(buf, "ANAND", 6)) {
1049 /* ANAND\0 not found. Continue */
1050#ifdef PSYCHO_DEBUG
1051 printf("ANAND header not found at 0x%x\n", block * nftl->EraseSize);
1052#endif
1053 continue;
1054 }
1055
1056#ifdef NFTL_DEBUG
1057 printf("ANAND header found at 0x%x\n", block * nftl->EraseSize);
1058#endif
1059
1060 /* To be safer with BIOS, also use erase mark as discriminant */
1061 if ((ret = nand_read_oob(nftl->mtd, block * nftl->EraseSize + SECTORSIZE + 8,
1062 8, &retlen, (char *)&h1) < 0)) {
1063#ifdef NFTL_DEBUG
1064 printf("ANAND header found at 0x%x, but OOB data read failed\n",
1065 block * nftl->EraseSize);
1066#endif
1067 continue;
1068 }
1069
1070 /* OK, we like it. */
1071
1072 if (boot_record_count) {
1073 /* We've already processed one. So we just check if
1074 this one is the same as the first one we found */
1075 if (memcmp(mh, buf, sizeof(struct NFTLMediaHeader))) {
1076#ifdef NFTL_DEBUG
1077 printf("NFTL Media Headers at 0x%x and 0x%x disagree.\n",
1078 nftl->MediaUnit * nftl->EraseSize, block * nftl->EraseSize);
1079#endif
1080 /* if (debug) Print both side by side */
1081 return -1;
1082 }
1083 if (boot_record_count == 1)
1084 nftl->SpareMediaUnit = block;
1085
1086 boot_record_count++;
1087 continue;
1088 }
1089
1090 /* This is the first we've seen. Copy the media header structure into place */
1091 memcpy(mh, buf, sizeof(struct NFTLMediaHeader));
1092
1093 /* Do some sanity checks on it */
1094 if (mh->UnitSizeFactor != 0xff) {
1095 puts ("Sorry, we don't support UnitSizeFactor "
1096 "of != 1 yet.\n");
1097 return -1;
1098 }
1099
1100 nftl->nb_boot_blocks = le16_to_cpu(mh->FirstPhysicalEUN);
1101 if ((nftl->nb_boot_blocks + 2) >= nftl->nb_blocks) {
1102 printf ("NFTL Media Header sanity check failed:\n"
1103 "nb_boot_blocks (%d) + 2 > nb_blocks (%d)\n",
1104 nftl->nb_boot_blocks, nftl->nb_blocks);
1105 return -1;
1106 }
1107
1108 nftl->numvunits = le32_to_cpu(mh->FormattedSize) / nftl->EraseSize;
1109 if (nftl->numvunits > (nftl->nb_blocks - nftl->nb_boot_blocks - 2)) {
1110 printf ("NFTL Media Header sanity check failed:\n"
1111 "numvunits (%d) > nb_blocks (%d) - nb_boot_blocks(%d) - 2\n",
1112 nftl->numvunits,
1113 nftl->nb_blocks,
1114 nftl->nb_boot_blocks);
1115 return -1;
1116 }
1117
1118 nftl->nr_sects = nftl->numvunits * (nftl->EraseSize / SECTORSIZE);
1119
1120 /* If we're not using the last sectors in the device for some reason,
1121 reduce nb_blocks accordingly so we forget they're there */
1122 nftl->nb_blocks = le16_to_cpu(mh->NumEraseUnits) + le16_to_cpu(mh->FirstPhysicalEUN);
1123
1124 /* read the Bad Erase Unit Table and modify ReplUnitTable[] accordingly */
1125 for (i = 0; i < nftl->nb_blocks; i++) {
1126 if ((i & (SECTORSIZE - 1)) == 0) {
1127 /* read one sector for every SECTORSIZE of blocks */
1128 if ((ret = nand_read_ecc(nftl->mtd, block * nftl->EraseSize +
1129 i + SECTORSIZE, SECTORSIZE,
1130 &retlen, buf, (char *)&oob)) < 0) {
1131 puts ("Read of bad sector table failed\n");
1132 return -1;
1133 }
1134 }
1135 /* mark the Bad Erase Unit as RESERVED in ReplUnitTable */
1136 if (buf[i & (SECTORSIZE - 1)] != 0xff)
1137 nftl->ReplUnitTable[i] = BLOCK_RESERVED;
1138 }
1139
1140 nftl->MediaUnit = block;
1141 boot_record_count++;
1142
1143 } /* foreach (block) */
1144
1145 return boot_record_count?0:-1;
1146}
1147static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
1148 size_t * retlen, u_char * buf)
1149{
1150 int len256 = 0, ret;
1151 unsigned long nandptr;
1152 struct Nand *mychip;
1153
1154 nandptr = nand->IO_ADDR;
1155
1156 mychip = &nand->chips[shr(ofs, nand->chipshift)];
1157
1158 /* update address for 2M x 8bit devices. OOB starts on the second */
1159 /* page to maintain compatibility with nand_read_ecc. */
1160 if (nand->page256) {
1161 if (!(ofs & 0x8))
1162 ofs += 0x100;
1163 else
1164 ofs -= 0x8;
1165 }
1166
1167 NanD_Command(nand, NAND_CMD_READOOB);
1168 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1169
1170 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1171 /* Note: datasheet says it should automaticaly wrap to the */
1172 /* next OOB block, but it didn't work here. mf. */
1173 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1174 len256 = (ofs | 0x7) + 1 - ofs;
1175 NanD_ReadBuf(nand, buf, len256);
1176
1177 NanD_Command(nand, NAND_CMD_READOOB);
1178 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1179 }
1180
1181 NanD_ReadBuf(nand, &buf[len256], len - len256);
1182
1183 *retlen = len;
1184 /* Reading the full OOB data drops us off of the end of the page,
1185 * causing the flash device to go into busy mode, so we need
1186 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
1187
1188 ret = NanD_WaitReady(nand);
1189
1190 return ret;
1191
1192}
1193static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
1194 size_t * retlen, const u_char * buf)
1195{
1196 int len256 = 0;
1197 unsigned long nandptr = nand->IO_ADDR;
1198
1199#ifdef PSYCHO_DEBUG
1200 printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
1201 (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
1202 buf[8], buf[9], buf[14],buf[15]);
1203#endif
1204
1205 /* Reset the chip */
1206 NanD_Command(nand, NAND_CMD_RESET);
1207
1208 /* issue the Read2 command to set the pointer to the Spare Data Area. */
1209 NanD_Command(nand, NAND_CMD_READOOB);
1210 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1211
1212 /* update address for 2M x 8bit devices. OOB starts on the second */
1213 /* page to maintain compatibility with nand_read_ecc. */
1214 if (nand->page256) {
1215 if (!(ofs & 0x8))
1216 ofs += 0x100;
1217 else
1218 ofs -= 0x8;
1219 }
1220
1221 /* issue the Serial Data In command to initial the Page Program process */
1222 NanD_Command(nand, NAND_CMD_SEQIN);
1223 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1224
1225 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1226 /* Note: datasheet says it should automaticaly wrap to the */
1227 /* next OOB block, but it didn't work here. mf. */
1228 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1229 len256 = (ofs | 0x7) + 1 - ofs;
1230 NanD_WriteBuf(nand, buf, len256);
1231
1232 NanD_Command(nand, NAND_CMD_PAGEPROG);
1233 NanD_Command(nand, NAND_CMD_STATUS);
1234 /* NanD_WaitReady() is implicit in NanD_Command */
1235
1236 if (READ_NAND(nandptr) & 1) {
1237 puts ("Error programming oob data\n");
1238 /* There was an error */
1239 *retlen = 0;
1240 return -1;
1241 }
1242 NanD_Command(nand, NAND_CMD_SEQIN);
1243 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1244 }
1245
1246 NanD_WriteBuf(nand, &buf[len256], len - len256);
1247
1248 NanD_Command(nand, NAND_CMD_PAGEPROG);
1249 NanD_Command(nand, NAND_CMD_STATUS);
1250 /* NanD_WaitReady() is implicit in NanD_Command */
1251
1252 if (READ_NAND(nandptr) & 1) {
1253 puts ("Error programming oob data\n");
1254 /* There was an error */
1255 *retlen = 0;
1256 return -1;
1257 }
1258
1259 *retlen = len;
1260 return 0;
1261
1262}
1263#endif
1264
1265static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len)
1266{
1267 unsigned long nandptr;
1268 struct Nand *mychip;
85ec0bcc 1269 int ret = 0;
dc7c9a1a
WD
1270
1271 if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
1272 printf ("Offset and size must be sector aligned, erasesize = %d\n",
1273 (int) nand->erasesize);
1274 return -1;
1275 }
1276
1277 nandptr = nand->IO_ADDR;
1278
85ec0bcc
WD
1279 /* Select the NAND device */
1280 NAND_ENABLE_CE(nand); /* set pin low */
1281
1282 /* Check the WP bit */
1283 NanD_Command(nand, NAND_CMD_STATUS);
1284 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1285 printf ("nand_write_ecc: Device is write protected!!!\n");
1286 ret = -1;
1287 goto out;
1288 }
1289
dc7c9a1a
WD
1290 /* FIXME: Do nand in the background. Use timers or schedule_task() */
1291 while(len) {
1292 mychip = &nand->chips[shr(ofs, nand->chipshift)];
1293
1294 NanD_Command(nand, NAND_CMD_ERASE1);
1295 NanD_Address(nand, ADDR_PAGE, ofs);
1296 NanD_Command(nand, NAND_CMD_ERASE2);
1297
1298 NanD_Command(nand, NAND_CMD_STATUS);
1299
1300 if (READ_NAND(nandptr) & 1) {
1301 printf("Error erasing at 0x%lx\n", (long)ofs);
1302 /* There was an error */
85ec0bcc
WD
1303 ret = -1;
1304 goto out;
dc7c9a1a
WD
1305 }
1306 ofs += nand->erasesize;
1307 len -= nand->erasesize;
1308 }
1309
85ec0bcc
WD
1310out:
1311 /* De-select the NAND device */
1312 NAND_DISABLE_CE(nand); /* set pin high */
1313
1314 return ret;
dc7c9a1a
WD
1315}
1316
1317static inline int nandcheck(unsigned long potential, unsigned long physadr)
1318{
dc7c9a1a
WD
1319 return 0;
1320}
1321
1322void nand_probe(unsigned long physadr)
1323{
1324 struct nand_chip *nand = NULL;
1325 int i = 0, ChipID = 1;
1326
1327#ifdef CONFIG_MTD_NAND_ECC_JFFS2
1328 oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
1329 oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
1330 oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
1331 oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
1332 oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
1333 oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
1334 oob_config.badblock_pos = 5;
1335 oob_config.eccvalid_pos = 4;
1336#else
1337 oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
1338 oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
1339 oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
1340 oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
1341 oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
1342 oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
1343 oob_config.badblock_pos = NAND_NOOB_BADBPOS;
1344 oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
1345#endif
1346
1347 for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
1348 if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
1349 nand = nand_dev_desc + i;
1350 break;
1351 }
1352 }
1353
1354 if (curr_device == -1)
1355 curr_device = i;
1356
1357 memset((char *)nand, 0, sizeof(struct nand_chip));
1358
1359 nand->cache_page = -1; /* init the cache page */
1360 nand->IO_ADDR = physadr;
1361 nand->ChipID = ChipID;
1362 NanD_ScanChips(nand);
1363 nand->data_buf = malloc (nand->oobblock + nand->oobsize);
1364 if (!nand->data_buf) {
1365 puts ("Cannot allocate memory for data structures.\n");
1366 return;
1367 }
1368}
1369
1370#ifdef CONFIG_MTD_NAND_ECC
1371/*
1372 * Pre-calculated 256-way 1 byte column parity
1373 */
1374static const u_char nand_ecc_precalc_table[] = {
1375 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
1376 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1377 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1378 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1379 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1380 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1381 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1382 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1383 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1384 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1385 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1386 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1387 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1388 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1389 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1390 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
1391};
1392
1393
1394/*
1395 * Creates non-inverted ECC code from line parity
1396 */
1397static void nand_trans_result(u_char reg2, u_char reg3,
1398 u_char *ecc_code)
1399{
1400 u_char a, b, i, tmp1, tmp2;
1401
1402 /* Initialize variables */
1403 a = b = 0x80;
1404 tmp1 = tmp2 = 0;
1405
1406 /* Calculate first ECC byte */
1407 for (i = 0; i < 4; i++) {
1408 if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
1409 tmp1 |= b;
1410 b >>= 1;
1411 if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
1412 tmp1 |= b;
1413 b >>= 1;
1414 a >>= 1;
1415 }
1416
1417 /* Calculate second ECC byte */
1418 b = 0x80;
1419 for (i = 0; i < 4; i++) {
1420 if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
1421 tmp2 |= b;
1422 b >>= 1;
1423 if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
1424 tmp2 |= b;
1425 b >>= 1;
1426 a >>= 1;
1427 }
1428
1429 /* Store two of the ECC bytes */
1430 ecc_code[0] = tmp1;
1431 ecc_code[1] = tmp2;
1432}
1433
1434/*
1435 * Calculate 3 byte ECC code for 256 byte block
1436 */
1437static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
1438{
1439 u_char idx, reg1, reg2, reg3;
1440 int j;
1441
1442 /* Initialize variables */
1443 reg1 = reg2 = reg3 = 0;
1444 ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
1445
1446 /* Build up column parity */
1447 for(j = 0; j < 256; j++) {
1448
1449 /* Get CP0 - CP5 from table */
1450 idx = nand_ecc_precalc_table[dat[j]];
1451 reg1 ^= (idx & 0x3f);
1452
1453 /* All bit XOR = 1 ? */
1454 if (idx & 0x40) {
1455 reg3 ^= (u_char) j;
1456 reg2 ^= ~((u_char) j);
1457 }
1458 }
1459
1460 /* Create non-inverted ECC code from line parity */
1461 nand_trans_result(reg2, reg3, ecc_code);
1462
1463 /* Calculate final ECC code */
1464 ecc_code[0] = ~ecc_code[0];
1465 ecc_code[1] = ~ecc_code[1];
1466 ecc_code[2] = ((~reg1) << 2) | 0x03;
1467}
1468
1469/*
1470 * Detect and correct a 1 bit error for 256 byte block
1471 */
1472static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
1473{
1474 u_char a, b, c, d1, d2, d3, add, bit, i;
1475
1476 /* Do error detection */
1477 d1 = calc_ecc[0] ^ read_ecc[0];
1478 d2 = calc_ecc[1] ^ read_ecc[1];
1479 d3 = calc_ecc[2] ^ read_ecc[2];
1480
1481 if ((d1 | d2 | d3) == 0) {
1482 /* No errors */
1483 return 0;
1484 }
1485 else {
1486 a = (d1 ^ (d1 >> 1)) & 0x55;
1487 b = (d2 ^ (d2 >> 1)) & 0x55;
1488 c = (d3 ^ (d3 >> 1)) & 0x54;
1489
1490 /* Found and will correct single bit error in the data */
1491 if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
1492 c = 0x80;
1493 add = 0;
1494 a = 0x80;
1495 for (i=0; i<4; i++) {
1496 if (d1 & c)
1497 add |= a;
1498 c >>= 2;
1499 a >>= 1;
1500 }
1501 c = 0x80;
1502 for (i=0; i<4; i++) {
1503 if (d2 & c)
1504 add |= a;
1505 c >>= 2;
1506 a >>= 1;
1507 }
1508 bit = 0;
1509 b = 0x04;
1510 c = 0x80;
1511 for (i=0; i<3; i++) {
1512 if (d3 & c)
1513 bit |= b;
1514 c >>= 2;
1515 b >>= 1;
1516 }
1517 b = 0x01;
1518 a = dat[add];
1519 a ^= (b << bit);
1520 dat[add] = a;
1521 return 1;
1522 }
1523 else {
1524 i = 0;
1525 while (d1) {
1526 if (d1 & 0x01)
1527 ++i;
1528 d1 >>= 1;
1529 }
1530 while (d2) {
1531 if (d2 & 0x01)
1532 ++i;
1533 d2 >>= 1;
1534 }
1535 while (d3) {
1536 if (d3 & 0x01)
1537 ++i;
1538 d3 >>= 1;
1539 }
1540 if (i == 1) {
1541 /* ECC Code Error Correction */
1542 read_ecc[0] = calc_ecc[0];
1543 read_ecc[1] = calc_ecc[1];
1544 read_ecc[2] = calc_ecc[2];
1545 return 2;
1546 }
1547 else {
1548 /* Uncorrectable Error */
1549 return -1;
1550 }
1551 }
1552 }
1553
1554 /* Should never happen */
1555 return -1;
1556}
1557#endif
1558#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */