[people/ms/u-boot.git] / common / cmd_pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI routines
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

#if (CONFIG_COMMANDS & CFG_CMD_PCI)

extern int cmd_get_data_size(char* arg, int default_size);

unsigned char	ShortPCIListing = 1;

/*
 * Follows routines for the output of infos about devices on PCI bus.
 */

void pci_header_show(pci_dev_t dev);
void pci_header_show_brief(pci_dev_t dev);

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *				Depending on the define CFG_SHORT_PCI_LISTING
 *				the output will be more or less exhaustive.
 *
 * Inputs:	bus_no		the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(int BusNum, int ShortPCIListing)
{
	int Device;
	int Function;
	unsigned char HeaderType;
	unsigned short VendorID;
	pci_dev_t dev;

	printf("Scanning PCI devices on bus %d\n", BusNum);

	if (ShortPCIListing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}

	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
		HeaderType = 0;
		VendorID = 0;
		for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
			/*
			 * If this is not a multi-function device, we skip the rest.
			 */
			if (Function && !(HeaderType & 0x80))
				break;

			dev = PCI_BDF(BusNum, Device, Function);

			pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
			if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
				continue;

			if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

			if (ShortPCIListing)
			{
				printf("%02x.%02x.%02x   ", BusNum, Device, Function);
				pci_header_show_brief(dev);
			}
			else
			{
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       BusNum, Device, Function);
				pci_header_show(dev);
			}
	    }
    }
}

static char *pci_classes_str(u8 class)
{
	switch (class) {
	case PCI_CLASS_NOT_DEFINED:
		return "Build before PCI Rev2.0";
		break;
	case PCI_BASE_CLASS_STORAGE:
		return "Mass storage controller";
		break;
	case PCI_BASE_CLASS_NETWORK:
		return "Network controller";
		break;
	case PCI_BASE_CLASS_DISPLAY:
		return "Display controller";
		break;
	case PCI_BASE_CLASS_MULTIMEDIA:
		return "Multimedia device";
		break;
	case PCI_BASE_CLASS_MEMORY:
		return "Memory controller";
		break;
	case PCI_BASE_CLASS_BRIDGE:
		return "Bridge device";
		break;
	case PCI_BASE_CLASS_COMMUNICATION:
		return "Simple comm. controller";
		break;
	case PCI_BASE_CLASS_SYSTEM:
		return "Base system peripheral";
		break;
	case PCI_BASE_CLASS_INPUT:
		return "Input device";
		break;
	case PCI_BASE_CLASS_DOCKING:
		return "Docking station";
		break;
	case PCI_BASE_CLASS_PROCESSOR:
		return "Processor";
		break;
	case PCI_BASE_CLASS_SERIAL:
		return "Serial bus controller";
		break;
	case PCI_BASE_CLASS_INTELLIGENT:
		return "Intelligent controller";
		break;
	case PCI_BASE_CLASS_SATELLITE:
		return "Satellite controller";
		break;
	case PCI_BASE_CLASS_CRYPT:
		return "Cryptographic device";
		break;
	case PCI_BASE_CLASS_SIGNAL_PROCESSING:
		return "DSP";
		break;
	case PCI_CLASS_OTHERS:
		return "Does not fit any class";
		break;
	default:
	return  "???";
		break;
	};
}

/*
 * Subroutine:  pci_header_show_brief
 *
 * Description: Reads and prints the header of the
 * 		specified PCI device in short form.
 *
 * Inputs:	dev      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show_brief(pci_dev_t dev)
{
	u16 vendor, device;
	u8 class, subclass;

	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);

	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
	       vendor, device,
	       pci_classes_str(class), subclass);
}

/*
 * Subroutine:  PCI_Header_Show
 *
 * Description: Reads the header of the specified PCI device.
 *
 * Inputs:		BusDevFunc      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show(pci_dev_t dev)
{
	u8 _byte, header_type;
	u16 _word;
	u32 _dword;

#define PRINT(msg, type, reg) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type)

#define PRINT2(msg, type, reg, func) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type, func(_##type))

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	PRINT ("  vendor ID =                   0x%.4x\n", word, PCI_VENDOR_ID);
	PRINT ("  device ID =                   0x%.4x\n", word, PCI_DEVICE_ID);
	PRINT ("  command register =            0x%.4x\n", word, PCI_COMMAND);
	PRINT ("  status register =             0x%.4x\n", word, PCI_STATUS);
	PRINT ("  revision ID =                 0x%.2x\n", byte, PCI_REVISION_ID);
	PRINT2("  class code =                  0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
								pci_classes_str);
	PRINT ("  sub class code =              0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	PRINT ("  programming interface =       0x%.2x\n", byte, PCI_CLASS_PROG);
	PRINT ("  cache line =                  0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	PRINT ("  latency time =                0x%.2x\n", byte, PCI_LATENCY_TIMER);
	PRINT ("  header type =                 0x%.2x\n", byte, PCI_HEADER_TYPE);
	PRINT ("  BIST =                        0x%.2x\n", byte, PCI_BIST);
	PRINT ("  base address 0 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_0);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  base address 2 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		PRINT ("  base address 3 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		PRINT ("  base address 4 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		PRINT ("  base address 5 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		PRINT ("  cardBus CIS pointer =         0x%.8x\n", dword, PCI_CARDBUS_CIS);
		PRINT ("  sub system vendor ID =        0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		PRINT ("  sub system ID =               0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  min Grant =                   0x%.2x\n", byte, PCI_MIN_GNT);
		PRINT ("  max Latency =                 0x%.2x\n", byte, PCI_MAX_LAT);
		break;

	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */

		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_PRIMARY_BUS);
		PRINT ("  secondary bus number =        0x%.2x\n", byte, PCI_SECONDARY_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
		PRINT ("  secondary latency timer =     0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
		PRINT ("  IO base =                     0x%.2x\n", byte, PCI_IO_BASE);
		PRINT ("  IO limit =                    0x%.2x\n", byte, PCI_IO_LIMIT);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_SEC_STATUS);
		PRINT ("  memory base =                 0x%.4x\n", word, PCI_MEMORY_BASE);
		PRINT ("  memory limit =                0x%.4x\n", word, PCI_MEMORY_LIMIT);
		PRINT ("  prefetch memory base =        0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
		PRINT ("  prefetch memory limit =       0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
		PRINT ("  prefetch memory base upper =  0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
		PRINT ("  prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
		PRINT ("  IO base upper 16 bits =       0x%.4x\n", word, PCI_IO_BASE_UPPER16);
		PRINT ("  IO limit upper 16 bits =      0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS1);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_BRIDGE_CONTROL);
		break;

	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */

		PRINT ("  capabilities =                0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_CB_SEC_STATUS);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
		PRINT ("  CardBus number =              0x%.2x\n", byte, PCI_CB_CARD_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
		PRINT ("  CardBus latency timer =       0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
		PRINT ("  CardBus memory base 0 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
		PRINT ("  CardBus memory limit 0 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
		PRINT ("  CardBus memory base 1 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		PRINT ("  CardBus memory limit 1 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		PRINT ("  CardBus IO base 0 =           0x%.4x\n", word, PCI_CB_IO_BASE_0);
		PRINT ("  CardBus IO base high 0 =      0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		PRINT ("  CardBus IO limit 0 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		PRINT ("  CardBus IO limit high 0 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		PRINT ("  CardBus IO base 1 =           0x%.4x\n", word, PCI_CB_IO_BASE_1);
		PRINT ("  CardBus IO base high 1 =      0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		PRINT ("  CardBus IO limit 1 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		PRINT ("  CardBus IO limit high 1 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		PRINT ("  subvendor ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		PRINT ("  subdevice ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		PRINT ("  PC Card 16bit base address =  0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		break;

	default:
		printf("unknown header\n");
		break;
    }

#undef PRINT
#undef PRINT2
}

/* Convert the "bus.device.function" identifier into a number.
 */
static pci_dev_t get_pci_dev(char* name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = simple_strtoul(cnum, NULL, 16);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int rc = 0;

	if (length == 0)
		length = 0x40 / size; /* Standard PCI configuration space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * size;
	do {
		uint	val4;
		ushort  val2;
		u_char	val1;

		printf("%08lx:", addr);
		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
		for (i=0; i<linebytes; i+= size) {
			if (size == 4) {
				pci_read_config_dword(bdf, addr, &val4);
				printf(" %08x", val4);
			} else if (size == 2) {
				pci_read_config_word(bdf, addr, &val2);
				printf(" %04x", val2);
			} else {
				pci_read_config_byte(bdf, addr, &val1);
				printf(" %02x", val1);
			}
			addr += size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
	if (size == 4) {
		pci_write_config_dword(bdf, addr, value);
	}
	else if (size == 2) {
		ushort val = value & 0xffff;
		pci_write_config_word(bdf, addr, val);
	}
	else {
		u_char val = value & 0xff;
		pci_write_config_byte(bdf, addr, val);
	}
	return 0;
}

static int
pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	extern char console_buffer[];
	uint	val4;
	ushort  val2;
	u_char	val1;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		if (size == 4) {
			pci_read_config_dword(bdf, addr, &val4);
			printf(" %08x", val4);
		}
		else if (size == 2) {
			pci_read_config_word(bdf, addr, &val2);
			printf(" %04x", val2);
		}
		else {
			pci_read_config_byte(bdf, addr, &val1);
			printf(" %02x", val1);
		}

		nbytes = readline (" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
#ifdef CONFIG_BOOT_RETRY_TIME
			reset_cmd_timeout(); /* good enough to not time out */
#endif
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = simple_strtoul(console_buffer, &endp, 16);
			nbytes = endp - console_buffer;
			if (nbytes) {
#ifdef CONFIG_BOOT_RETRY_TIME
				/* good enough to not time out
				 */
				reset_cmd_timeout();
#endif
				pci_cfg_write (bdf, addr, size, i);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong addr = 0, value = 0, size = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		size = cmd_get_data_size(argv[1], 4);
		if (argc > 3)
			addr = simple_strtoul(argv[3], NULL, 16);
		if (argc > 4)
			value = simple_strtoul(argv[4], NULL, 16);
	case 'h':		/* header */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
	default:		/* scan bus */
		value = 1; /* short listing */
		bdf = 0;   /* bus number  */
		if (argc > 1) {
			if (argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				bdf = simple_strtoul(argv[1], NULL, 16);
		}
		pciinfo(bdf, value);
		return 0;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(bdf);
		return 0;
	case 'd':		/* display */
		return pci_cfg_display(bdf, addr, size, value);
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 0);
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 1);
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		return pci_cfg_write(bdf, addr, size, value);
	}

	return 1;
 usage:
	printf ("Usage:\n%s\n", cmdtp->usage);
	return 1;
}

/***************************************************/


U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"pci     - list and access PCI Configuration Space\n",
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address\n"
);

#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */

#endif /* CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
	5	* (C) Copyright 2002
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	/*
	29	* PCI routines
	30	*/
	31
	32	#include <common.h>
	33
	34	#ifdef CONFIG_PCI
	35
	36	#include <command.h>
c609719b WD	37	#include <asm/processor.h>
c609719b WD	38	#include <asm/io.h>
c609719b WD	39	#include <pci.h>
	40
	41	#if (CONFIG_COMMANDS & CFG_CMD_PCI)
	42
	43	extern int cmd_get_data_size(char* arg, int default_size);
	44
	45	unsigned char ShortPCIListing = 1;
	46
	47	/*
	48	* Follows routines for the output of infos about devices on PCI bus.
	49	*/
	50
	51	void pci_header_show(pci_dev_t dev);
	52	void pci_header_show_brief(pci_dev_t dev);
	53
	54	/*
	55	* Subroutine: pciinfo
	56	*
	57	* Description: Show information about devices on PCI bus.
	58	* Depending on the define CFG_SHORT_PCI_LISTING
	59	* the output will be more or less exhaustive.
	60	*
	61	* Inputs: bus_no the number of the bus to be scanned.
	62	*
	63	* Return: None
	64	*
	65	*/
	66	void pciinfo(int BusNum, int ShortPCIListing)
	67	{
	68	int Device;
	69	int Function;
	70	unsigned char HeaderType;
	71	unsigned short VendorID;
	72	pci_dev_t dev;
	73
	74	printf("Scanning PCI devices on bus %d\n", BusNum);
	75
	76	if (ShortPCIListing) {
	77	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	78	printf("_____________________________________________________________\n");
	79	}
	80
	81	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
	82	HeaderType = 0;
	83	VendorID = 0;
	84	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
	85	/*
	86	* If this is not a multi-function device, we skip the rest.
	87	*/
	88	if (Function && !(HeaderType & 0x80))
	89	break;
	90
	91	dev = PCI_BDF(BusNum, Device, Function);
	92
	93	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
	94	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
	95	continue;
	96
c7de829c	97	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
c609719b WD	98
	99	if (ShortPCIListing)
	100	{
	101	printf("%02x.%02x.%02x ", BusNum, Device, Function);
	102	pci_header_show_brief(dev);
	103	}
	104	else
	105	{
	106	printf("\nFound PCI device %02x.%02x.%02x:\n",
	107	BusNum, Device, Function);
	108	pci_header_show(dev);
	109	}
	110	}
	111	}
	112	}
	113
5d232d0e	114	static char *pci_classes_str(u8 class)
c609719b	115	{
06d01dbe	116	switch (class) {
8bde7f77 WD	117	case PCI_CLASS_NOT_DEFINED:
	118	return "Build before PCI Rev2.0";
	119	break;
	120	case PCI_BASE_CLASS_STORAGE:
	121	return "Mass storage controller";
	122	break;
	123	case PCI_BASE_CLASS_NETWORK:
	124	return "Network controller";
	125	break;
	126	case PCI_BASE_CLASS_DISPLAY:
	127	return "Display controller";
	128	break;
	129	case PCI_BASE_CLASS_MULTIMEDIA:
	130	return "Multimedia device";
	131	break;
	132	case PCI_BASE_CLASS_MEMORY:
	133	return "Memory controller";
	134	break;
	135	case PCI_BASE_CLASS_BRIDGE:
	136	return "Bridge device";
	137	break;
	138	case PCI_BASE_CLASS_COMMUNICATION:
	139	return "Simple comm. controller";
	140	break;
	141	case PCI_BASE_CLASS_SYSTEM:
	142	return "Base system peripheral";
	143	break;
	144	case PCI_BASE_CLASS_INPUT:
	145	return "Input device";
	146	break;
	147	case PCI_BASE_CLASS_DOCKING:
	148	return "Docking station";
	149	break;
	150	case PCI_BASE_CLASS_PROCESSOR:
	151	return "Processor";
	152	break;
	153	case PCI_BASE_CLASS_SERIAL:
	154	return "Serial bus controller";
	155	break;
	156	case PCI_BASE_CLASS_INTELLIGENT:
	157	return "Intelligent controller";
	158	break;
	159	case PCI_BASE_CLASS_SATELLITE:
	160	return "Satellite controller";
	161	break;
	162	case PCI_BASE_CLASS_CRYPT:
	163	return "Cryptographic device";
	164	break;
	165	case PCI_BASE_CLASS_SIGNAL_PROCESSING:
	166	return "DSP";
	167	break;
	168	case PCI_CLASS_OTHERS:
	169	return "Does not fit any class";
	170	break;
	171	default:
5d232d0e	172	return "???";
8bde7f77	173	break;
06d01dbe	174	};
c609719b WD	175	}
	176
	177	/*
	178	* Subroutine: pci_header_show_brief
	179	*
	180	* Description: Reads and prints the header of the
	181	* specified PCI device in short form.
	182	*
	183	* Inputs: dev Bus+Device+Function number
	184	*
	185	* Return: None
	186	*
	187	*/
	188	void pci_header_show_brief(pci_dev_t dev)
	189	{
	190	u16 vendor, device;
	191	u8 class, subclass;
	192
	193	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	194	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	195	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	196	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
	197
5d232d0e	198	printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
c609719b WD	199	vendor, device,
	200	pci_classes_str(class), subclass);
	201	}
	202
	203	/*
	204	* Subroutine: PCI_Header_Show
	205	*
	206	* Description: Reads the header of the specified PCI device.
	207	*
	208	* Inputs: BusDevFunc Bus+Device+Function number
	209	*
	210	* Return: None
	211	*
	212	*/
	213	void pci_header_show(pci_dev_t dev)
	214	{
	215	u8 _byte, header_type;
	216	u16 _word;
	217	u32 _dword;
	218
	219	#define PRINT(msg, type, reg) \
	220	pci_read_config_##type(dev, reg, &_##type); \
	221	printf(msg, _##type)
	222
	223	#define PRINT2(msg, type, reg, func) \
	224	pci_read_config_##type(dev, reg, &_##type); \
	225	printf(msg, _##type, func(_##type))
	226
	227	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	228
	229	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
	230	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
	231	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
	232	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
	233	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
	234	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
8bde7f77	235	pci_classes_str);
c609719b WD	236	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	237	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
	238	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	239	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
	240	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
	241	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
	242	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
c609719b	243
7c7a23bd WD	244	switch (header_type & 0x03) {
	245	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
	246	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
	247	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
	248	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
	249	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
	250	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
	251	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
	252	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
	253	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
	254	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
	255	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	256	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	257	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
	258	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
	259	break;
8bde7f77	260
7c7a23bd WD	261	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
	262
	263	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
c609719b WD	264	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
	265	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
	266	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
	267	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
	268	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
	269	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
	270	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
	271	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
	272	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
	273	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
	274	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
	275	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
	276	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
	277	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
	278	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
	279	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
	280	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	281	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	282	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
7c7a23bd WD	283	break;
	284
	285	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
	286
	287	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
	288	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
	289	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
	290	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
	291	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
8bde7f77	292	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
7c7a23bd WD	293	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
	294	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
	295	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
	296	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
	297	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
	298	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
	299	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
	300	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
	301	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
	302	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
	303	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
	304	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
	305	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	306	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	307	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
	308	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
	309	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
	310	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
	311	break;
8bde7f77	312
7c7a23bd WD	313	default:
7c7a23bd WD	314	printf("unknown header\n");
8bde7f77	315	break;
c609719b WD	316	}
	317
	318	#undef PRINT
	319	#undef PRINT2
	320	}
	321
	322	/* Convert the "bus.device.function" identifier into a number.
	323	*/
	324	static pci_dev_t get_pci_dev(char* name)
	325	{
	326	char cnum[12];
	327	int len, i, iold, n;
	328	int bdfs[3] = {0,0,0};
	329
	330	len = strlen(name);
	331	if (len > 8)
	332	return -1;
	333	for (i = 0, iold = 0, n = 0; i < len; i++) {
	334	if (name[i] == '.') {
	335	memcpy(cnum, &name[iold], i - iold);
	336	cnum[i - iold] = '\0';
	337	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
	338	iold = i + 1;
	339	}
	340	}
	341	strcpy(cnum, &name[iold]);
	342	if (n == 0)
	343	n = 1;
	344	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	345	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	346	}
	347
	348	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
	349	{
	350	#define DISP_LINE_LEN 16
	351	ulong i, nbytes, linebytes;
	352	int rc = 0;
	353
	354	if (length == 0)
	355	length = 0x40 / size; /* Standard PCI configuration space */
	356
	357	/* Print the lines.
	358	* once, and all accesses are with the specified bus width.
	359	*/
	360	nbytes = length * size;
	361	do {
	362	uint val4;
	363	ushort val2;
	364	u_char val1;
	365
	366	printf("%08lx:", addr);
	367	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
	368	for (i=0; i<linebytes; i+= size) {
	369	if (size == 4) {
	370	pci_read_config_dword(bdf, addr, &val4);
	371	printf(" %08x", val4);
	372	} else if (size == 2) {
	373	pci_read_config_word(bdf, addr, &val2);
	374	printf(" %04x", val2);
	375	} else {
	376	pci_read_config_byte(bdf, addr, &val1);
	377	printf(" %02x", val1);
	378	}
	379	addr += size;
380	}
381	printf("\n");
382	nbytes -= linebytes;
383	if (ctrlc()) {
384	rc = 1;
385	break;
386	}
387	} while (nbytes > 0);
388
389	return (rc);
390	}
391
392	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
393	{
394	if (size == 4) {
395	pci_write_config_dword(bdf, addr, value);
396	}
397	else if (size == 2) {
398	ushort val = value & 0xffff;
399	pci_write_config_word(bdf, addr, val);
400	}
401	else {
402	u_char val = value & 0xff;
403	pci_write_config_byte(bdf, addr, val);
404	}
405	return 0;
406	}
407
408	static int
409	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
410	{
411	ulong i;
412	int nbytes;
413	extern char console_buffer[];
414	uint val4;
415	ushort val2;
416	u_char val1;
417
418	/* Print the address, followed by value. Then accept input for
419	* the next value. A non-converted value exits.
420	*/
421	do {
422	printf("%08lx:", addr);
423	if (size == 4) {
424	pci_read_config_dword(bdf, addr, &val4);
425	printf(" %08x", val4);
426	}
427	else if (size == 2) {
428	pci_read_config_word(bdf, addr, &val2);
429	printf(" %04x", val2);
430	}
431	else {
432	pci_read_config_byte(bdf, addr, &val1);
433	printf(" %02x", val1);
434	}
435
436	nbytes = readline (" ? ");
437	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
438	/* <CR> pressed as only input, don't modify current
439	* location and move to next. "-" pressed will go back.
440	*/
441	if (incrflag)
442	addr += nbytes ? -size : size;
443	nbytes = 1;
444	#ifdef CONFIG_BOOT_RETRY_TIME
445	reset_cmd_timeout(); /* good enough to not time out */
446	#endif
447	}
448	#ifdef CONFIG_BOOT_RETRY_TIME
449	else if (nbytes == -2) {
450	break; /* timed out, exit the command */
451	}
452	#endif
453	else {
454	char *endp;
455	i = simple_strtoul(console_buffer, &endp, 16);
456	nbytes = endp - console_buffer;
457	if (nbytes) {
458	#ifdef CONFIG_BOOT_RETRY_TIME
459	/* good enough to not time out
460	*/
461	reset_cmd_timeout();
462	#endif
463	pci_cfg_write (bdf, addr, size, i);
464	if (incrflag)
465	addr += size;
466	}
467	}
468	} while (nbytes);
469
470	return 0;
471	}
472
473	/* PCI Configuration Space access commands
474	*
475	* Syntax:
476	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
477	* pci next[.b, .w, .l] bus.device.function [addr]
478	* pci modify[.b, .w, .l] bus.device.function [addr]
479	* pci write[.b, .w, .l] bus.device.function addr value
480	*/
481	int do_pci (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
482	{
483	ulong addr = 0, value = 0, size = 0;
484	pci_dev_t bdf = 0;
485	char cmd = 's';
486
487	if (argc > 1)
488	cmd = argv[1][0];
489
490	switch (cmd) {
491	case 'd': /* display */
492	case 'n': /* next */
493	case 'm': /* modify */
494	case 'w': /* write */
495	/* Check for a size specification. */
496	size = cmd_get_data_size(argv[1], 4);
497	if (argc > 3)
498	addr = simple_strtoul(argv[3], NULL, 16);
499	if (argc > 4)
500	value = simple_strtoul(argv[4], NULL, 16);
501	case 'h': /* header */
502	if (argc < 3)
503	goto usage;
504	if ((bdf = get_pci_dev(argv[2])) == -1)
505	return 1;
506	break;
507	default: /* scan bus */
508	value = 1; /* short listing */
509	bdf = 0; /* bus number */
510	if (argc > 1) {
511	if (argv[argc-1][0] == 'l') {
512	value = 0;
513	argc--;
514	}
515	if (argc > 1)
516	bdf = simple_strtoul(argv[1], NULL, 16);
517	}
518	pciinfo(bdf, value);
519	return 0;
520	}
521
522	switch (argv[1][0]) {
523	case 'h': /* header */
524	pci_header_show(bdf);
525	return 0;
526	case 'd': /* display */
527	return pci_cfg_display(bdf, addr, size, value);
528	case 'n': /* next */
529	if (argc < 4)
530	goto usage;
531	return pci_cfg_modify(bdf, addr, size, value, 0);
532	case 'm': /* modify */
533	if (argc < 4)
534	goto usage;
535	return pci_cfg_modify(bdf, addr, size, value, 1);
536	case 'w': /* write */
537	if (argc < 5)
538	goto usage;
539	return pci_cfg_write(bdf, addr, size, value);
540	}
541
542	return 1;
543	usage:
544	printf ("Usage:\n%s\n", cmdtp->usage);
545	return 1;
546	}
547
8bde7f77 WD	548	/***************************************************/
	549
	550
0d498393 WD	551	U_BOOT_CMD(
0d498393 WD	552	pci, 5, 1, do_pci,
256d31c0	553	"pci - list and access PCI Configuration Space\n",
8bde7f77 WD	554	"[bus] [long]\n"
	555	" - short or long list of PCI devices on bus 'bus'\n"
	556	"pci header b.d.f\n"
	557	" - show header of PCI device 'bus.device.function'\n"
	558	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	559	" - display PCI configuration space (CFG)\n"
	560	"pci next[.b, .w, .l] b.d.f address\n"
	561	" - modify, read and keep CFG address\n"
	562	"pci modify[.b, .w, .l] b.d.f address\n"
	563	" - modify, auto increment CFG address\n"
	564	"pci write[.b, .w, .l] b.d.f address value\n"
	565	" - write to CFG address\n"
	566	);
	567
c609719b WD	568	#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */
	569
	570	#endif /* CONFIG_PCI */