[people/ms/u-boot.git] / common / cmd_pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * PCI routines
 */

#include <common.h>
#include <bootretry.h>
#include <cli.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

/*
 * Follows routines for the output of infos about devices on PCI bus.
 */

void pci_header_show(pci_dev_t dev);
void pci_header_show_brief(pci_dev_t dev);

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *				Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
 *				the output will be more or less exhaustive.
 *
 * Inputs:	bus_no		the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(int BusNum, int ShortPCIListing)
{
	struct pci_controller *hose = pci_bus_to_hose(BusNum);
	int Device;
	int Function;
	unsigned char HeaderType;
	unsigned short VendorID;
	pci_dev_t dev;

	if (!hose)
		return;

	printf("Scanning PCI devices on bus %d\n", BusNum);

	if (ShortPCIListing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}

	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
		HeaderType = 0;
		VendorID = 0;
		for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
			/*
			 * If this is not a multi-function device, we skip the rest.
			 */
			if (Function && !(HeaderType & 0x80))
				break;

			dev = PCI_BDF(BusNum, Device, Function);

			if (pci_skip_dev(hose, dev))
				continue;

			pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
			if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
				continue;

			if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

			if (ShortPCIListing)
			{
				printf("%02x.%02x.%02x   ", BusNum, Device, Function);
				pci_header_show_brief(dev);
			}
			else
			{
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       BusNum, Device, Function);
				pci_header_show(dev);
			}
	    }
    }
}


/*
 * Subroutine:  pci_header_show_brief
 *
 * Description: Reads and prints the header of the
 *		specified PCI device in short form.
 *
 * Inputs:	dev      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show_brief(pci_dev_t dev)
{
	u16 vendor, device;
	u8 class, subclass;

	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);

	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
	       vendor, device,
	       pci_class_str(class), subclass);
}

/*
 * Subroutine:  PCI_Header_Show
 *
 * Description: Reads the header of the specified PCI device.
 *
 * Inputs:		BusDevFunc      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show(pci_dev_t dev)
{
	u8 _byte, header_type;
	u16 _word;
	u32 _dword;

#define PRINT(msg, type, reg) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type)

#define PRINT2(msg, type, reg, func) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type, func(_##type))

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	PRINT ("  vendor ID =                   0x%.4x\n", word, PCI_VENDOR_ID);
	PRINT ("  device ID =                   0x%.4x\n", word, PCI_DEVICE_ID);
	PRINT ("  command register =            0x%.4x\n", word, PCI_COMMAND);
	PRINT ("  status register =             0x%.4x\n", word, PCI_STATUS);
	PRINT ("  revision ID =                 0x%.2x\n", byte, PCI_REVISION_ID);
	PRINT2("  class code =                  0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
								pci_class_str);
	PRINT ("  sub class code =              0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	PRINT ("  programming interface =       0x%.2x\n", byte, PCI_CLASS_PROG);
	PRINT ("  cache line =                  0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	PRINT ("  latency time =                0x%.2x\n", byte, PCI_LATENCY_TIMER);
	PRINT ("  header type =                 0x%.2x\n", byte, PCI_HEADER_TYPE);
	PRINT ("  BIST =                        0x%.2x\n", byte, PCI_BIST);
	PRINT ("  base address 0 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_0);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  base address 2 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		PRINT ("  base address 3 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		PRINT ("  base address 4 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		PRINT ("  base address 5 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		PRINT ("  cardBus CIS pointer =         0x%.8x\n", dword, PCI_CARDBUS_CIS);
		PRINT ("  sub system vendor ID =        0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		PRINT ("  sub system ID =               0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  min Grant =                   0x%.2x\n", byte, PCI_MIN_GNT);
		PRINT ("  max Latency =                 0x%.2x\n", byte, PCI_MAX_LAT);
		break;

	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */

		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_PRIMARY_BUS);
		PRINT ("  secondary bus number =        0x%.2x\n", byte, PCI_SECONDARY_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
		PRINT ("  secondary latency timer =     0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
		PRINT ("  IO base =                     0x%.2x\n", byte, PCI_IO_BASE);
		PRINT ("  IO limit =                    0x%.2x\n", byte, PCI_IO_LIMIT);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_SEC_STATUS);
		PRINT ("  memory base =                 0x%.4x\n", word, PCI_MEMORY_BASE);
		PRINT ("  memory limit =                0x%.4x\n", word, PCI_MEMORY_LIMIT);
		PRINT ("  prefetch memory base =        0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
		PRINT ("  prefetch memory limit =       0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
		PRINT ("  prefetch memory base upper =  0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
		PRINT ("  prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
		PRINT ("  IO base upper 16 bits =       0x%.4x\n", word, PCI_IO_BASE_UPPER16);
		PRINT ("  IO limit upper 16 bits =      0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS1);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_BRIDGE_CONTROL);
		break;

	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */

		PRINT ("  capabilities =                0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_CB_SEC_STATUS);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
		PRINT ("  CardBus number =              0x%.2x\n", byte, PCI_CB_CARD_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
		PRINT ("  CardBus latency timer =       0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
		PRINT ("  CardBus memory base 0 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
		PRINT ("  CardBus memory limit 0 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
		PRINT ("  CardBus memory base 1 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		PRINT ("  CardBus memory limit 1 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		PRINT ("  CardBus IO base 0 =           0x%.4x\n", word, PCI_CB_IO_BASE_0);
		PRINT ("  CardBus IO base high 0 =      0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		PRINT ("  CardBus IO limit 0 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		PRINT ("  CardBus IO limit high 0 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		PRINT ("  CardBus IO base 1 =           0x%.4x\n", word, PCI_CB_IO_BASE_1);
		PRINT ("  CardBus IO base high 1 =      0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		PRINT ("  CardBus IO limit 1 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		PRINT ("  CardBus IO limit high 1 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		PRINT ("  subvendor ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		PRINT ("  subdevice ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		PRINT ("  PC Card 16bit base address =  0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		break;

	default:
		printf("unknown header\n");
		break;
    }

#undef PRINT
#undef PRINT2
}

/* Convert the "bus.device.function" identifier into a number.
 */
static pci_dev_t get_pci_dev(char* name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = simple_strtoul(cnum, NULL, 16);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int rc = 0;

	if (length == 0)
		length = 0x40 / size; /* Standard PCI configuration space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * size;
	do {
		uint	val4;
		ushort  val2;
		u_char	val1;

		printf("%08lx:", addr);
		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
		for (i=0; i<linebytes; i+= size) {
			if (size == 4) {
				pci_read_config_dword(bdf, addr, &val4);
				printf(" %08x", val4);
			} else if (size == 2) {
				pci_read_config_word(bdf, addr, &val2);
				printf(" %04x", val2);
			} else {
				pci_read_config_byte(bdf, addr, &val1);
				printf(" %02x", val1);
			}
			addr += size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
	if (size == 4) {
		pci_write_config_dword(bdf, addr, value);
	}
	else if (size == 2) {
		ushort val = value & 0xffff;
		pci_write_config_word(bdf, addr, val);
	}
	else {
		u_char val = value & 0xff;
		pci_write_config_byte(bdf, addr, val);
	}
	return 0;
}

static int
pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	uint	val4;
	ushort  val2;
	u_char	val1;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		if (size == 4) {
			pci_read_config_dword(bdf, addr, &val4);
			printf(" %08x", val4);
		}
		else if (size == 2) {
			pci_read_config_word(bdf, addr, &val2);
			printf(" %04x", val2);
		}
		else {
			pci_read_config_byte(bdf, addr, &val1);
			printf(" %02x", val1);
		}

		nbytes = cli_readline(" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
			/* good enough to not time out */
			bootretry_reset_cmd_timeout();
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = simple_strtoul(console_buffer, &endp, 16);
			nbytes = endp - console_buffer;
			if (nbytes) {
				/* good enough to not time out
				 */
				bootretry_reset_cmd_timeout();
				pci_cfg_write (bdf, addr, size, i);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong addr = 0, value = 0, size = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		size = cmd_get_data_size(argv[1], 4);
		if (argc > 3)
			addr = simple_strtoul(argv[3], NULL, 16);
		if (argc > 4)
			value = simple_strtoul(argv[4], NULL, 16);
	case 'h':		/* header */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		break;
#endif
	default:		/* scan bus */
		value = 1; /* short listing */
		bdf = 0;   /* bus number  */
		if (argc > 1) {
			if (argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				bdf = simple_strtoul(argv[1], NULL, 16);
		}
		pciinfo(bdf, value);
		return 0;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(bdf);
		return 0;
	case 'd':		/* display */
		return pci_cfg_display(bdf, addr, size, value);
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		pci_init();
		return 0;
#endif
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 0);
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 1);
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		return pci_cfg_write(bdf, addr, size, value);
	}

	return 1;
 usage:
	return CMD_RET_USAGE;
}

/***************************************************/

#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
#ifdef CONFIG_CMD_PCI_ENUM
	"pci enum\n"
	"    - re-enumerate PCI buses\n"
#endif
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address";
#endif

U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"list and access PCI Configuration Space", pci_help_text
);
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
	5	* (C) Copyright 2002
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	10	*/
	11
	12	/*
	13	* PCI routines
	14	*/
	15
	16	#include <common.h>
0098e179	17	#include <bootretry.h>
18d66533	18	#include <cli.h>
c609719b	19	#include <command.h>
c609719b WD	20	#include <asm/processor.h>
c609719b WD	21	#include <asm/io.h>
c609719b WD	22	#include <pci.h>
c609719b WD	23
c609719b WD	24	/*
	25	* Follows routines for the output of infos about devices on PCI bus.
	26	*/
	27
	28	void pci_header_show(pci_dev_t dev);
	29	void pci_header_show_brief(pci_dev_t dev);
	30
	31	/*
	32	* Subroutine: pciinfo
	33	*
	34	* Description: Show information about devices on PCI bus.
6d0f6bcf	35	* Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
c609719b WD	36	* the output will be more or less exhaustive.
	37	*
	38	* Inputs: bus_no the number of the bus to be scanned.
	39	*
	40	* Return: None
	41	*
	42	*/
	43	void pciinfo(int BusNum, int ShortPCIListing)
	44	{
042b83d4	45	struct pci_controller *hose = pci_bus_to_hose(BusNum);
c609719b WD	46	int Device;
	47	int Function;
	48	unsigned char HeaderType;
	49	unsigned short VendorID;
	50	pci_dev_t dev;
	51
042b83d4 TR	52	if (!hose)
	53	return;
	54
c609719b WD	55	printf("Scanning PCI devices on bus %d\n", BusNum);
	56
	57	if (ShortPCIListing) {
	58	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	59	printf("_____________________________________________________________\n");
	60	}
	61
	62	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
	63	HeaderType = 0;
	64	VendorID = 0;
	65	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
	66	/*
	67	* If this is not a multi-function device, we skip the rest.
	68	*/
	69	if (Function && !(HeaderType & 0x80))
	70	break;
	71
	72	dev = PCI_BDF(BusNum, Device, Function);
	73
4efe52bf TR	74	if (pci_skip_dev(hose, dev))
	75	continue;
	76
c609719b WD	77	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
	78	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
	79	continue;
	80
c7de829c	81	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
c609719b WD	82
	83	if (ShortPCIListing)
	84	{
	85	printf("%02x.%02x.%02x ", BusNum, Device, Function);
	86	pci_header_show_brief(dev);
	87	}
	88	else
	89	{
	90	printf("\nFound PCI device %02x.%02x.%02x:\n",
	91	BusNum, Device, Function);
	92	pci_header_show(dev);
	93	}
	94	}
	95	}
	96	}
	97
c609719b WD	98
	99	/*
	100	* Subroutine: pci_header_show_brief
	101	*
	102	* Description: Reads and prints the header of the
53677ef1	103	* specified PCI device in short form.
c609719b WD	104	*
	105	* Inputs: dev Bus+Device+Function number
	106	*
	107	* Return: None
	108	*
	109	*/
	110	void pci_header_show_brief(pci_dev_t dev)
	111	{
	112	u16 vendor, device;
	113	u8 class, subclass;
	114
	115	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	116	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	117	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	118	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
	119
5d232d0e	120	printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
c609719b	121	vendor, device,
983eb9d1	122	pci_class_str(class), subclass);
c609719b WD	123	}
	124
	125	/*
	126	* Subroutine: PCI_Header_Show
	127	*
	128	* Description: Reads the header of the specified PCI device.
	129	*
	130	* Inputs: BusDevFunc Bus+Device+Function number
	131	*
	132	* Return: None
	133	*
	134	*/
	135	void pci_header_show(pci_dev_t dev)
	136	{
	137	u8 _byte, header_type;
	138	u16 _word;
	139	u32 _dword;
	140
	141	#define PRINT(msg, type, reg) \
	142	pci_read_config_##type(dev, reg, &_##type); \
	143	printf(msg, _##type)
	144
	145	#define PRINT2(msg, type, reg, func) \
	146	pci_read_config_##type(dev, reg, &_##type); \
	147	printf(msg, _##type, func(_##type))
	148
	149	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	150
	151	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
	152	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
	153	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
	154	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
	155	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
	156	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
983eb9d1	157	pci_class_str);
c609719b WD	158	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	159	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
	160	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	161	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
	162	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
	163	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
	164	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
c609719b	165
7c7a23bd WD	166	switch (header_type & 0x03) {
	167	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
	168	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
	169	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
	170	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
	171	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
	172	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
	173	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
	174	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
	175	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
	176	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
	177	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	178	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	179	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
	180	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
	181	break;
8bde7f77	182
7c7a23bd WD	183	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
	184
	185	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
c609719b WD	186	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
	187	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
	188	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
	189	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
	190	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
	191	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
	192	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
	193	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
	194	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
	195	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
	196	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
	197	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
	198	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
	199	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
	200	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
	201	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
	202	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	203	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	204	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
7c7a23bd WD	205	break;
	206
	207	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
	208
	209	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
	210	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
	211	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
	212	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
	213	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
8bde7f77	214	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
7c7a23bd WD	215	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
	216	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
	217	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
	218	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
	219	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
	220	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
	221	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
	222	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
	223	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
	224	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
	225	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
	226	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
	227	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	228	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	229	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
	230	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
	231	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
	232	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
	233	break;
8bde7f77	234
7c7a23bd WD	235	default:
7c7a23bd WD	236	printf("unknown header\n");
8bde7f77	237	break;
c609719b WD	238	}
	239
	240	#undef PRINT
	241	#undef PRINT2
	242	}
	243
	244	/* Convert the "bus.device.function" identifier into a number.
	245	*/
	246	static pci_dev_t get_pci_dev(char* name)
	247	{
	248	char cnum[12];
	249	int len, i, iold, n;
	250	int bdfs[3] = {0,0,0};
	251
	252	len = strlen(name);
	253	if (len > 8)
	254	return -1;
	255	for (i = 0, iold = 0, n = 0; i < len; i++) {
	256	if (name[i] == '.') {
	257	memcpy(cnum, &name[iold], i - iold);
	258	cnum[i - iold] = '\0';
	259	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
	260	iold = i + 1;
	261	}
	262	}
	263	strcpy(cnum, &name[iold]);
	264	if (n == 0)
	265	n = 1;
	266	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	267	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	268	}
	269
	270	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
	271	{
	272	#define DISP_LINE_LEN 16
	273	ulong i, nbytes, linebytes;
	274	int rc = 0;
	275
	276	if (length == 0)
	277	length = 0x40 / size; /* Standard PCI configuration space */
	278
	279	/* Print the lines.
	280	* once, and all accesses are with the specified bus width.
	281	*/
	282	nbytes = length * size;
	283	do {
	284	uint val4;
	285	ushort val2;
	286	u_char val1;
	287
	288	printf("%08lx:", addr);
	289	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
	290	for (i=0; i<linebytes; i+= size) {
	291	if (size == 4) {
	292	pci_read_config_dword(bdf, addr, &val4);
	293	printf(" %08x", val4);
	294	} else if (size == 2) {
	295	pci_read_config_word(bdf, addr, &val2);
	296	printf(" %04x", val2);
	297	} else {
	298	pci_read_config_byte(bdf, addr, &val1);
	299	printf(" %02x", val1);
	300	}
	301	addr += size;
302	}
303	printf("\n");
304	nbytes -= linebytes;
305	if (ctrlc()) {
306	rc = 1;
307	break;
308	}
309	} while (nbytes > 0);
310
311	return (rc);
312	}
313
314	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
315	{
316	if (size == 4) {
317	pci_write_config_dword(bdf, addr, value);
318	}
319	else if (size == 2) {
320	ushort val = value & 0xffff;
321	pci_write_config_word(bdf, addr, val);
322	}
323	else {
324	u_char val = value & 0xff;
325	pci_write_config_byte(bdf, addr, val);
326	}
327	return 0;
328	}
329
330	static int
331	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
332	{
333	ulong i;
334	int nbytes;
c609719b WD	335	uint val4;
	336	ushort val2;
	337	u_char val1;
	338
	339	/* Print the address, followed by value. Then accept input for
	340	* the next value. A non-converted value exits.
	341	*/
	342	do {
	343	printf("%08lx:", addr);
	344	if (size == 4) {
	345	pci_read_config_dword(bdf, addr, &val4);
	346	printf(" %08x", val4);
	347	}
	348	else if (size == 2) {
	349	pci_read_config_word(bdf, addr, &val2);
	350	printf(" %04x", val2);
	351	}
	352	else {
	353	pci_read_config_byte(bdf, addr, &val1);
	354	printf(" %02x", val1);
	355	}
	356
e1bf824d	357	nbytes = cli_readline(" ? ");
c609719b WD	358	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
	359	/* <CR> pressed as only input, don't modify current
	360	* location and move to next. "-" pressed will go back.
	361	*/
	362	if (incrflag)
	363	addr += nbytes ? -size : size;
	364	nbytes = 1;
b26440f1 SG	365	/* good enough to not time out */
b26440f1 SG	366	bootretry_reset_cmd_timeout();
c609719b WD	367	}
	368	#ifdef CONFIG_BOOT_RETRY_TIME
	369	else if (nbytes == -2) {
	370	break; /* timed out, exit the command */
	371	}
	372	#endif
	373	else {
	374	char *endp;
	375	i = simple_strtoul(console_buffer, &endp, 16);
	376	nbytes = endp - console_buffer;
	377	if (nbytes) {
c609719b WD	378	/* good enough to not time out
c609719b WD	379	*/
b26440f1	380	bootretry_reset_cmd_timeout();
c609719b WD	381	pci_cfg_write (bdf, addr, size, i);
	382	if (incrflag)
	383	addr += size;
	384	}
	385	}
	386	} while (nbytes);
	387
	388	return 0;
	389	}
	390
	391	/* PCI Configuration Space access commands
	392	*
	393	* Syntax:
	394	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
	395	* pci next[.b, .w, .l] bus.device.function [addr]
	396	* pci modify[.b, .w, .l] bus.device.function [addr]
	397	* pci write[.b, .w, .l] bus.device.function addr value
	398	*/
088f1b19	399	static int do_pci(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
c609719b WD	400	{
	401	ulong addr = 0, value = 0, size = 0;
	402	pci_dev_t bdf = 0;
	403	char cmd = 's';
	404
	405	if (argc > 1)
	406	cmd = argv[1][0];
	407
	408	switch (cmd) {
	409	case 'd': /* display */
	410	case 'n': /* next */
	411	case 'm': /* modify */
	412	case 'w': /* write */
	413	/* Check for a size specification. */
	414	size = cmd_get_data_size(argv[1], 4);
	415	if (argc > 3)
	416	addr = simple_strtoul(argv[3], NULL, 16);
	417	if (argc > 4)
	418	value = simple_strtoul(argv[4], NULL, 16);
	419	case 'h': /* header */
	420	if (argc < 3)
	421	goto usage;
	422	if ((bdf = get_pci_dev(argv[2])) == -1)
	423	return 1;
	424	break;
96d61603 JS	425	#ifdef CONFIG_CMD_PCI_ENUM
	426	case 'e':
	427	break;
	428	#endif
c609719b WD	429	default: /* scan bus */
	430	value = 1; /* short listing */
	431	bdf = 0; /* bus number */
	432	if (argc > 1) {
	433	if (argv[argc-1][0] == 'l') {
	434	value = 0;
	435	argc--;
	436	}
	437	if (argc > 1)
	438	bdf = simple_strtoul(argv[1], NULL, 16);
	439	}
	440	pciinfo(bdf, value);
	441	return 0;
	442	}
	443
	444	switch (argv[1][0]) {
	445	case 'h': /* header */
	446	pci_header_show(bdf);
	447	return 0;
	448	case 'd': /* display */
	449	return pci_cfg_display(bdf, addr, size, value);
96d61603 JS	450	#ifdef CONFIG_CMD_PCI_ENUM
	451	case 'e':
	452	pci_init();
	453	return 0;
	454	#endif
c609719b WD	455	case 'n': /* next */
	456	if (argc < 4)
	457	goto usage;
	458	return pci_cfg_modify(bdf, addr, size, value, 0);
	459	case 'm': /* modify */
	460	if (argc < 4)
	461	goto usage;
	462	return pci_cfg_modify(bdf, addr, size, value, 1);
	463	case 'w': /* write */
	464	if (argc < 5)
	465	goto usage;
	466	return pci_cfg_write(bdf, addr, size, value);
	467	}
	468
	469	return 1;
	470	usage:
4c12eeb8	471	return CMD_RET_USAGE;
c609719b WD	472	}
c609719b WD	473
8bde7f77 WD	474	/***************************************************/
8bde7f77 WD	475
088f1b19 KP	476	#ifdef CONFIG_SYS_LONGHELP
088f1b19 KP	477	static char pci_help_text[] =
8bde7f77 WD	478	"[bus] [long]\n"
8bde7f77 WD	479	" - short or long list of PCI devices on bus 'bus'\n"
96d61603 JS	480	#ifdef CONFIG_CMD_PCI_ENUM
	481	"pci enum\n"
	482	" - re-enumerate PCI buses\n"
	483	#endif
8bde7f77 WD	484	"pci header b.d.f\n"
	485	" - show header of PCI device 'bus.device.function'\n"
	486	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	487	" - display PCI configuration space (CFG)\n"
	488	"pci next[.b, .w, .l] b.d.f address\n"
	489	" - modify, read and keep CFG address\n"
	490	"pci modify[.b, .w, .l] b.d.f address\n"
	491	" - modify, auto increment CFG address\n"
	492	"pci write[.b, .w, .l] b.d.f address value\n"
088f1b19 KP	493	" - write to CFG address";
	494	#endif
	495
	496	U_BOOT_CMD(
	497	pci, 5, 1, do_pci,
	498	"list and access PCI Configuration Space", pci_help_text
8bde7f77	499	);