[people/ms/u-boot.git] / common / cmd_reginfo.c

/*
 * (C) Copyright 2000
 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <cmd_boot.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#elif defined (CONFIG_405GP)
#include <asm/processor.h>
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
#endif
#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)

int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_8xx)
	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	volatile sit8xx_t *timers = &immap->im_sit;

	/* Hopefully more PowerPC  knowledgable people will add code to display
	 * other useful registers
	 */

	printf("\nSystem Configuration registers\n");

	printf("\tIMMR\t0x%08X\n", get_immr(0));

	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

	printf("\tSWT\t0x%08X",    sysconf->sc_swt);
	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
		sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
		sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
		sysconf->sc_tesr, sysconf->sc_sdcr);

	printf("Memory Controller Registers\n");

	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	printf("\n");

	printf("\tmamr\t0x%08X\tmbmr\t0x%08X \n",
		memctl->memc_mamr, memctl->memc_mbmr );
	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
		memctl->memc_mstat, memctl->memc_mptpr );
	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

	printf("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
		timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	/*
	 * May be some CPM info here?
	 */

/* DBU[dave@cray.com]   For the CRAY-L1, but should be generically 405gp */
#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
	printf("\n405GP registers; MSR=%x\n",mfmsr());
		printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr    uicsrs   uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
	mfdcr(uicsr),
	mfdcr(uicsrs),
	mfdcr(uicer),
	mfdcr(uiccr),
	mfdcr(uicpr),
	mfdcr(uictr),
	mfdcr(uicmsr),
	mfdcr(uicvr),
	mfdcr(uicvcr));

	printf ("\nMemory (SDRAM) Configuration\n"
"besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");

	mtdcr(memcfga,mem_besra); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsa);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrb); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsb); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_bear); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n"
"mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb2cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb3cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_sdtr1); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_ecccf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_eccerr); 	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n\n"
"DMA Channels\n"
"dmasr    dmasgc   dmaadr\n"						"%08x %08x %08x\n"
"dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"	"%08x %08x %08x %08x %08x\n"
"dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"	"%08x %08x %08x %08x %08x\n",
mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));

	printf (
"dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"	"%08x %08x %08x %08x %08x\n"
"dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"	"%08x %08x %08x %08x %08x\n",
mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );

	printf ("\n"
"External Bus\n"
"pbear    pbesr0   pbesr1   epcr\n");
	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr0); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));

	printf ("\n"
"pb0cr    pb0ap    pb1cr    bp1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));

	printf ("\n"
"pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7ap); 	printf ("%08x ", mfdcr(ebccfgd));

	printf ("\n\n");
#elif defined(CONFIG_5xx)

	volatile immap_t     	*immap  = (immap_t *)CFG_IMMR;
	volatile memctl5xx_t	*memctl = &immap->im_memctl;
	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
	volatile sit5xx_t	*timers = &immap->im_sit;
	volatile car5xx_t	*car = &immap->im_clkrst;
	volatile uimb5xx_t	*uimb = &immap->im_uimb;

	printf("\nSystem Configuration registers\n");
	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

	printf("\nMemory Controller Registers\n");
	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

	printf("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	printf("\nClocks and Reset\n");
	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

	printf("\nU-Bus to IMB3 Bus Interface\n");
	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	printf ("\n\n");
#endif /* CONFIG_5xx */
	return 0;
}

#endif	/* CONFIG_COMMANDS & CFG_CMD_REGINFO */
Commit	Line	Data
e887afc9 WD	1	/*
	2	* (C) Copyright 2000
	3	* Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
	26	#include <cmd_boot.h>
	27	#if defined(CONFIG_8xx)
	28	#include <mpc8xx.h>
	29	#elif defined (CONFIG_405GP)
	30	#include <asm/processor.h>
0db5bca8 WD	31	#elif defined (CONFIG_5xx)
0db5bca8 WD	32	#include <mpc5xx.h>
e887afc9 WD	33	#endif
	34	#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
	35
	36	int do_reginfo (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	37	{
	38	#if defined(CONFIG_8xx)
	39	volatile immap_t immap = (immap_t )CFG_IMMR;
	40	volatile memctl8xx_t *memctl = &immap->im_memctl;
	41	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	42	volatile sit8xx_t *timers = &immap->im_sit;
	43
	44	/* Hopefully more PowerPC knowledgable people will add code to display
	45	* other useful registers
	46	*/
	47
	48	printf("\nSystem Configuration registers\n");
	49
	50	printf("\tIMMR\t0x%08X\n", get_immr(0));
	51
	52	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	53	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
	54
	55	printf("\tSWT\t0x%08X", sysconf->sc_swt);
	56	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
	57
	58	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
	59	sysconf->sc_sipend, sysconf->sc_simask);
	60	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
	61	sysconf->sc_siel, sysconf->sc_sivec);
	62	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
	63	sysconf->sc_tesr, sysconf->sc_sdcr);
	64
	65	printf("Memory Controller Registers\n");
	66
	67	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	68	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	69	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	70	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	71	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	72	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	73	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	74	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	75	printf("\n");
	76
	77	printf("\tmamr\t0x%08X\tmbmr\t0x%08X \n",
	78	memctl->memc_mamr, memctl->memc_mbmr );
	79	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
	80	memctl->memc_mstat, memctl->memc_mptpr );
	81	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
	82
	83	printf("\nSystem Integration Timers\n");
	84	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
	85	timers->sit_tbscr, timers->sit_rtcsc);
	86	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	87
	88	/*
	89	* May be some CPM info here?
	90	*/
	91
	92	/* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */
b867d705	93	#elif defined (CONFIG_405GP) \|\| defined(CONFIG_405EP)
e887afc9 WD	94	printf("\n405GP registers; MSR=%x\n",mfmsr());
	95	printf ("\nUniversal Interrupt Controller Regs\n"
	96	"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
	97	"\n"
	98	"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
	99	mfdcr(uicsr),
	100	mfdcr(uicsrs),
	101	mfdcr(uicer),
	102	mfdcr(uiccr),
	103	mfdcr(uicpr),
	104	mfdcr(uictr),
	105	mfdcr(uicmsr),
	106	mfdcr(uicvr),
	107	mfdcr(uicvcr));
	108
	109	printf ("\nMemory (SDRAM) Configuration\n"
	110	"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
	111
	112	mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
	113	mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
	114	mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
	115	mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
	116	mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
	117	mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
	118	mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
	119	mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
	120
	121	printf ("\n"
	122	"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
	123	mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
	124	mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
	125	mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
	126	mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
	127	mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
	128	mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
	129	mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
	130
	131	printf ("\n\n"
	132	"DMA Channels\n"
	133	"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
	134	"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
	135	"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
	136	mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
	137	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	138	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
	139
	140	printf (
	141	"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
	142	"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
	143	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	144	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
	145
	146	printf ("\n"
	147	"External Bus\n"
	148	"pbear pbesr0 pbesr1 epcr\n");
	149	mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
	150	mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
	151	mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
	152	mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
	153
	154	printf ("\n"
	155	"pb0cr pb0ap pb1cr bp1ap pb2cr pb2ap pb3cr pb3ap\n");
	156	mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
	157	mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
158	mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
159	mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
160	mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
161	mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
162	mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
163	mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
164
165	printf ("\n"
166	"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
167	mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
168	mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
169	mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
170	mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
171	mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
172	mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
173	mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
174	mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
175
176	printf ("\n\n");
0db5bca8	177	#elif defined(CONFIG_5xx)
e887afc9	178
0db5bca8 WD	179	volatile immap_t immap = (immap_t )CFG_IMMR;
	180	volatile memctl5xx_t *memctl = &immap->im_memctl;
	181	volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
	182	volatile sit5xx_t *timers = &immap->im_sit;
	183	volatile car5xx_t *car = &immap->im_clkrst;
	184	volatile uimb5xx_t *uimb = &immap->im_uimb;
	185
	186	printf("\nSystem Configuration registers\n");
	187	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	188	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	189	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	190	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	191	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
	192
	193	printf("\nMemory Controller Registers\n");
	194	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	195	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	196	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	197	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	198	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	199	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
	200
	201	printf("\nSystem Integration Timers\n");
	202	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	203	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	204
	205	printf("\nClocks and Reset\n");
	206	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
	207
	208	printf("\nU-Bus to IMB3 Bus Interface\n");
	209	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	210	printf ("\n\n");
	211	#endif /* CONFIG_5xx */
e887afc9 WD	212	return 0;
	213	}
	214
0db5bca8	215	#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */