[people/ms/u-boot.git] / common / cmd_reginfo.c

/*
 * (C) Copyright 2000
 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#elif defined (CONFIG_4xx)
extern void ppc4xx_reginfo(void);
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
#elif defined (CONFIG_MPC5200)
#include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#elif defined(CONFIG_MPC85xx)
extern void mpc85xx_reginfo(void);
#endif

int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_8xx)
	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	volatile sit8xx_t *timers = &immap->im_sit;

	/* Hopefully more PowerPC  knowledgable people will add code to display
	 * other useful registers
	 */

	printf ("\nSystem Configuration registers\n"

		"\tIMMR\t0x%08X\n", get_immr(0));

	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

	printf("\tSWT\t0x%08X",    sysconf->sc_swt);
	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
		sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
		sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
		sysconf->sc_tesr, sysconf->sc_sdcr);

	printf ("Memory Controller Registers\n"

		"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	printf ("\n"
		"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
		memctl->memc_mamr, memctl->memc_mbmr );
	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
		memctl->memc_mstat, memctl->memc_mptpr );
	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

	printf ("\nSystem Integration Timers\n"
		"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
		timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	/*
	 * May be some CPM info here?
	 */

#elif defined (CONFIG_4xx)
	ppc4xx_reginfo();
#elif defined(CONFIG_5xx)

	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl5xx_t	*memctl = &immap->im_memctl;
	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
	volatile sit5xx_t	*timers = &immap->im_sit;
	volatile car5xx_t	*car = &immap->im_clkrst;
	volatile uimb5xx_t	*uimb = &immap->im_uimb;

	puts ("\nSystem Configuration registers\n");
	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

	puts ("\nMemory Controller Registers\n");
	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

	puts ("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	puts ("\nClocks and Reset\n");
	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

	puts ("\nU-Bus to IMB3 Bus Interface\n");
	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	puts ("\n\n");

#elif defined(CONFIG_MPC5200)
	puts ("\nMPC5200 registers\n");
	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
	puts ("Memory map registers\n");
	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS0_START,
		*(volatile ulong*)MPC5XXX_CS0_STOP,
		*(volatile ulong*)MPC5XXX_CS0_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS1_START,
		*(volatile ulong*)MPC5XXX_CS1_STOP,
		*(volatile ulong*)MPC5XXX_CS1_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS2_START,
		*(volatile ulong*)MPC5XXX_CS2_STOP,
		*(volatile ulong*)MPC5XXX_CS2_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS3_START,
		*(volatile ulong*)MPC5XXX_CS3_STOP,
		*(volatile ulong*)MPC5XXX_CS3_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS4_START,
		*(volatile ulong*)MPC5XXX_CS4_STOP,
		*(volatile ulong*)MPC5XXX_CS4_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS5_START,
		*(volatile ulong*)MPC5XXX_CS5_STOP,
		*(volatile ulong*)MPC5XXX_CS5_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS6_START,
		*(volatile ulong*)MPC5XXX_CS6_STOP,
		*(volatile ulong*)MPC5XXX_CS6_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS7_START,
		*(volatile ulong*)MPC5XXX_CS7_STOP,
		*(volatile ulong*)MPC5XXX_CS7_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_BOOTCS_START,
		*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
		*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
	printf ("\tSDRAMCS0: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
	printf ("\tSDRAMCS1: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
	mpc86xx_reginfo();

#elif defined(CONFIG_MPC85xx)
	mpc85xx_reginfo();

#elif defined(CONFIG_BLACKFIN)
	puts("\nSystem Configuration registers\n");

	puts("\nPLL Registers\n");
	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
	printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
		bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
	printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());

	puts("\nEBIU AMC Registers\n");
	printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
	printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
		bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
	printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
		bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
	printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
		bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif

# ifdef EBIU_RSTCTL
	puts("\nEBIU DDR Registers\n");
	printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
		bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
	printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
		bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
	printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
		bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
	printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
		bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
	puts("\nEBIU SDC Registers\n");
	printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
		bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif

#endif /* CONFIG_BLACKFIN */

	return 0;
}

 /**************************************************/

#if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
	reginfo,	2,	1,	do_reginfo,
	"print register information",
	""
);
#endif
Commit	Line	Data
e887afc9 WD	1	/*
	2	* (C) Copyright 2000
	3	* Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
e887afc9 WD	26	#if defined(CONFIG_8xx)
e887afc9 WD	27	#include <mpc8xx.h>
78d2a641 NG	28	#elif defined (CONFIG_4xx)
78d2a641 NG	29	extern void ppc4xx_reginfo(void);
0db5bca8 WD	30	#elif defined (CONFIG_5xx)
0db5bca8 WD	31	#include <mpc5xx.h>
56523f12 WD	32	#elif defined (CONFIG_MPC5200)
56523f12 WD	33	#include <mpc5xxx.h>
4f93f8b1 BB	34	#elif defined (CONFIG_MPC86xx)
4f93f8b1 BB	35	extern void mpc86xx_reginfo(void);
199e262e BB	36	#elif defined(CONFIG_MPC85xx)
199e262e BB	37	extern void mpc85xx_reginfo(void);
e887afc9	38	#endif
65c450b4	39
54841ab5	40	int do_reginfo (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
e887afc9 WD	41	{
e887afc9 WD	42	#if defined(CONFIG_8xx)
6d0f6bcf	43	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
e887afc9 WD	44	volatile memctl8xx_t *memctl = &immap->im_memctl;
	45	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	46	volatile sit8xx_t *timers = &immap->im_sit;
	47
	48	/* Hopefully more PowerPC knowledgable people will add code to display
	49	* other useful registers
	50	*/
	51
4b9206ed	52	printf ("\nSystem Configuration registers\n"
e887afc9	53
4b9206ed	54	"\tIMMR\t0x%08X\n", get_immr(0));
e887afc9 WD	55
	56	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	57	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
	58
	59	printf("\tSWT\t0x%08X", sysconf->sc_swt);
	60	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
	61
	62	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
	63	sysconf->sc_sipend, sysconf->sc_simask);
	64	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
	65	sysconf->sc_siel, sysconf->sc_sivec);
	66	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
	67	sysconf->sc_tesr, sysconf->sc_sdcr);
	68
4b9206ed	69	printf ("Memory Controller Registers\n"
e887afc9	70
4b9206ed	71	"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
e887afc9 WD	72	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	73	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	74	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	75	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	76	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	77	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	78	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
4b9206ed WD	79	printf ("\n"
4b9206ed WD	80	"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
e887afc9 WD	81	memctl->memc_mamr, memctl->memc_mbmr );
	82	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
	83	memctl->memc_mstat, memctl->memc_mptpr );
	84	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
	85
4b9206ed WD	86	printf ("\nSystem Integration Timers\n"
4b9206ed WD	87	"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
e887afc9 WD	88	timers->sit_tbscr, timers->sit_rtcsc);
	89	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	90
	91	/*
	92	* May be some CPM info here?
	93	*/
	94
78d2a641 NG	95	#elif defined (CONFIG_4xx)
78d2a641 NG	96	ppc4xx_reginfo();
0db5bca8	97	#elif defined(CONFIG_5xx)
e887afc9	98
6d0f6bcf	99	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
0db5bca8 WD	100	volatile memctl5xx_t *memctl = &immap->im_memctl;
	101	volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
	102	volatile sit5xx_t *timers = &immap->im_sit;
	103	volatile car5xx_t *car = &immap->im_clkrst;
	104	volatile uimb5xx_t *uimb = &immap->im_uimb;
	105
4b9206ed	106	puts ("\nSystem Configuration registers\n");
0db5bca8 WD	107	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	108	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	109	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	110	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	111	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
	112
4b9206ed	113	puts ("\nMemory Controller Registers\n");
0db5bca8 WD	114	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	115	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	116	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	117	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	118	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	119	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
	120
4b9206ed	121	puts ("\nSystem Integration Timers\n");
0db5bca8 WD	122	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	123	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	124
4b9206ed	125	puts ("\nClocks and Reset\n");
0db5bca8 WD	126	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
0db5bca8 WD	127
4b9206ed	128	puts ("\nU-Bus to IMB3 Bus Interface\n");
0db5bca8	129	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
4b9206ed	130	puts ("\n\n");
56523f12 WD	131
	132	#elif defined(CONFIG_MPC5200)
	133	puts ("\nMPC5200 registers\n");
6d0f6bcf	134	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
56523f12	135	puts ("Memory map registers\n");
9b55a253	136	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	137	(volatile ulong)MPC5XXX_CS0_START,
	138	(volatile ulong)MPC5XXX_CS0_STOP,
	139	(volatile ulong)MPC5XXX_CS0_CFG,
	140	((volatile ulong)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
9b55a253	141	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	142	(volatile ulong)MPC5XXX_CS1_START,
	143	(volatile ulong)MPC5XXX_CS1_STOP,
	144	(volatile ulong)MPC5XXX_CS1_CFG,
	145	((volatile ulong)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
9b55a253	146	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	147	(volatile ulong)MPC5XXX_CS2_START,
	148	(volatile ulong)MPC5XXX_CS2_STOP,
	149	(volatile ulong)MPC5XXX_CS2_CFG,
	150	((volatile ulong)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
9b55a253	151	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	152	(volatile ulong)MPC5XXX_CS3_START,
	153	(volatile ulong)MPC5XXX_CS3_STOP,
	154	(volatile ulong)MPC5XXX_CS3_CFG,
	155	((volatile ulong)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
9b55a253	156	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	157	(volatile ulong)MPC5XXX_CS4_START,
	158	(volatile ulong)MPC5XXX_CS4_STOP,
	159	(volatile ulong)MPC5XXX_CS4_CFG,
	160	((volatile ulong)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
9b55a253	161	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	162	(volatile ulong)MPC5XXX_CS5_START,
	163	(volatile ulong)MPC5XXX_CS5_STOP,
	164	(volatile ulong)MPC5XXX_CS5_CFG,
	165	((volatile ulong)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
9b55a253	166	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	167	(volatile ulong)MPC5XXX_CS6_START,
	168	(volatile ulong)MPC5XXX_CS6_STOP,
	169	(volatile ulong)MPC5XXX_CS6_CFG,
	170	((volatile ulong)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
9b55a253	171	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	172	(volatile ulong)MPC5XXX_CS7_START,
	173	(volatile ulong)MPC5XXX_CS7_STOP,
	174	(volatile ulong)MPC5XXX_CS7_CFG,
	175	((volatile ulong)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
9b55a253	176	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	177	(volatile ulong)MPC5XXX_BOOTCS_START,
	178	(volatile ulong)MPC5XXX_BOOTCS_STOP,
	179	(volatile ulong)MPC5XXX_BOOTCS_CFG,
	180	((volatile ulong)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
9b55a253	181	printf ("\tSDRAMCS0: %08lX\n",
56523f12	182	(volatile ulong)MPC5XXX_SDRAM_CS0CFG);
9b55a253	183	printf ("\tSDRAMCS1: %08lX\n",
56523f12	184	(volatile ulong)MPC5XXX_SDRAM_CS1CFG);
4f93f8b1 BB	185	#elif defined(CONFIG_MPC86xx)
4f93f8b1 BB	186	mpc86xx_reginfo();
97c26e00	187
199e262e BB	188	#elif defined(CONFIG_MPC85xx)
	189	mpc85xx_reginfo();
	190
97c26e00 MF	191	#elif defined(CONFIG_BLACKFIN)
	192	puts("\nSystem Configuration registers\n");
	193
	194	puts("\nPLL Registers\n");
	195	printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
	196	bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
	197	printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
	198	bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
	199	printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
	200
	201	puts("\nEBIU AMC Registers\n");
	202	printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
	203	printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
	204	bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
	205	# ifdef EBIU_MODE
	206	printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
	207	bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
	208	printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
	209	bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
	210	# endif
	211
	212	# ifdef EBIU_RSTCTL
	213	puts("\nEBIU DDR Registers\n");
	214	printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
	215	bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
	216	printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
	217	bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
	218	printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
	219	bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
	220	printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
	221	bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
	222	# else
	223	puts("\nEBIU SDC Registers\n");
	224	printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
	225	bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
	226	printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
	227	bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
	228	# endif
	229
9e04a813	230	#endif /* CONFIG_BLACKFIN */
4f93f8b1	231
e887afc9 WD	232	return 0;
	233	}
	234
8bde7f77 WD	235	/**************************************************/
8bde7f77 WD	236
97c26e00	237	#if defined(CONFIG_CMD_REGINFO)
0d498393	238	U_BOOT_CMD(
53677ef1	239	reginfo, 2, 1, do_reginfo,
2fb2604d	240	"print register information",
a89c33db	241	""
8bde7f77 WD	242	);
8bde7f77 WD	243	#endif